WO2000014681A2 - Puce de connexion a structure superficielle de raccordement specifique - Google Patents

Puce de connexion a structure superficielle de raccordement specifique Download PDF

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Publication number
WO2000014681A2
WO2000014681A2 PCT/EP1999/006471 EP9906471W WO0014681A2 WO 2000014681 A2 WO2000014681 A2 WO 2000014681A2 EP 9906471 W EP9906471 W EP 9906471W WO 0014681 A2 WO0014681 A2 WO 0014681A2
Authority
WO
WIPO (PCT)
Prior art keywords
circuit chip
connection
circuit
integrated circuit
substrate
Prior art date
Application number
PCT/EP1999/006471
Other languages
German (de)
English (en)
Other versions
WO2000014681A3 (fr
Inventor
Andreas Plettner
Karl Haberger
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO2000014681A2 publication Critical patent/WO2000014681A2/fr
Publication of WO2000014681A3 publication Critical patent/WO2000014681A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to circuit chips and the arrangement of at least two pads on the same and in particular to ultra-thin circuit chips which are suitable for the construction of flat chip cards or electronic labels.
  • Disposable electronics require inexpensive chips or micro modules in ecologically acceptable carriers.
  • a contactless module which consists of an integrated circuit, ie a circuit chip, and an antenna coil
  • Such an electronic label requires a particularly flat design of the contactless module with a thickness application that is as small as possible, so as not to impair paper technology processes, such as printing, laminating, etc.
  • other thin, flexible substrates such as polymer films can also be used to produce electronic labels.
  • the area of application for electronic labels ranges from goods labeling to tickets to security papers and beyond to the domain of today's chip cards.
  • a number of special requirements must be made of the contacting technology for such thin chips. These refer to a low price, a low use of materials, easy contactability and above all a low overall height. The latter is essential if all advantages of thin chip technology are to be used.
  • peripheral circuitry In contrast to individual and, above all, power components, integrated circuits are generally connected to the peripheral circuitry by means of contacts which are planar in one plane, namely the useful surface of the semiconductor.
  • this peripheral circuitry is formed by the contact pins of a housing.
  • this peripheral circuitry is formed, for example, by conductor tracks on a substrate, which essentially corresponds to a conventional copper-clad printed circuit board.
  • current contacting techniques see for example the article "Packing trends: high-tech in the smallest format" H. Reichl u. a., Components, IC packaging, electronics 12/1998, referenced.
  • flip-chip bonding techniques are described there, in which the assembly of the chip and the contacting take place simultaneously.
  • the possibility of thin-film wiring is also described there.
  • the use of such a flip chip method for contactless chip cards is also described in DE-A-19639902.
  • DE-C-4430812 describes a method for producing an ion-sensitive field-effect transistor with a rear-side contact. A method is described there to implement freely selectable vertical contacts between the component level and the rear side metallization. The component level is then contacted exclusively from the rear, so that the metallization is only on the side remote from the sample liquid, which increases the short-circuit protection. All known contacting methods are disadvantageous in the production of ultra-flat chip card modules or electronic labels, since on the one hand exact adjustment methods are required and on the other hand the contacts generated prevent a further reduction in the thickness of such modules.
  • planar contact arrangement of conventional integrated circuits is based on their planar manufacture. This is based on the one-sided access to the surface and its structuring by means of lithographic processes.
  • Conventional integrated circuits generally have from a few 10 in the case of memories to several 100 connections in the case of complex logic components, which are usually arranged on the edge of the integrated circuits as so-called connection pads. Typical pad dimensions are in the range of 70 ⁇ m in order to keep the requirements for the adjustment accuracy during testing and contacting within tolerable limits.
  • Circuit chips suitable for disposable electronics largely have different requirements.
  • integrated circuits for transponder modules as the only peripheral circuitry, have a large-area inductance, ie an antenna coil and / or a capacitance, ie a dipole.
  • the thickness of these external connection elements is typically a few micrometers.
  • the integrated circuit draws its operating energy from an external high-frequency field and exchanges data with this high-frequency field. In the simplest case, this data exchange takes place by means of a data memory-programmed attenuation of the antenna circuit.
  • the antenna circuit forms a resonance circuit through a transistor that opens and closes and thus dampens the resonant circuit.
  • the object of the present invention is to create a circuit chip with a specific pad arrangement, which enables the simple and inexpensive production of ultra-flat chip cards or electronic labels.
  • the present invention provides a circuit chip consisting of a semiconducting substrate with a front and a back, an integrated circuit with a in the front of the semiconducting substrate A plurality of components is defined.
  • the integrated circuit has two connections which serve for signal coupling or signal coupling and can be interchanged without impairing the function of the integrated circuit.
  • the circuit chip has only two pads, one on the front of the semiconducting substrate and one on the back thereof, each of the pads being connected to one of the interchangeable terminals.
  • the integrated circuit has two connections for signal coupling or signal coupling and interchangeable without impairing the function of the integrated circuit, one of which is connected to the connection pad arranged on the front side, while the other of these is connected to the connection pad arranged on the rear side connected is.
  • the two pads are therefore considered to be electrically equivalent.
  • the circuit chip according to the invention When used for a transponder module, it therefore has only two connection areas, one of which is arranged on the front side and essentially covers it, while the other is arranged on the rear side and essentially covers it.
  • the metallic contacts are preferably made over a large area, taking up a maximum of the entire chip area. This results in a very simple and therefore imprecise adjustment and contacting with low contact resistance.
  • a low contact resistance is required to conduct the relatively high currents in the resonant circuit in the case of resonance. These determine the coil quality, which should be as high as possible in the sense of a narrow-band resonance.
  • connection surfaces according to the invention enables, for example, a connection that is as flat as possible when using the circuit chip in a transponder module Connection surfaces with the peripheral components, whereby, as stated above, two connections are usually sufficient for a transponder module in order to ensure both the energy supply and the bidirectional data flow.
  • This enables installation in or between thin substrates.
  • the construction of the circuit chip according to the invention enables a very low-mass micro module, which plays a role in the material costs and in particular in the disposal in the case of disposable electronics.
  • connection area on the front side and a connection area on the rear side of the circuit chip maximizes the area occupied by the connection areas, so that the bonding process can be carried out both in a simplified and in an accelerated manner.
  • the two contacts are designed to be electrically equivalent, so that the installation orientation with regard to the alignment of the upper side or the lower side is arbitrary.
  • large-area metallizations on the front or the back can take on further tasks, for example as light protection, as shielding, as equipotential bonding, as corrosion protection, as an attachment surface for magnetic or electrostatic handling, etc.
  • connection surfaces located on different main surfaces eliminate the risk of short circuits due to conductive adhesive and the like flowing into one another.
  • the circuit chip according to the invention is particularly suitable for installation in an insulation substrate, such that both main surfaces of the chip are essentially flush with it the main surfaces of the insulation substrate.
  • a full-area metallization can preferably be provided on the underside of the insulation substrate, as a result of which contact is made with the connection area provided on the underside of the circuit chip.
  • the contacting of the connection surface arranged on the upper side of the circuit chip can take place by means of a structured metallization, which is applied to this surface of the insulation substrate and the circuit chip.
  • FIG. 1 schematically shows a cross-sectional view of a circuit chip according to the invention
  • FIG. 2 shows a schematic cross-sectional view of a transponder module which contains a circuit chip according to the invention
  • Fig. 3 is a schematic representation illustrating how a metallization can be performed on the back of the circuit chip.
  • FIG. 1 a simple embodiment of a circuit chip according to the invention is shown schematically.
  • An integrated circuit 4 with a plurality of components is formed in the useful side of a semiconducting substrate 2.
  • the semiconducting substrate 2 has a thickness of 10 ⁇ m, for example.
  • Thin passivation layers 6 and 8 are applied to the top and bottom of the semiconducting substrate 2, respectively.
  • a metal layer 10 and 12 with a thickness of typically 0.5 ⁇ m is provided on each of these passivation layers 6 and 8.
  • the metal layer 10 is connected to the integrated circuit in the semiconducting substrate 2 via a conductive connection 14.
  • the metal layer 12 is on an arbitrary bige suitable way connected to the integrated circuit 4, as shown schematically by a connection 16 shown in dashed lines.
  • the metal layers 10 and 12 are preferably connected to two connections of the integrated circuit serving for signal coupling or signal coupling, which are interchangeable without impairing the integrated circuit, so that the circuit chip can be contacted externally in any orientation by means of the connection surfaces 10 and 12.
  • the passivation layers 6 and 8 serve to isolate the semiconductor substrate 2 from the connection areas which are formed by the metal layers 10 and 12. It should be noted that the passivation layer 8 is not necessarily present, as will be explained in more detail below.
  • the metal layers 10 and 12 can consist of any metal according to the specifications of the semiconductor technology and can be produced by means of the methods used there. Exemplary metals are Al, W, Cr, Ti, TiN, Cu or Au, as well as alloys and combinations thereof.
  • the conductive connection shown schematically at 16 in FIG. 1 can be implemented in different ways. For example, it can be implemented through a plated-through hole up to a suitably doped region of the integrated circuit. Alternatively, this conductive connection can be implemented via conductive structures provided on at least one side surface of the semiconducting substrate 2, two multilayer metallizations then being able to be provided on the useful side of the semiconductor substrate, which are used to connect the conductive structures provided on the side surface of the semiconductor substrate to a corresponding connection area serve the integrated circuit.
  • a plated-through hole for the conductive connection of the metal layer 12 can also be used up to a metallization level of a plurality of metallization levels on the useful side of the semiconducting substrate 2 are performed.
  • one or more contact holes are first etched, the depth of which corresponds to the later chip thickness. If a galvanic separation is to take place between the semiconducting substrate 2 and the rear side metallization 12, plasma oxide is subsequently deposited isotropically in the contact hole for lateral isolation. This oxide is subsequently anisotropically etched at the bottom of the hole, whereupon the hole is filled with a metal, preferably tungsten.
  • the semiconducting substrate is preferably still thinned in the wafer assembly until the semiconducting substrate has the desired thickness and the contact pin is exposed.
  • the back is then metallized with one of the metals mentioned above. This method is particularly suitable for extremely thin chips, while thick chips are less suitable for this method due to the limited aspect ratio that can be achieved by etching.
  • Another possibility is to completely dispense with an additional galvanic isolation between the rear side metallization 12 and the semiconducting substrate 2.
  • the passivation layer 8 on the back of the semiconducting substrate 2 is unnecessary.
  • the rear side metallization 12 is connected directly to the substrate, care being taken to ensure that a sufficiently good ohmic contact is established between the metallization layer 12 and the semiconducting substrate.
  • processing must take place on thin and mechanically no longer manageable wafers, this processing possibly involving temperature steps up to 450 ° C, which are not easily tolerated by thin wafers and in particular the components contained therein .
  • Ion implantation combined with a short-term annealing process can be used as a method for achieving good ohmic contacts on the back of thinned wafers.
  • RTP short-term annealing process
  • Such more or less transient processes can also be carried out on a
  • thin chip wafers attached to a handling wafer by means of organic adhesives can be used advantageously. After this processing, the backside metallization is then applied.
  • the rear side metallization 12 is connected directly to the semiconducting substrate 2, suitable insulation of the semiconductor substrate 2 from the integrated circuit 4 must of course be provided. Such isolation can expediently be implemented by blocking diode paths to the CMOS wells of the integrated circuit that are usually used.
  • a conductive connection of the rear side metallization 12 to the integrated circuit 4 could be realized by the provision of suitably doped conductive areas.
  • FIG. 2 shows a transponder module that contains a circuit chip according to the invention.
  • the circuit chip 20 is introduced into a recess in an insulation substrate 22 such that both main surfaces of the circuit chip 20 are essentially flush with the main surfaces of the insulation substrate 22.
  • a metallization layer 24 is preferably provided over the entire area on the rear side of the insulation substrate 22.
  • a structured metallization 26, which defines an antenna device in the form of a coil, is provided on the front side of the insulation substrate 22 and on parts of the circuit chip 20.
  • a connection end 28 of the coil is conductively connected to the front contact (not shown in FIG. 2) of the circuit chip 20.
  • a second connection end 30 of the structured metallization 26 is connected via a via 32 through the insulation substrate 22 to the metallization layer 24 provided on the rear side of the insulation substrate 22.
  • the metallization layer 24 contacts the rear side connection area (not shown in FIG. 2) of the circuit chip 20, so that this rear side connection is connected via the metallization layer 24 and the via 32 to the second connection end 30 of the structured metallization layer.
  • the circuit chip according to the present invention enables extremely simple contacting and moreover enables the creation of a flat transponder module with a thickness between 10 and 50 ⁇ m, possibly below up to 5 ⁇ m.
  • the contacting between the connection end 28 of the structured metallization 26 and the contacting between the metallization layer 24 and the circuit chip 20 can be carried out by any known contacting method.
  • FIG. 3 shows a schematic illustration of how a conductive structure can already be carried out on the edges of a circuit chip during the production of the circuit chips in order to produce a conductive connection to the rear side.
  • 3 shows two semiconductor chips 40 which are applied to an auxiliary carrier 42.
  • the integrated circuits in the chips 40 shown in FIG. 3 are formed in the upper regions thereof.
  • the chips are separated by means of an anisotropic KOH etching, which causes the 54-degree edges shown.
  • An insulation 44 and subsequently a metallization 46 can now advantageously optionally be applied to these beveled edges in order to produce the aforementioned conductive connection to the rear of the circuit chip.
  • the coil area can be approximately 2 to 100 square centimeters.
  • the thickness of the module should be in a range of 10 ⁇ m. This small thickness enables sufficiently low resistance values even with the substrate doping of 10 14 cm -3 , which is common in CMOS technology, which leads to a specific resistance of 1 to 10 Ohmcm leads. This series resistance of the substrate enters into the resonant circuit resistance when it makes direct contact with the rear side connection area and must be as low as possible in order to ensure sufficient coil quality.
  • the circuit chip according to the present invention has a semiconducting substrate, which preferably consists of monocrystalline or polycrystalline silicon.
  • the semiconducting substrate can also be replaced by other semiconductors or compound semiconductors, e.g. Gallium arsenide.
  • the semiconducting substrate can be realized by semiconducting polymers.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne une puce de connexion comprenant un substrat semi-conducteur (2) avec une face avant et une face arrière. Un circuit intégré (4) comportant une pluralité de composants est défini dans la face avant du substrat semi-conducteur (2). Le circuit intégré (4) comprend deux connexions servant à l'injection ou à l'éjection de signaux, qui sont permutables sans que cela n'altère la fonction du circuit intégré (4). La puce de connexion ne présente que deux faces de connexion (10, 12) dont une (10) se situe sur la face avant du substrat semi-conducteur (2) et l'autre (12), sur la face arrière dudit substrat. Chacune de ces surfaces de connexion est reliée à une des connexions permutables.
PCT/EP1999/006471 1998-09-03 1999-09-02 Puce de connexion a structure superficielle de raccordement specifique WO2000014681A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1998140248 DE19840248A1 (de) 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung
DE19840248.1 1998-09-03

Publications (2)

Publication Number Publication Date
WO2000014681A2 true WO2000014681A2 (fr) 2000-03-16
WO2000014681A3 WO2000014681A3 (fr) 2000-06-02

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ID=7879729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1999/006471 WO2000014681A2 (fr) 1998-09-03 1999-09-02 Puce de connexion a structure superficielle de raccordement specifique

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DE (1) DE19840248A1 (fr)
WO (1) WO2000014681A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715675B1 (en) 2000-11-16 2004-04-06 Eldat Communication Ltd. Electronic shelf label systems and methods
DE10120408B4 (de) * 2001-04-25 2006-02-02 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip, elektronische Baugruppe aus gestapelten Halbleiterchips und Verfahren zu deren Herstellung
US7074509B2 (en) 2001-11-13 2006-07-11 Eldat Communication Ltd. Hydrogen generators for fuel cells
US6770186B2 (en) 2001-11-13 2004-08-03 Eldat Communication Ltd. Rechargeable hydrogen-fueled motor vehicle
DE10161043B4 (de) * 2001-12-12 2005-12-15 Infineon Technologies Ag Chipanordnung
DE10356367B4 (de) 2003-11-28 2009-06-10 Georg Bernitz Verfahren zur Herstellung eines Bauelements und Bauelement
DE10358282A1 (de) * 2003-12-12 2005-07-28 Georg Bernitz Bauelement und Verfahren zu dessen Herstellung
DE102006048583B3 (de) * 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Bauelement mit mehreren Kontaktflächen und ein Kontaktierungsverfahren
US8796137B2 (en) 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Citations (4)

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Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (nl) * 1992-05-20 1993-12-16 Nedap Nv Wegwerp chipkaart voor eenmalig gebruik.
DE19628504A1 (de) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Etikettenvorrichtung mit einer kapazitiv an eine Antenne gekoppelten integrierten Schaltung und Verfahren zu ihrer Herstellung
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer

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US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US4549247A (en) * 1980-11-21 1985-10-22 Gao Gesellschaft Fur Automation Und Organisation Mbh Carrier element for IC-modules
US5223851A (en) * 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device
US5374818A (en) * 1992-03-09 1994-12-20 Control Module Inc. Identification means with integral memory device
DE19654902C2 (de) * 1996-03-15 2000-02-03 David Finn Chipkarte

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (nl) * 1992-05-20 1993-12-16 Nedap Nv Wegwerp chipkaart voor eenmalig gebruik.
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer
DE19628504A1 (de) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Etikettenvorrichtung mit einer kapazitiv an eine Antenne gekoppelten integrierten Schaltung und Verfahren zu ihrer Herstellung

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Publication number Publication date
DE19840248A1 (de) 2000-03-16
WO2000014681A3 (fr) 2000-06-02

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