WO2000014681A3 - Puce de connexion a structure superficielle de raccordement specifique - Google Patents

Puce de connexion a structure superficielle de raccordement specifique Download PDF

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Publication number
WO2000014681A3
WO2000014681A3 PCT/EP1999/006471 EP9906471W WO0014681A3 WO 2000014681 A3 WO2000014681 A3 WO 2000014681A3 EP 9906471 W EP9906471 W EP 9906471W WO 0014681 A3 WO0014681 A3 WO 0014681A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit chip
connection area
specific connection
area configuration
integrated circuit
Prior art date
Application number
PCT/EP1999/006471
Other languages
German (de)
English (en)
Other versions
WO2000014681A2 (fr
Inventor
Andreas Plettner
Karl Haberger
Original Assignee
Fraunhofer Ges Forschung
Andreas Plettner
Karl Haberger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Andreas Plettner, Karl Haberger filed Critical Fraunhofer Ges Forschung
Publication of WO2000014681A2 publication Critical patent/WO2000014681A2/fr
Publication of WO2000014681A3 publication Critical patent/WO2000014681A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne une puce de connexion comprenant un substrat semi-conducteur (2) avec une face avant et une face arrière. Un circuit intégré (4) comportant une pluralité de composants est défini dans la face avant du substrat semi-conducteur (2). Le circuit intégré (4) comprend deux connexions servant à l'injection ou à l'éjection de signaux, qui sont permutables sans que cela n'altère la fonction du circuit intégré (4). La puce de connexion ne présente que deux faces de connexion (10, 12) dont une (10) se situe sur la face avant du substrat semi-conducteur (2) et l'autre (12), sur la face arrière dudit substrat. Chacune de ces surfaces de connexion est reliée à une des connexions permutables.
PCT/EP1999/006471 1998-09-03 1999-09-02 Puce de connexion a structure superficielle de raccordement specifique WO2000014681A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19840248.1 1998-09-03
DE1998140248 DE19840248A1 (de) 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung

Publications (2)

Publication Number Publication Date
WO2000014681A2 WO2000014681A2 (fr) 2000-03-16
WO2000014681A3 true WO2000014681A3 (fr) 2000-06-02

Family

ID=7879729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1999/006471 WO2000014681A2 (fr) 1998-09-03 1999-09-02 Puce de connexion a structure superficielle de raccordement specifique

Country Status (2)

Country Link
DE (1) DE19840248A1 (fr)
WO (1) WO2000014681A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715675B1 (en) 2000-11-16 2004-04-06 Eldat Communication Ltd. Electronic shelf label systems and methods
DE10120408B4 (de) 2001-04-25 2006-02-02 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip, elektronische Baugruppe aus gestapelten Halbleiterchips und Verfahren zu deren Herstellung
US7074509B2 (en) 2001-11-13 2006-07-11 Eldat Communication Ltd. Hydrogen generators for fuel cells
US6770186B2 (en) 2001-11-13 2004-08-03 Eldat Communication Ltd. Rechargeable hydrogen-fueled motor vehicle
DE10161043B4 (de) * 2001-12-12 2005-12-15 Infineon Technologies Ag Chipanordnung
DE10356367B4 (de) 2003-11-28 2009-06-10 Georg Bernitz Verfahren zur Herstellung eines Bauelements und Bauelement
DE10358282A1 (de) * 2003-12-12 2005-07-28 Georg Bernitz Bauelement und Verfahren zu dessen Herstellung
DE102006048583B3 (de) 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Bauelement mit mehreren Kontaktflächen und ein Kontaktierungsverfahren
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (nl) * 1992-05-20 1993-12-16 Nedap Nv Wegwerp chipkaart voor eenmalig gebruik.
DE19628504A1 (de) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Etikettenvorrichtung mit einer kapazitiv an eine Antenne gekoppelten integrierten Schaltung und Verfahren zu ihrer Herstellung
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US4549247A (en) * 1980-11-21 1985-10-22 Gao Gesellschaft Fur Automation Und Organisation Mbh Carrier element for IC-modules
US5223851A (en) * 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device
US5374818A (en) * 1992-03-09 1994-12-20 Control Module Inc. Identification means with integral memory device
DE19654902C2 (de) * 1996-03-15 2000-02-03 David Finn Chipkarte

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (nl) * 1992-05-20 1993-12-16 Nedap Nv Wegwerp chipkaart voor eenmalig gebruik.
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer
DE19628504A1 (de) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Etikettenvorrichtung mit einer kapazitiv an eine Antenne gekoppelten integrierten Schaltung und Verfahren zu ihrer Herstellung

Also Published As

Publication number Publication date
DE19840248A1 (de) 2000-03-16
WO2000014681A2 (fr) 2000-03-16

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