DE19740223C2 - Verfahren zum Prüfen einer Speichersteuerung - Google Patents

Verfahren zum Prüfen einer Speichersteuerung

Info

Publication number
DE19740223C2
DE19740223C2 DE19740223A DE19740223A DE19740223C2 DE 19740223 C2 DE19740223 C2 DE 19740223C2 DE 19740223 A DE19740223 A DE 19740223A DE 19740223 A DE19740223 A DE 19740223A DE 19740223 C2 DE19740223 C2 DE 19740223C2
Authority
DE
Germany
Prior art keywords
memory
sdram
signal
self
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19740223A
Other languages
German (de)
English (en)
Other versions
DE19740223A1 (de
Inventor
J Michael Andrewartha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE19740223A1 publication Critical patent/DE19740223A1/de
Application granted granted Critical
Publication of DE19740223C2 publication Critical patent/DE19740223C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE19740223A 1996-10-10 1997-09-12 Verfahren zum Prüfen einer Speichersteuerung Expired - Fee Related DE19740223C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/720,960 US5754557A (en) 1996-10-10 1996-10-10 Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller

Publications (2)

Publication Number Publication Date
DE19740223A1 DE19740223A1 (de) 1998-04-16
DE19740223C2 true DE19740223C2 (de) 2003-11-13

Family

ID=24895954

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19740223A Expired - Fee Related DE19740223C2 (de) 1996-10-10 1997-09-12 Verfahren zum Prüfen einer Speichersteuerung

Country Status (4)

Country Link
US (1) US5754557A (enExample)
JP (1) JP4083847B2 (enExample)
DE (1) DE19740223C2 (enExample)
GB (1) GB2320774B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999481A (en) * 1997-08-22 1999-12-07 Micron Technology, Inc. Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
JP2001290696A (ja) * 2000-04-07 2001-10-19 Minolta Co Ltd メモリ基板
JP4689087B2 (ja) * 2000-08-22 2011-05-25 キヤノン株式会社 情報処理装置及び省電力移行制御方法
US6901359B1 (en) * 2000-09-06 2005-05-31 Quickturn Design Systems, Inc. High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory
US7236987B1 (en) 2003-02-28 2007-06-26 Sun Microsystems Inc. Systems and methods for providing a storage virtualization environment
US7447939B1 (en) * 2003-02-28 2008-11-04 Sun Microsystems, Inc. Systems and methods for performing quiescence in a storage virtualization environment
US7290168B1 (en) 2003-02-28 2007-10-30 Sun Microsystems, Inc. Systems and methods for providing a multi-path network switch system
US7383381B1 (en) 2003-02-28 2008-06-03 Sun Microsystems, Inc. Systems and methods for configuring a storage virtualization environment
US7107394B2 (en) * 2003-03-28 2006-09-12 Hewlett-Packard Development Company, L.P. Apparatus for capturing data on a debug bus
JP3811143B2 (ja) * 2003-07-09 2006-08-16 株式会社東芝 メモリ制御回路
JP5082727B2 (ja) * 2007-09-28 2012-11-28 ソニー株式会社 記憶制御装置、記憶制御方法およびコンピュータプログラム
US8495287B2 (en) 2010-06-24 2013-07-23 International Business Machines Corporation Clock-based debugging for embedded dynamic random access memory element in a processor core
WO2013076529A1 (en) * 2011-11-23 2013-05-30 Freescale Semiconductor, Inc. System-on-chip, method of manufacture thereof and method of controlling a system-on-chip
US11586383B2 (en) 2018-10-16 2023-02-21 Micron Technology, Inc. Command block management
US11543996B2 (en) 2020-05-20 2023-01-03 Western Digital Technologies, Inc. Systems and methods for power management in a data storage device
US11137823B1 (en) * 2020-05-20 2021-10-05 Western Digital Technologies, Inc. Systems and methods for power management in a data storage device
CN112328305B (zh) * 2020-10-30 2022-10-18 歌尔光学科技有限公司 一种眼图测试方法、装置、电子设备及可读存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469721A2 (en) * 1990-07-03 1992-02-05 Digital Equipment Corporation Mode switching for a memory system with diagnostic scan
WO1995018998A1 (en) * 1994-01-05 1995-07-13 Norand Corporation Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827476A (en) * 1987-04-16 1989-05-02 Tandem Computers Incorporated Scan test apparatus for digital systems having dynamic random access memory
JPH02255925A (ja) * 1988-11-30 1990-10-16 Hitachi Ltd メモリテスト方法および装置
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469721A2 (en) * 1990-07-03 1992-02-05 Digital Equipment Corporation Mode switching for a memory system with diagnostic scan
WO1995018998A1 (en) * 1994-01-05 1995-07-13 Norand Corporation Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PRINCE, Betty: High Performance Memories, Willey & Sons, S. 154-161, 1. Aufl., 1996, New York, ISBN 90 471 95646 5 *

Also Published As

Publication number Publication date
US5754557A (en) 1998-05-19
JPH10133960A (ja) 1998-05-22
DE19740223A1 (de) 1998-04-16
GB2320774A (en) 1998-07-01
GB2320774B (en) 2000-12-27
GB9721488D0 (en) 1997-12-10
JP4083847B2 (ja) 2008-04-30

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8304 Grant after examination procedure
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee