DE19724904A1 - Verfahren zum Herstellen eines Halbleiterbauelements - Google Patents

Verfahren zum Herstellen eines Halbleiterbauelements

Info

Publication number
DE19724904A1
DE19724904A1 DE19724904A DE19724904A DE19724904A1 DE 19724904 A1 DE19724904 A1 DE 19724904A1 DE 19724904 A DE19724904 A DE 19724904A DE 19724904 A DE19724904 A DE 19724904A DE 19724904 A1 DE19724904 A1 DE 19724904A1
Authority
DE
Germany
Prior art keywords
insulating layer
layer
semiconductor substrate
conductive layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19724904A
Other languages
German (de)
English (en)
Inventor
Yoshikazu Ohno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19724904A1 publication Critical patent/DE19724904A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
DE19724904A 1996-12-26 1997-06-12 Verfahren zum Herstellen eines Halbleiterbauelements Withdrawn DE19724904A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34750996A JP3592870B2 (ja) 1996-12-26 1996-12-26 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE19724904A1 true DE19724904A1 (de) 1998-07-02

Family

ID=18390712

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19724904A Withdrawn DE19724904A1 (de) 1996-12-26 1997-06-12 Verfahren zum Herstellen eines Halbleiterbauelements

Country Status (6)

Country Link
US (1) US6100134A (enExample)
JP (1) JP3592870B2 (enExample)
KR (1) KR100351929B1 (enExample)
CN (1) CN1155077C (enExample)
DE (1) DE19724904A1 (enExample)
TW (1) TW332928B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100668221B1 (ko) * 2004-12-31 2007-01-11 동부일렉트로닉스 주식회사 Ｍｉｍ 캐패시터 형성 방법
JP6123242B2 (ja) * 2012-11-09 2017-05-10 大日本印刷株式会社 パターン形成方法
CN104617035A (zh) * 2013-11-05 2015-05-13 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920004541B1 (ko) * 1989-05-30 1992-06-08 현대전자산업 주식회사 반도체 소자에서 식각베리어층을 사용한 콘택홀 형성방법
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
JPH07235594A (ja) * 1994-02-22 1995-09-05 Mitsubishi Electric Corp 半導体装置の製造方法
JP2765478B2 (ja) * 1994-03-30 1998-06-18 日本電気株式会社 半導体装置およびその製造方法
US5501998A (en) * 1994-04-26 1996-03-26 Industrial Technology Research Institution Method for fabricating dynamic random access memory cells having vertical sidewall stacked storage capacitors
JPH0846173A (ja) * 1994-07-26 1996-02-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US5489546A (en) * 1995-05-24 1996-02-06 Micron Technology, Inc. Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process
US5770498A (en) * 1996-01-31 1998-06-23 Micron Technology, Inc. Process for forming a diffusion barrier using an insulating spacer layer

Also Published As

Publication number Publication date
CN1155077C (zh) 2004-06-23
KR100351929B1 (ko) 2003-04-10
CN1186336A (zh) 1998-07-01
US6100134A (en) 2000-08-08
KR19980063335A (ko) 1998-10-07
JPH10189901A (ja) 1998-07-21
TW332928B (en) 1998-06-01
JP3592870B2 (ja) 2004-11-24

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8130 Withdrawal