DE19645033C2 - Verfahren zur Bildung eines Metalldrahtes - Google Patents

Verfahren zur Bildung eines Metalldrahtes

Info

Publication number
DE19645033C2
DE19645033C2 DE19645033A DE19645033A DE19645033C2 DE 19645033 C2 DE19645033 C2 DE 19645033C2 DE 19645033 A DE19645033 A DE 19645033A DE 19645033 A DE19645033 A DE 19645033A DE 19645033 C2 DE19645033 C2 DE 19645033C2
Authority
DE
Germany
Prior art keywords
layer
tin layer
tin
tetrakis
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19645033A
Other languages
German (de)
English (en)
Other versions
DE19645033A1 (de
Inventor
Jeong Tae Kim
Heung Lak Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of DE19645033A1 publication Critical patent/DE19645033A1/de
Application granted granted Critical
Publication of DE19645033C2 publication Critical patent/DE19645033C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19645033A 1995-11-01 1996-10-31 Verfahren zur Bildung eines Metalldrahtes Expired - Fee Related DE19645033C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039165A KR100218728B1 (ko) 1995-11-01 1995-11-01 반도체 소자의 금속 배선 제조방법

Publications (2)

Publication Number Publication Date
DE19645033A1 DE19645033A1 (de) 1997-05-07
DE19645033C2 true DE19645033C2 (de) 2002-09-12

Family

ID=19432609

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19645033A Expired - Fee Related DE19645033C2 (de) 1995-11-01 1996-10-31 Verfahren zur Bildung eines Metalldrahtes

Country Status (6)

Country Link
JP (1) JP2760490B2 (ja)
KR (1) KR100218728B1 (ja)
CN (1) CN1075244C (ja)
DE (1) DE19645033C2 (ja)
GB (1) GB2306777B (ja)
TW (1) TW382764B (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291343B1 (en) * 1994-11-14 2001-09-18 Applied Materials, Inc. Plasma annealing of substrates to improve adhesion
GB2322963B (en) * 1996-09-07 1999-02-24 United Microelectronics Corp Method of fabricating a conductive plug
KR100226742B1 (ko) * 1996-12-24 1999-10-15 구본준 반도체 소자의 금속배선 형성 방법
NL1005653C2 (nl) * 1997-03-26 1998-09-29 United Microelectronics Corp Werkwijze voor het fabriceren van een geleidende contactpen.
US5969425A (en) * 1997-09-05 1999-10-19 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
US6037252A (en) * 1997-11-05 2000-03-14 Tokyo Electron Limited Method of titanium nitride contact plug formation
US6432479B2 (en) 1997-12-02 2002-08-13 Applied Materials, Inc. Method for in-situ, post deposition surface passivation of a chemical vapor deposited film
KR100458295B1 (ko) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 반도체소자의콘택플러그형성방법
KR100558034B1 (ko) * 1999-06-30 2006-03-07 주식회사 하이닉스반도체 텅스텐 비트라인 형성시 플러그의 손상을 방지할 수 있는 반도체 소자 제조 방법
US6436819B1 (en) * 2000-02-01 2002-08-20 Applied Materials, Inc. Nitrogen treatment of a metal nitride/metal stack
DE10208714B4 (de) * 2002-02-28 2006-08-31 Infineon Technologies Ag Herstellungsverfahren für einen Kontakt für eine integrierte Schaltung
JP2006344684A (ja) 2005-06-07 2006-12-21 Fujitsu Ltd 半導体装置及びその製造方法
KR100885186B1 (ko) * 2007-05-03 2009-02-23 삼성전자주식회사 확산 베리어 필름을 포함하는 반도체 소자의 형성 방법
CN101459121B (zh) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 通孔及通孔形成方法
JP5872904B2 (ja) * 2012-01-05 2016-03-01 東京エレクトロン株式会社 ＴｉＮ膜の成膜方法および記憶媒体

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3711790C2 (ja) * 1986-05-13 1991-04-11 Mitsubishi Denki K.K., Tokio/Tokyo, Jp
US5089438A (en) * 1991-04-26 1992-02-18 At&T Bell Laboratories Method of making an article comprising a TiNx layer
JPH04216621A (ja) * 1990-12-18 1992-08-06 Seiko Instr Inc 薄膜の堆積方法
US5312774A (en) * 1991-12-05 1994-05-17 Sharp Kabushiki Kaisha Method for manufacturing a semiconductor device comprising titanium
US5416045A (en) * 1993-02-18 1995-05-16 Micron Technology, Inc. Method for chemical vapor depositing a titanium nitride layer on a semiconductor wafer and method of annealing tin films

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
US5175126A (en) * 1990-12-27 1992-12-29 Intel Corporation Process of making titanium nitride barrier layer
AU3726593A (en) * 1992-02-26 1993-09-13 Materials Research Corporation Ammonia plasma treatment of silicide contact surfaces in semiconductor devices
EP0571691B1 (en) * 1992-05-27 1996-09-18 STMicroelectronics S.r.l. Metallization over tungsten plugs
KR0144956B1 (ko) * 1994-06-10 1998-08-17 김광호 반도체 장치의 배선 구조 및 그 형성방법
JPH0926387A (ja) * 1995-07-11 1997-01-28 Tokyo Seimitsu Co Ltd 液体比重検出方法及び加工液比重検出装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3711790C2 (ja) * 1986-05-13 1991-04-11 Mitsubishi Denki K.K., Tokio/Tokyo, Jp
JPH04216621A (ja) * 1990-12-18 1992-08-06 Seiko Instr Inc 薄膜の堆積方法
US5089438A (en) * 1991-04-26 1992-02-18 At&T Bell Laboratories Method of making an article comprising a TiNx layer
US5312774A (en) * 1991-12-05 1994-05-17 Sharp Kabushiki Kaisha Method for manufacturing a semiconductor device comprising titanium
US5416045A (en) * 1993-02-18 1995-05-16 Micron Technology, Inc. Method for chemical vapor depositing a titanium nitride layer on a semiconductor wafer and method of annealing tin films

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KLAGES, C.-P.: Low Temperature Deposition of TiN Using Tetrakis(dime-thylamido)-Titanium in an Electron Cyclotron Resonance Plasma Process. In: J.Electrochem.Soc., 1994, Vol. 141, No. 3, S. 849-853 *
WEBER, A., NIKULSKI, R. *

Also Published As

Publication number Publication date
JPH09172083A (ja) 1997-06-30
GB9622538D0 (en) 1997-01-08
GB2306777B (en) 2000-03-08
JP2760490B2 (ja) 1998-05-28
CN1075244C (zh) 2001-11-21
KR100218728B1 (ko) 1999-09-01
DE19645033A1 (de) 1997-05-07
TW382764B (en) 2000-02-21
CN1151610A (zh) 1997-06-11
KR970030327A (ko) 1997-06-26
GB2306777A (en) 1997-05-07

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20110502