GB2306777A - Method for forming a metal wire - Google Patents

Method for forming a metal wire Download PDF

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Publication number
GB2306777A
GB2306777A GB9622538A GB9622538A GB2306777A GB 2306777 A GB2306777 A GB 2306777A GB 9622538 A GB9622538 A GB 9622538A GB 9622538 A GB9622538 A GB 9622538A GB 2306777 A GB2306777 A GB 2306777A
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United Kingdom
Prior art keywords
tin layer
layer
tin
depositing
contact hole
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Granted
Application number
GB9622538A
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GB9622538D0 (en
GB2306777B (en
Inventor
Jeong Tae Kim
Heung Lak Park
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of GB9622538D0 publication Critical patent/GB9622538D0/en
Publication of GB2306777A publication Critical patent/GB2306777A/en
Application granted granted Critical
Publication of GB2306777B publication Critical patent/GB2306777B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

2306777 METHOD FOR FORMING METAL WIRE
BACKGROUND OF THE INVENTION
Field of the Inventi
The present invention relates, in general, to a method for forming a metal wire in a semiconductor device and, more particularly, to a significant decrease in the contact resistance of the metal wire through chemical vapor deposition.
DescriRtion of the Prior Art
As semiconductor devices are highly integrated, many contact holes, which are typically formed by etching predetermined portions of interlayer insulating films, are necessary to interconnect lower conductive wires with upper ones. Also, the contact holes have a larger aspect ratio, the ratio of height to width, due to their own size and a reduction in the distance between themselves and neighboring wires.
In general, the metal wires of a semiconductor device are primarily made of aluminum-based metals by virtue of their simple deposition process and low resistance. However, when a contact to a semiconductor substrate or a conductive wire is accomplished by use of an aluminum-based metal layer, a phenomenon in which the atoms in the lower, layer diffuse into the metal layer or metal atoms penetrate into the substrate, occurs at the interface between the metal layer and the semiconductor substrate or conductive wire.
In order to prevent the spark phenomenon and minimize contact resistance, a barrier metal layer with a stack structure of Ti/TiN is thinly deposited on the lower surface of a contact hole, followed by the deposition of an aluminum-based metal layer thick enough to fill the contact hole. Then, a patterning process is carried out to form a metal wire in contact with the lower conductive layer or semiconductor substrate.
1 V.
A sputtering process, a physical vapor deposition process (hereinafter referred to as 11M11), is required for depositing such an aluminum-based metal layer. However, PVD has the significant disadvantage of causing poor step coverage which leads, in turn, to voids in the contact hole, resulting in deleteriously affecting the reliability of the semiconductor device.
In order better understand the background of the invention, a description will be given of a conventional method for forming a metal wire in a semiconductor device, with reference to the drawing accompanied.
Fig. 1 shows in schematic form a metal wire according to a conventional method.
is According to the conventional method, a contact hole is formed by depositing an interlayer insulating film 12 on a semiconductor substrate 11 and removing a predetermined portion of the interlayer insulating film 12.
Then, a stack structure consisting of a Ti layer 14A and a TiN layer 14B is formed using a sputtering process by which the two layers are, in sequence, deposited, the former being in contact with the semiconductor substrate 11 through the contact hole 13. The stack structure serves as a barrier metal layer 14. While the Ti layer 14A plays the role of reducing the contact resistance between the semiconductor substrate 11 and a conductive wire to be formed. The TiN layer 14B prevents the spark phenomenon of aluminum-based metal layer in the contact region of the conductive wire.
Thereafter, an aluminum-based metal layer 15 playing a principal role, for example, Al-Cu-Si alloy, is deposited over the barrier metal layer 14 by use of a PVD process, followed by the formation of a reflectionpreventing film 16 of TiN over the metal 2 layer 14.
When depositing the metal layer 15, poor step coverage is produced at the contact hole 13, generating a void 17 inside the contact hole 13. As a result, the reliability of the metal wire thus obtained is inferior.
is SUMMARY OF THE INVENTION
Therefore, it is an objective of the present invention to overcome the above problems encountered in prior arts and to provide a method for forming a metal wire in a semiconductor device by which any void in a contact hole is prevented and contact resistance is remarkably decreased.
In accordance with the present invention, the above objective could be accomplished by a provision of a method for forming a metal wire, comprising the steps of: forming an interlayer insulating film on a lower conductive layer; etching a predetermined portion of the interlayer insulating film to form a contact hole; depositing a Ti layer entirely over the resulting structure; depositing a thin TiN layer over the Ti layer in a chemical vapor deposition process; treating the TiN layer with a plasma, to give a low resistance to the TiN layer; repeating said steps of depositing a thin TiN layer and of treating the TiN layer enough to fill the contact hole; subjecting the TiN layer to etch to form a contact plug of TiN filling only the contact hole; and depositing a metal layer entirely over the resulting structure.
The repeated deposition and plasma treatment of the thin TiN layer on the contact hole, according to the present invention, has the effect of reducing the specific resistance of the TiN layer from 103-104 MDCM into 102 order pncm. In addition, the application of CVD for the repetitive deposition of the TiN layer allows the contact hole to be easily filled without any void, producing a 3 metal wire high in reliability.
BRIEF DESCRIPTION OF THE DRAWINGS is other objectives and aspects of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which:
Fig. 1 is a schematic cross sectional view showing a metal wire in contact with a semiconductor substrate, according to a prior art;
Figs. 2 through 7 are schematic cross sectional views showing a method for forming a metal wire in a semiconductor device, according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The application of the preferred embodiments of the present invention is best understood with reference to the accompanying drawings, wherein like reference numerals are used for like and corresponding parts, respectively.
Referring to Figs. 2 through 7, a method for forming a metal wire in a semiconductor device is illustrated.
First, as shown in Fig. 2, a interlayer insulating film is formed on a semiconductor substrate 1 or a conductive wire, followed by the formation of a contact hole 3 by selective etch of the interlayer insulating film 2. Then, a relatively thin Ti layer 4, for example, 50-300 A thick, is formed over the entire surface of the resulting structure by a PVD process, which will serve to lower the contact resistance.
Next, using a chemical deposition vapor (hereinafter referred to as 11CVD11) process, a first TiN layer 9A about 100-1,000 A thick is formed on the Ti layer 4, as shown in Fig. 3.
4 In more detail, the first TiN layer 9A is formed from tetrakis dimethyl amino titanium (Ti(N(CH3Y4; hereinafter referred to as IlTDMAT11) or tetrakis diethyl amino titanium (Ti(N(C2H,)2)4) alone or together with a mix gas of NH3/NF.. These sources are pyrolysed and then, carried by He or N2 gas. For deposition of the first TiN layer 9A, the pressure of the carrier gas containing TDMAT is maintained at 50 torr with a deposition temperature ranging from 300 to 6000C. The CVD process is carried out for 50 to 1,000 sec. Thereafter, the surface of the first TiN layer 9A is treated with a plasma of N2. H2 or the combination thereof. In the present invention, the TiN layer 9A is plasma treated to a depth of about 20 to 600 A, to be of low resistance. This plasma treatment is carried out under the condition that N. gas, H2 gas or the mix gas thereof flows at a rate of 50 to 700 sccm at a temperature of 50 to 6000 C under a pressure of 0.1 to 20 torr with an RF power of 50 to 1,000 W.
Fig. 4 is a cross section taken after a second TiN layer 9B is deposited and subjected to plasma treatment in the same manner with that for the first TiN layer 9A. Similarly, the second TiN layer 9B shows a low resistance.
Fig. 5 is a cross section taken after the same process as that of Fig. 4 is repeated, to form a third TiN layer 9C of low resistance on the second TiN layer 9B.
Subsequently, the three TiN layers 9C, 9B and 9A are, in sequence, subjected to anisotropic etching until the upper surface of the Ti layer 4 is exposed, so as to form a contact plug 10 consisting of parts of the three TiN layers, filling the contact hole 3, as shown in Fig.6.
Finally, after being formed over the resulting structure by a PVD process, an aluminum-based metal layer 5 is patterned along with the Ti layer 4, to provide a conductive wire consisting of Ti layer 4 and the Al-based metal layer 5, both being in contact with the contact plug 10, as shown in Fig. 7.
In the above embodiment, the TiN layer deposition and plasma treatment is repeated three times but may be repeated more times if thinner TiN layers are deposited. Higher content of the low resistance TiN layer in the contact plug 10 results in lower resistance of the metal wire.
is In accordance with another embodiment of the present invention, the first TiN layer 9A is deposited without depositing the Ti layer 4 shown in Fig. 2 and then, the subsequent processes are carried out.
The repeated deposition and plasma treatment of the TiN layer on the contact hole has the effect of reducing the specific resistance of the TiN layer from 103_104 ACM into 102 M0cm. When the TiN layer source is deposited through thermal decomposition, it is not completely decomposed, which generates a plenty of carbon and oxygen in the TiN thin film, giving rise to an increase of the specific resistance. The plasma treatment allows the carbon and oxygen atoms incompletely bonded in the TiN thin film to bind to hydrogen ions. Thus, the carbon and oxygen atoms are emitted in forms of CH3. CH4 and HP and their vacant spaces are filled by nitrogen ions, so that more TiN bonds are produced, lowering the specific resistance.
As described hereinbefore. the present invention is to prevent void in a contact hole as well as to minimize contact resistance, with the aim of improving the yield of the metal wire process and the reliability of the semiconductor device through a repetitive process of depositing a thin TiN layer in contact with a lower conductive layer via the contact hole in a CVD process and plasma treating the surface of the TiN layer with N2. H2 or the mix gas thereof.
6 The present invention has been described in an illustrative manner, and it is to be understood that the terminology used is intended to be in the nature of description rather than limitation.
Many modifications and variations of the present invention are possible in light of the above teachings. For example, although the above embodiments are illustrated with the example of a metal contact or a metal wire contact, it is obvious that the method according to the spirit of the present invention can be applied for a contact between metal wires. Therefore, it is to be understood that within the scope of the appended claims, the invention may be practiced in ways other than those specifically described.
7

Claims (21)

CLAIM:
1. A method for forming a metal wire in a semiconductor device, comprising the steps of: forming an interlayer insulating film on a lower conductive layer; etching a predetermined portion of the interlayer insulating film to form a contact hole; depositing a Ti layer entirely over the resulting structure; depositing a thin TiN layer over the Ti layer in a chemical vapor deposition process; treating the TiN layer with a plasma, to give a low resistance to the TiN layer; repeating said steps of depositing a thin TiN layer and of treating the TiN layer enough to fill the contact hole; subjecting the TiN layer to etch to form a contact plug of TiN filling only the contact hole; and depositing a metal layer. entirely over the resulting structure.
2. A methoe, in accor with claim 1 a thickness of about 50 to 300 A.
3. A method according to claims 1 or 2, has a thickness of 100 to 1,000 A.
9 wherein said Ti layer has wherein said TiN layer
4. A method according to any am of claims 1 to 3, wherein said TiN layer is deposited using a tetrakis dimethyl amino titanium or tetrakis diethyl amino titanium liquid source.
5. A method according to any one of claims 1 to 3. wherein.said TiN layer isdeposited usinga mixture of a tetrakis dimethyl amino titanium or tetrakis diethyl amino titanium liquid source and a NH3/NF3 mix gas.
6. A method in accordance with claim 4, wherein said TiN layer is 8 deposited by pyrolysing said source and using He or N. as a carrier gas at a pressure of 0.1 to 50 torr and at a temperature of 300 to 6000C for 50 to 1,000 sec.
7. A method according to any cne of claim 1 to 6, whierein TiN layer is surface treated with a plasm of N., H. or the mixture thereof.
8. A method 6coording to any cne of claims.1 to 7. wherein sald TiN layer ia part or all is lowered in resistance by the plasma treatment.
9. A method according to cl 7 or 8, wherein the plasma treatment is carried out using N2, H. or the mixture thereof
10. A method in accordance with claim 9, wherein said plasma is treatment is carried out at a flow rate of 50 to 700 sccm and at a temperature of 50 to 6000C under a pressure of 0.1 to 20 torr with an RF power ranging from 50 to 1,000 W.
11. A method for forming a metal wire in a semiconductor device, comprising the steps of: forming an interlayer insulating film on a lower conductive layer; etching a predetermined portion of the interlayer insulating film to form a contact hole; depositing a thin TiN layer entirely over the resulting structure in a chemical vapor deposition process; treating the TiN layer with a plasma, to give a low resistance to the TiN layer; repeating said steps of depositing a thin TiN layer and of treating the TiN layer enough to fill the contact hole; subjecting the TiN layer to etch to form a contact plug of TiN filling only the contact hole; and depositing a metal layer entirely over the resulting structure.
9
12. A method in accordance with claim 11, wherein said TiN layer has a thickness of 100 to 1,000 A.
13. A method according to cl 11 or 12, wherein said TiN layer is deposited using a tetrakis dimethyl amino titanium or tetrakis diethyl amino titanium liquid source.
14. A method according to cl 11 or 12, wherein said TiN layer is deposited using a mixture of a tetrakis dimethyl amino titanium or tetrakis diethyl amino titanium liquid source and a NH 3/NF3 Mix gas.
is
15. A method in accordance with claim 13, wherein said TiN layer is deposited by pyrolysing said source and using He or N2 as a carrier gas at a pressure of 0.1 to 50 torr and at a temperature of 300 to 6000C for 50 to 1,000 sec.
16. A method according to any one of cl 11 to 15, wherein said TiN layer is surface.. treated with a plasm of N2, H2 or the mixture thereof
17. A method according to any an6 of cl 11 to 16, wherein sald TiN layer in part or all is lowered in resistance by the plasma treatment.
18. A method accog to cl 16 or 17, wherein the plasma treatment is carried out using N2. H2 or the mixture thereof.
19. A method in accOrdance with claim 18, wherein said plasma treatment is carried out at a flow rate of 50 to 700 sccm and at a temperature of 50 to 6000 C under a pressure of 0.1 to 20 torr with an RF power ranging from 50 to 1,000 W.
20. A method in accordance with any cue of claims 11 to 19, wherein said metal layer is an aluminum based metal layer.
21. A method for forming a metal in a semicanductor device substantially as hereud)efore described with reference to any cne of Figures 2 to 7 of the acoaqpmying drawings.
GB9622538A 1995-11-01 1996-10-30 Method for forming metal wire Expired - Fee Related GB2306777B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950039165A KR100218728B1 (en) 1995-11-01 1995-11-01 Manufacturing method of metal interconnection of semiconductor device

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GB9622538D0 GB9622538D0 (en) 1997-01-08
GB2306777A true GB2306777A (en) 1997-05-07
GB2306777B GB2306777B (en) 2000-03-08

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JP (1) JP2760490B2 (en)
KR (1) KR100218728B1 (en)
CN (1) CN1075244C (en)
DE (1) DE19645033C2 (en)
GB (1) GB2306777B (en)
TW (1) TW382764B (en)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
FR2753304A1 (en) * 1996-09-07 1998-03-13 United Microelectronics Corp METHOD FOR MANUFACTURING A CONDUCTIVE PLUG
NL1005653C2 (en) * 1997-03-26 1998-09-29 United Microelectronics Corp Conductive plug manufacture
WO1999013501A1 (en) * 1997-09-05 1999-03-18 Advanced Micro Devices, Inc. Borderless vias with cvd barrier layer
WO1999023698A1 (en) * 1997-11-05 1999-05-14 Tokyo Electron Limited Titanium nitride contact plug formation
US6436819B1 (en) 2000-02-01 2002-08-20 Applied Materials, Inc. Nitrogen treatment of a metal nitride/metal stack
US9257278B2 (en) 2012-01-05 2016-02-09 Tokyo Electron Limited Method for forming TiN and storage medium

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US6291343B1 (en) * 1994-11-14 2001-09-18 Applied Materials, Inc. Plasma annealing of substrates to improve adhesion
KR100226742B1 (en) * 1996-12-24 1999-10-15 구본준 Method for forming metal interconnection layer of semiconductor device
US6432479B2 (en) 1997-12-02 2002-08-13 Applied Materials, Inc. Method for in-situ, post deposition surface passivation of a chemical vapor deposited film
KR100458295B1 (en) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 Contact plug formation method of semiconductor device
KR100558034B1 (en) * 1999-06-30 2006-03-07 주식회사 하이닉스반도체 Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process
DE10208714B4 (en) 2002-02-28 2006-08-31 Infineon Technologies Ag Manufacturing method for a contact for an integrated circuit
JP2006344684A (en) 2005-06-07 2006-12-21 Fujitsu Ltd Semiconductor device and its manufacturing method
KR100885186B1 (en) * 2007-05-03 2009-02-23 삼성전자주식회사 Methods of forming a semiconductor device including a dffiusion barrier film
CN101459121B (en) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 Through hole and through hole forming method

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GB2290166A (en) * 1994-06-10 1995-12-13 Samsung Electronics Co Ltd Wiring structure and method of manufacture

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2753304A1 (en) * 1996-09-07 1998-03-13 United Microelectronics Corp METHOD FOR MANUFACTURING A CONDUCTIVE PLUG
GB2322963A (en) * 1996-09-07 1998-09-09 United Microelectronics Corp Method of forming a conductive plug
GB2322963B (en) * 1996-09-07 1999-02-24 United Microelectronics Corp Method of fabricating a conductive plug
NL1005653C2 (en) * 1997-03-26 1998-09-29 United Microelectronics Corp Conductive plug manufacture
WO1999013501A1 (en) * 1997-09-05 1999-03-18 Advanced Micro Devices, Inc. Borderless vias with cvd barrier layer
US5969425A (en) * 1997-09-05 1999-10-19 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
US6159851A (en) * 1997-09-05 2000-12-12 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
WO1999023698A1 (en) * 1997-11-05 1999-05-14 Tokyo Electron Limited Titanium nitride contact plug formation
US6037252A (en) * 1997-11-05 2000-03-14 Tokyo Electron Limited Method of titanium nitride contact plug formation
US6436819B1 (en) 2000-02-01 2002-08-20 Applied Materials, Inc. Nitrogen treatment of a metal nitride/metal stack
US9257278B2 (en) 2012-01-05 2016-02-09 Tokyo Electron Limited Method for forming TiN and storage medium

Also Published As

Publication number Publication date
GB9622538D0 (en) 1997-01-08
KR100218728B1 (en) 1999-09-01
JPH09172083A (en) 1997-06-30
CN1075244C (en) 2001-11-21
JP2760490B2 (en) 1998-05-28
GB2306777B (en) 2000-03-08
DE19645033C2 (en) 2002-09-12
TW382764B (en) 2000-02-21
CN1151610A (en) 1997-06-11
KR970030327A (en) 1997-06-26
DE19645033A1 (en) 1997-05-07

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Effective date: 20101030