GB2322963A - Method of forming a conductive plug - Google Patents

Method of forming a conductive plug Download PDF

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Publication number
GB2322963A
GB2322963A GB9704377A GB9704377A GB2322963A GB 2322963 A GB2322963 A GB 2322963A GB 9704377 A GB9704377 A GB 9704377A GB 9704377 A GB9704377 A GB 9704377A GB 2322963 A GB2322963 A GB 2322963A
Authority
GB
United Kingdom
Prior art keywords
conductive
barrier layer
conductive material
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9704377A
Other versions
GB2322963B (en
GB9704377D0 (en
Inventor
Client Wu
Horng-Bor Bu
Jenn-Tarng Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW085110947A external-priority patent/TW314654B/en
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to GB9704377A priority Critical patent/GB2322963B/en
Priority to DE19710688A priority patent/DE19710688A1/en
Priority to JP9060377A priority patent/JPH1098013A/en
Priority to FR9703262A priority patent/FR2753304B1/en
Publication of GB9704377D0 publication Critical patent/GB9704377D0/en
Publication of GB2322963A publication Critical patent/GB2322963A/en
Application granted granted Critical
Publication of GB2322963B publication Critical patent/GB2322963B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A diffusion barrier layer (eg titanium nitride) 24 is formed between a conductive layer 26 and an underlying semiconductor region 20A. The barrier layer is treated with a hydrogen plasma which roughens the surface of the barrier layer. The roughened surface increases the number of adhesion sites for deposited layer 26 and thereby reduces void formation in layer 26.

Description

METHOD OF FABRICATING A CONDUCTIVE PLUG BACKGROUND OF THE INVENTION Field of the Invention This invention relates in general to a semiconductor manufacturing process, and more particularly to a method of forming a conductive plug to avoid voids.
Description of Related Art When the density of the integrated circuits increases, the surface of a chip might not provide enough area for interconnects to lay thereon. For the need of interconnects with reduced size of metal-oxide-semiconductor transistors, more than two metal layers become the necessary way for many integrated circuits. For some complicated products, such as microprocessors, even more metal layers are needed to complete the interconnection between individual devices within the microprocessor. Different metal layers are connected by conductive plugs.
Usually, a conductive plug is. formed by. etching an.insulating layer to form a contact hole, then filling a conductive material such as tungsten into the contact hole.
Because the adhension between the conductive material and the insulating layer is defficient, a glueroarrier material must be formed between the conductive material and the insulating layer. Commonly used glue/barrier materials include Ti, TiN, or TiW formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
However, the conductive plug of an integrated circuit formed by a conventional process is apt to generate voids. For more clearly understanding the reason, an example is used to explain the conventional process offabricating the conductive plug ofan integrated circuit.
Figure 1 shows a cross-sectional diagram of a conductive plug of an integrated circuit formed by a conventional manufacturing method. An insulating layer !2, JüCil as borophosphosiiicate glass (BPSG) or oxide, is formed on the silicon substrate l0 or on a metal line After, a portion of the insulating layer 12 is removed by etching to form a contact window 13 which exposes a region I Oa of the conductive material by, for example, an anisotropic etching A diffusion barrier layer 14 is formed on the region Ca of the conductive material and the periphery ofthe contact window 13, and extended to the upper surface of the insulating layer 12 The diffusion barrier layer 14 can be, for example, a TiNx layer which prevents diffusion and improves adhension. Then, a conductive material 16, for example, a tungsten, copper or aluminum, is filled into the contact window 13, by PVD or CVD. Since the step coverage is bad, a void 18 is formed therein.
In the above mentioned manufacturing method of the conductive plug of the integrated circuit, a diffusion barrier layer is deposited before the conductive material is filled into the contact window of the insulating layer as a glue/barrier layer. Therefore, the contact window becomes narrower, and deposition sites on the diffusion barrier layer become recessed, which results in voids generating when the conductive material is deposited. As a result, the large voids seriously affect the characteristics of the device such as resistance raising and short circuit.
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method to form a conductive plug of an integrated circuit by plasma treatment on diffusion barrier layer before the conductive layer is deposited. Therefore, the problem of void can be avoided as the conductive material is later filled According to a preferred embodiment of the invention, an insulating layer is formed on the semiconductor substrate or on a metal line. The insulating layer is etched to form a contact window which exposes the conductive region of the device. A diffusion barrier layer 5 formed on the exposed conductive region and the periphery of the contact window.
A hydrogen plasma treatment is performed in a reaction chamber; and a conductive material is filled in the contact window, to form the conductive plug.
BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features, and advantages of the present invention will become apparent by way of the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which: Figure 1 shows the cross-sectional structure ofthe conductive plug ofan integrated circuit fabricated by a conventional manufacturing method; and Figure 2 shows the cross-sectional structure of the conductive plug of an integrated circuit in accordance with a preferred embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 2, an insulating layer 22, for example, a borophosphosilicate glass or oxide, is formed on a silicon substrate or on a metal line semiconductor 20 Then, a contact window 23 is formed by etching the insulating layer 22 to expose a region 20a of a conductive material, which can be, for example, a source/drain region, a gate or a metal line. A portion of the insulating layer 22 is removed using, for exarnple, a photolithograpy and anisotropic etching. A diffusion barrier layer 24 is formed on the region 20a of a conductive material, the periphery of the contact window 23 and further onto the upper surface of the insulating layer 22. The diffusion barrier layer 24 can be a composed layer which is formed by physical vapor depositing or chemical vapor depositing a Ti layer and then a TiN, layer. Alternatively, the diffusion barrier layer 24 can be a tungsten nitride layer or a titanium-tungsten layer. After that, a hydrogen plasma treatment is carried out on to the diffusion barrier layer 24. The hydrogen plasma treatment is performed under the following conditions: a power of less than 3000watt a hydrogen input flow rate of less than 3000sccm, a reaction temperature of less than 1000 C, and a reaction interval of between 10sex and loin. Then, a conductive material 26 such as tungsten, copper, or aluminum is filled into the contact window 23 by, for example, PVD or CVD to form a conductive plug with a tiny void 28.
In the above mentioned embodiment during a hydrogen plasma treatment, the high energy particles increase the density of the diffusion barrier layer, enlarge the contact window and form a number of small caves on the surface of the diffusion barrier layer, which therefore becomes rough. Consequently, the number of the deposition sites increase and a smoother conductive layer can be obtained. Therefore, improving the problem of voids tremendously. Additionally, another merit is that the value of x of TiNx of the diffusion barrier layer (Ti/TiNx) will be reduced so that the contact resistance lowers.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention need not be iimited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and- scope of the appended- claims; the scope-of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (13)

  1. i . A method of forming a conductive plug, comprising the steps of: providing a semiconductor substrate; forming a device having a conductive. region on the semiconductor substrate; forming an insulating layer over the semiconductor substrate; etching the insulating layer to form a contact window which exposes the conductive region of the device; forming a diffusion barrier layer on the exposed conductive region and the periphery of the contact window; performing a hydrogen plasma treatment on the diffUsion barrier layer, and filling - a conductive material it the contact window to form the conductive plug.
  2. 2. A method according to claim I, wherein the conductive region is a source/drain region; and the contact window is formed to expose a portion of the source/drain region.
  3. 3. A method according to claim I, wherein the conductive region is a metal line; and the contact windows a via which exposes a portion of the metal line.
  4. 4. A method according to claim 1, wherein the difflision barrier layer includes a titanium layer and a titanium nitride layer.
  5. 5. A method according to claim 1 wherein the diffUsion barrier layer includes a tungsten nitride layer.
  6. 6. A method according to claim l, wherein the diffusion barrier layer includes a titanium-tungsten layer.
  7. 7. A method according to claim 1, wherein the hydrogen plasma treatment is performed in a reaction chamber and the operation condition includes: a power of less than 3000 watt; a hydrogen input flow rate of less than 3000 scrm; a reaction temperature of less than 1 000 C; and a reaction interval of between 10 sec and 10 min.
  8. 8. A method according to claim 1, wherein the conductive material includes tungsten.
  9. 9. A method according to claim 1, wherein the conductive material includes gold.
  10. 10. A method according to claim 1 wherein the conductive material includes aluminum.
  11. 11. A method according to claim I, wherein the conductive material is formed by chemical vapor deposition.
  12. 12. A method according to claim 1, wherein the conductive material is formed by physical vapor deposition.
  13. 13. A method of forming a conductive plug substantially as hereinbefore described with reference to and/or as illustrated in Fig. 2 of the accompanying drawings.
GB9704377A 1996-09-07 1997-03-03 Method of fabricating a conductive plug Expired - Fee Related GB2322963B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB9704377A GB2322963B (en) 1996-09-07 1997-03-03 Method of fabricating a conductive plug
DE19710688A DE19710688A1 (en) 1996-09-07 1997-03-14 Conductive plug manufacture
JP9060377A JPH1098013A (en) 1996-09-07 1997-03-14 Manufacture of conductive plug
FR9703262A FR2753304B1 (en) 1996-09-07 1997-03-18 METHOD FOR MANUFACTURING A CONDUCTIVE PLUG

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW085110947A TW314654B (en) 1996-09-07 1996-09-07 Manufacturing method of conductive plug
GB9704377A GB2322963B (en) 1996-09-07 1997-03-03 Method of fabricating a conductive plug

Publications (3)

Publication Number Publication Date
GB9704377D0 GB9704377D0 (en) 1997-04-23
GB2322963A true GB2322963A (en) 1998-09-09
GB2322963B GB2322963B (en) 1999-02-24

Family

ID=26311106

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9704377A Expired - Fee Related GB2322963B (en) 1996-09-07 1997-03-03 Method of fabricating a conductive plug

Country Status (4)

Country Link
JP (1) JPH1098013A (en)
DE (1) DE19710688A1 (en)
FR (1) FR2753304B1 (en)
GB (1) GB2322963B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990026626A (en) * 1997-09-25 1999-04-15 윤종용 Method of forming metal wiring in semiconductor process
KR20040019170A (en) * 2002-08-26 2004-03-05 삼성전자주식회사 Method of forming Al contact
DE102004026005B4 (en) 2004-05-27 2006-06-14 Stm Medizintechnik Starnberg Gmbh ZOOMOBJEKTIV for endoscopy equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2290166A (en) * 1994-06-10 1995-12-13 Samsung Electronics Co Ltd Wiring structure and method of manufacture
US5552341A (en) * 1992-12-10 1996-09-03 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
GB2306777A (en) * 1995-11-01 1997-05-07 Hyundai Electronics Ind Method for forming a metal wire

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970001883B1 (en) * 1992-12-30 1997-02-18 삼성전자 주식회사 Semiconductor device and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552341A (en) * 1992-12-10 1996-09-03 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
GB2290166A (en) * 1994-06-10 1995-12-13 Samsung Electronics Co Ltd Wiring structure and method of manufacture
GB2306777A (en) * 1995-11-01 1997-05-07 Hyundai Electronics Ind Method for forming a metal wire

Also Published As

Publication number Publication date
DE19710688A1 (en) 1998-03-12
JPH1098013A (en) 1998-04-14
FR2753304A1 (en) 1998-03-13
FR2753304B1 (en) 1998-12-24
GB2322963B (en) 1999-02-24
GB9704377D0 (en) 1997-04-23

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080303