WO1993017453A2 - Ammonia plasma treatment of silicide contact surfaces in semiconductor devices - Google Patents

Ammonia plasma treatment of silicide contact surfaces in semiconductor devices Download PDF

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Publication number
WO1993017453A2
WO1993017453A2 PCT/US1993/001507 US9301507W WO9317453A2 WO 1993017453 A2 WO1993017453 A2 WO 1993017453A2 US 9301507 W US9301507 W US 9301507W WO 9317453 A2 WO9317453 A2 WO 9317453A2
Authority
WO
Grant status
Application
Patent type
Prior art keywords
ammonia plasma
ammonia
freon
semiconductor devices
plasma treatment
Prior art date
Application number
PCT/US1993/001507
Other languages
French (fr)
Other versions
WO1993017453A3 (en )
Inventor
Bruce A. Sommer
Eric C. Eichman
Michael J. Churley
Original Assignee
Materials Research Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching

Abstract

Methods are disclosed for treating semiconductor devices with an ammonia (NH3) plasma subsequent to freon/O2 etching to remove native oxide layers. Freon/O2 etching leaves a fluoridated polymer residue which is removed by the ammonia plasma, thereby resulting in improved contact resistanc of the final semiconductor device product.

Description

AM ONIA PLASMA TREATMENT OF SILICIDE CONTACT SURFACES IN SEMICONDUCTOR DEVICES

Field of the Invention

The present invention relates to a process for treating semiconductor devices which results in improved contact resistance. Background of the Invention

Semiconductor devices are typically fab¬ ricated starting with a substrate, e.g. , a silicon wafer, having an insulating dielectric layer such as silicon dioxide on the surface thereof. In many applications, the silicon substrate has contact or junction regions in which the silicon is doped with boron, phosphorous, arsenic, or any other suitable doping compound. The doped contact regions in the substrate are exposed by etching a desired pattern in the oxide layer to form contact or via holes therein. Such etching is performed using etching techniques well known in the art. The contact holes are then filled with a conductor, such as aluminum, to provide electrical contact between the doped regions of the substrate and a conductive film which may be deposite over the dielectric insulating layer to serve as a low resistance interconnection within the semiconductor device. Such films may be aluminum, doped poly- crystalline silicon, tungsten, or another refractory metal.

The deposition of aluminum as the intercon¬ nect layer over an oxide insulating layer having contact holes therein has several drawbacks. One of these which is of particular concern is that aluminum diffuses rapidly or "spikes" into the silicon contact or junction regions exposed in the contact holes. As a means for inhibiting aluminum spiking in doped silicon contacts, it is known to deposit a barrier layer in the contact holes over the silicon contacts. One suitable barrier material is titanium nitride (TiN) and it may be deposited by known chemical vapor deposition or sputtering techniques.

The fabrication of semiconductor devices including, among other things, a barrier layer and an interconnect layer, as described above, typically includes as a first step etching the insulating layer to form contact holes therein. Subsequently, the barrier layer is deposited in the contact holes, and thereafter the desired interconnect layer may be deposited. In such fabrication processes, it is imperative that the surfaces upon which the various layers are deposited be free from impurities such as oxide films which form upon exposure to oxygen, i.e., native oxide films. The failure to provide clean contact between the layers of conductive material results in undesirably high contact resistance of the semiconductor device at the location of the contact regions. This high contact resistance greatly limits overall device speed and limits the development of higher density semiconductor devices.

Various techniques are known for removing native oxide films prior to deposition of subsequent layers such as titanium nitride, tungsten or aluminum over silicon contact regions. One known method uses freon/oxygen plasma etch chemistry to remove the native oxide from the exposed contact surfaces. This method has the drawback that a fluoridated carbon polymer residue is formed on the wafer contact sur¬ face. The polymer residue inhibits the growth of vapor deposited titanium nitride, thus adversely affecting the contact resistance of the final product Summary of the Invention

The present invention is directed to a process for pre-treating semiconductor devices with a ammonia plasma which results in improved contact resistance and which overcomes the drawbacks associ¬ ated with prior art techniques, as discussed above. In one aspect of the invention, ammonia plasma is utilized to remove deposition-inhibiting polymer residues from semiconductor contact surfaces which residues result from known freon/oxygen plasma etching used to remove native oxides. The use of ammonia plasma treatment subsequent to freon/oxygen plasma etching, but prior to low pressure chemical vapor deposition (LPCVD) of titanium nitride, or deposition of other materials including tungsten and aluminum, enables the CVD reaction to grow a desired titanium nitride film without the polymer residue contamination and without native oxide, both of which deleteriously affect the contact resistance of the final semiconductor device product.

In a preferred embodiment, a method of the present invention comprises treating a silicon wafer substrate with an ammonia plasma in a CVD reaction chamber prior to LPCVD of titanium nitride (or other material) to thereby remove any undesirable fluori¬ dated polymer residue from an earlier freon/oxygen plasma etch. Alternatively, the ammonia plasma pre-treatment may be performed in a pre-treatment chamber and then the device is transferred to a CVD reaction chamber for subsequent processing.

These and other features and advantages of the present invention will become apparent to persons skilled in the art upon reading the following detailed description. Detailed Description of the Invention

In the fabrication of typical semiconductor devices, a substrate (usually silicon) is provided with a plurality of doped contact or junction regions, which are formed by techniques well known in the art and which do not form a part of the present invention. Typically, a semiconductor device initially has a continuous dielectric insulating layer formed on the substrate. The dielectric insulating layer may be a doped or undoped, deposited or grown silicon dioxide insulating layer. Thereafter, the insulating layer is selectively etched by known techniques to form contact or via holes in which the doped regions are exposed. Exposure of the device to oxygen oxidizes the silicon substrate and a thin layer of native oxide is formed on the exposed surface of the doped regions. This native oxide layer must be removed since it increases the contact resistance of the semiconductor device.

In accordance with one aspect of the present invention, a semiconductor device which has a native oxide layer on the exposed contact surfaces is treated with an ammonia (NH_) plasma subsequent to a known freon/oxygen etch. The freon/oxygen etching is a well known technique for removing the native oxide layer from semiconductor devices. The use of freon/02 etching leaves a fluoridated carbon polymer residue on the exposed substrate surfaces. The ammonia plasma treatment of the present invention removes the polymer residue, thus resulting in an overall improvement in the contact resistance of the device.

By way of example but not intended to be limiting in any way, the freon/0_ etching of a semi¬ conductor device may be accomplished as follows. The semiconductor device is placed in a pre-treatment chamber and exposed to a flow of CF./O- on the order of about 30 seem. The gas composition is preferably about 92% 0 and about 8% CF . The reactor pressure is about 1.5 torr and is powered at about 150 watts RF. For titanium silicide contacts, the etch treat¬ ment is preferably about 35 seconds. It will be appreciated by persons skilled in the art that various other freon/0 etching protocols may be used, and such procedures are known in the art.

Once the semiconductor wafer is treated with the freon/oxygen etching, it is then subjected to an ammonia plasma treatment,- which is the focus of the present invention. The ammonia plasma treatment may be carried out in a pretreat ent chamber or in a CVD chamber. The following examples are illustrative of the ammonia plasma treatment of the present invention. EXAMPLE 1 A semiconductor device, which was previously treated with a freon/O- etch, is subjected to ammonia plasma treatment in a pretreat chamber. The ammonia gas flows at a rate of about 30 seem and the treatment chamber is maintained at a pressure of about 500 mtorr. The wafer temperature is about 80βC and the reactor is powered with about 225 watts RF power. About 60 seconds of ammonia plasma treatment effec¬ tively removes the fluoridated polymer residue resulting from the freon/0_ etch.

EXAMPLE 2

A semiconductor device, which was previousl treated with a freon/O etch, is subjected to ammonia plasma treatment in a CVD reaction chamber. The ammonia gas flows at a rate of about 100 seem, the treatment chamber is maintained at a pressure of abou 150 mtorr, and at a temperature in the range of about 650°-680*C. The reactor is powered with about 200 watts RF power and the plasma treatment is accom¬ plished in about 10 seconds.

Utilizing the ammonia plasma treatment of the present invention, the resulting semiconductor devices are suitable for subsequent deposition of blanket or selective tungsten, titanium nitride, aluminum (or alloys thereof) , or virtually any con¬ ductive material. The resulting devices have good ohmic contact, on the order of about 10—8 ohm cm2

(specific contact resistance) . The ammonia plasma treatment of the present invention may be accomplished in a pretreatment chamber utilizing an ammonia flow rate of at least about 20 seem, at pressures in the range of about 0.1-10 torr, and for treatment times of at least about 30 seconds. When the process is performed in a CVD reaction chamber, the ammonia gas flow rate is at least about 100 seem, the pressure is in the range of about 0.1-10 torr and treatment times of at least about 10 seconds are utilized. When the procedure is performed in a pretreatment chamber, the gas temperature is preferably in the range of about

25-400*C. When a CVD reaction chamber is used, the gas temperature is preferably in the range of about

450'-750βC.

It will be appreciated by persons skilled in the art that various modifications can be made to the method of the present invention without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A method of treating a semiconductor device subsequent to a freon/02 plasma etch, said method comprising: treating said semiconductor device with an ammonia plasma subsequent to a freon/0_ plasma etch, wherein said ammonia plasma treatment results in improved contact resistance in said semiconductor device.
2. A method of claim 1 wherein said ammonia plasma treating is carried out in a pretreatment chamber at a pressure in the range of about 0.1-10 torr and at a gas temperature in the range of about 25'C-400βC.
3. A method of claim 2 wherein said ammonia plasma treating is carried out for at least about 30 seconds at a gas flow rate of at least about 20 seem.
4. A method of claim 1 wherein said ammonia plasma treating is carried out in a CVD reaction chamber at a pressure in the range of about 0.1-10 torr and at a gas temperature in the range of about 450-750°C.
5. A method of claim 4 wherein said ammonia plasma treating is carried out for at least about 10 seconds at a gas flow rate of at least about 100 seem.
PCT/US1993/001507 1992-02-26 1993-02-22 Ammonia plasma treatment of silicide contact surfaces in semiconductor devices WO1993017453A3 (en)

Priority Applications (2)

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US84208892 true 1992-02-26 1992-02-26
US07/842,088 1992-02-26

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WO1993017453A2 true true WO1993017453A2 (en) 1993-09-02
WO1993017453A3 true WO1993017453A3 (en) 1993-10-28

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2306777A (en) * 1995-11-01 1997-05-07 Hyundai Electronics Ind Method for forming a metal wire
EP0851474A2 (en) * 1996-12-12 1998-07-01 Texas Instruments Inc. Improvements in or relating to integrated circuits
US5852915A (en) * 1996-09-26 1998-12-29 R. R. Donnelley & Sons Company Method of making compact disc product
WO2000029642A1 (en) * 1998-11-17 2000-05-25 Applied Materials, Inc. Removing oxides or other reducible contaminants from a substrate by plasma treatment
EP1081754A2 (en) * 1999-09-03 2001-03-07 Applied Materials, Inc. Cleaning contact area with successive fluoride and hydrogen plasmas
US6355571B1 (en) 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US6492266B1 (en) * 1998-07-09 2002-12-10 Advanced Micro Devices, Inc. Method of forming reliable capped copper interconnects
US6592770B1 (en) 1999-02-26 2003-07-15 Trikon Holdings Limited Method of treating an isulating layer
US6613681B1 (en) * 1998-08-28 2003-09-02 Micron Technology, Inc. Method of removing etch residues
US8492287B2 (en) 2006-08-15 2013-07-23 Tokyo Electron Limited Substrate processing method
US9614045B2 (en) 2014-09-17 2017-04-04 Infineon Technologies Ag Method of processing a semiconductor device and chip package

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
US4731156A (en) * 1987-02-25 1988-03-15 Itt Avionics, A Division Of Itt Corporation Plasma processes for surface modification of fluoropolymers using ammonia
EP0376252A2 (en) * 1988-12-27 1990-07-04 Kabushiki Kaisha Toshiba Method of removing an oxide film on a substrate
EP0485802A1 (en) * 1990-10-30 1992-05-20 Nec Corporation Method of preventing corrosion of aluminium alloys
US5174856A (en) * 1991-08-26 1992-12-29 Applied Materials, Inc. Method for removal of photoresist over metal which also removes or inactivates corrosion-forming materials remaining from previous metal etch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357203A (en) * 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
US4731156A (en) * 1987-02-25 1988-03-15 Itt Avionics, A Division Of Itt Corporation Plasma processes for surface modification of fluoropolymers using ammonia
EP0376252A2 (en) * 1988-12-27 1990-07-04 Kabushiki Kaisha Toshiba Method of removing an oxide film on a substrate
EP0485802A1 (en) * 1990-10-30 1992-05-20 Nec Corporation Method of preventing corrosion of aluminium alloys
US5174856A (en) * 1991-08-26 1992-12-29 Applied Materials, Inc. Method for removal of photoresist over metal which also removes or inactivates corrosion-forming materials remaining from previous metal etch

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2306777A (en) * 1995-11-01 1997-05-07 Hyundai Electronics Ind Method for forming a metal wire
GB2306777B (en) * 1995-11-01 2000-03-08 Hyundai Electronics Ind Method for forming metal wire
US5852915A (en) * 1996-09-26 1998-12-29 R. R. Donnelley & Sons Company Method of making compact disc product
US6140243A (en) * 1996-12-12 2000-10-31 Texas Instruments Incorporated Low temperature process for post-etch defluoridation of metals
EP0851474A2 (en) * 1996-12-12 1998-07-01 Texas Instruments Inc. Improvements in or relating to integrated circuits
EP0851474A3 (en) * 1996-12-12 1998-12-23 Texas Instruments Inc. Improvements in or relating to integrated circuits
US6660634B1 (en) 1998-07-09 2003-12-09 Advanced Micro Devices, Inc. Method of forming reliable capped copper interconnects
US6492266B1 (en) * 1998-07-09 2002-12-10 Advanced Micro Devices, Inc. Method of forming reliable capped copper interconnects
US6613681B1 (en) * 1998-08-28 2003-09-02 Micron Technology, Inc. Method of removing etch residues
US7022612B2 (en) 1998-08-28 2006-04-04 Micron Technology, Inc. Method of removing etch residues
US6946401B2 (en) 1998-11-17 2005-09-20 Applied Materials, Inc. Plasma treatment for copper oxide reduction
US6355571B1 (en) 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US8183150B2 (en) 1998-11-17 2012-05-22 Applied Materials, Inc. Semiconductor device having silicon carbide and conductive pathway interface
WO2000029642A1 (en) * 1998-11-17 2000-05-25 Applied Materials, Inc. Removing oxides or other reducible contaminants from a substrate by plasma treatment
US6700202B2 (en) 1998-11-17 2004-03-02 Applied Materials, Inc. Semiconductor device having reduced oxidation interface
US6734102B2 (en) 1998-11-17 2004-05-11 Applied Materials Inc. Plasma treatment for copper oxide reduction
US6592770B1 (en) 1999-02-26 2003-07-15 Trikon Holdings Limited Method of treating an isulating layer
US6824699B2 (en) 1999-02-26 2004-11-30 Trikon Holdings Ltd. Method of treating an insulting layer
EP1081754A3 (en) * 1999-09-03 2001-12-05 Applied Materials, Inc. Cleaning contact area with successive fluoride and hydrogen plasmas
EP1081754A2 (en) * 1999-09-03 2001-03-07 Applied Materials, Inc. Cleaning contact area with successive fluoride and hydrogen plasmas
US8492287B2 (en) 2006-08-15 2013-07-23 Tokyo Electron Limited Substrate processing method
US9614045B2 (en) 2014-09-17 2017-04-04 Infineon Technologies Ag Method of processing a semiconductor device and chip package

Also Published As

Publication number Publication date Type
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