JPH09172083A - Metal wiring preparation of semiconductor element - Google Patents
Metal wiring preparation of semiconductor elementInfo
- Publication number
- JPH09172083A JPH09172083A JP8292015A JP29201596A JPH09172083A JP H09172083 A JPH09172083 A JP H09172083A JP 8292015 A JP8292015 A JP 8292015A JP 29201596 A JP29201596 A JP 29201596A JP H09172083 A JPH09172083 A JP H09172083A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- titanium nitride
- nitride layer
- metal wiring
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子の金属配
線製造方法に関する。The present invention relates to a method for manufacturing a metal wiring of a semiconductor device.
【０００２】[0002]
【従来の技術】半導体素子の高集積化に伴い、半導体素
子の内部で上下の導電配線を連結するため層間絶縁膜の
一定部分をエッチングして形成するコンタクトホール
は、自らの大きさと周辺配線との間隔が減少することに
よりコンタクトホールの縦横比であるアスペクト比（as
pect ratio、溝の深さ／溝の幅）が増加する。2. Description of the Related Art Along with the high integration of a semiconductor device, a contact hole formed by etching a certain portion of an interlayer insulating film in order to connect upper and lower conductive wires inside the semiconductor device has a size of its own and a size of a peripheral wiring. As a result, the aspect ratio (as
pect ratio, groove depth / groove width) increases.
【０００３】一般に、半導体素子の金属配線では他の材
料に比べ蒸着工程が簡単であり、低抵抗の特性を有する
アルミニウム（Ａｌ）系の金属が主に用いられる。Ａ１
系の金属層を介して半導体基板又は導電配線にコンタク
トする場合、前記金属層と半導体基板の界面で下部層の
原子が金属層に拡散されたり金属原子が基板に拡散して
スパイク現象が発生する。[0003] In general, in metal wiring of a semiconductor element, an evaporation process is simpler than other materials, and an aluminum (Al) -based metal having low resistance characteristics is mainly used. A1
When a semiconductor substrate or a conductive wiring is contacted through a metal layer of a system, a spike phenomenon occurs at the interface between the metal layer and the semiconductor substrate, where atoms in a lower layer are diffused into the metal layer or metal atoms are diffused into the substrate. .
【０００４】このような現象等を防ぎしかも更にコンタ
クト抵抗を減少させるため、コンタクトホールの低部面
にＴｉ／ＴｉＮ積層構造の障壁金属（barrier metal）
層を薄く蒸着した後、コンタクトホールを十分に満たす
ことができるＡ１系の金属層を蒸着し、パターニング工
程で半導体基板、又は下部導電層にコンタクトされる金
属配線を形成する。In order to prevent such a phenomenon and further reduce the contact resistance, a barrier metal having a Ti / TiN laminated structure is provided on the lower surface of the contact hole.
After depositing a thin layer, an A1-based metal layer capable of sufficiently filling the contact hole is deposited, and a metal wiring contacting the semiconductor substrate or the lower conductive layer is formed in a patterning process.
【０００５】[0005]
【発明が解決しようとする課題】前記Ａ１系の金属層
は、物理的気相成長法（physical vapor deposition、
以下ＰＶＤという）方法の１つであるスパッタリング方
法で蒸着しなければならないため段差被覆性が不良とな
り、その結果コンタクトホールでボイドが発生し半導体
素子の信頼性が低下する問題が発生する。The A1-based metal layer is formed by physical vapor deposition,
Since deposition must be performed by a sputtering method, which is one of the methods (hereinafter referred to as PVD), the step coverage is poor, and as a result, voids are generated in the contact holes and the reliability of the semiconductor element is reduced.
【０００６】これについて具体的に説明する。図７は、
従来の金属配線製造方法により製造した半導体素子の金
属配線を示した断面図である。半導体基板１１上に層間
絶縁膜１２を形成し、前記半導体基板１１でメタルコン
タクトに予定されている部分上側の層間絶縁膜１２を除
去しコンタクトホール１３を形成する。その次に、ＰＶ
Ｄ法のスパッタリング法で前記コンタクトホール１３を
介し、前記半導体基板１１とコンタクトするＴｉ層１４
ＡとＴｉＮ層１４Ｂを、順次積層してＴｉ層１４ＡとＴ
ｉＮ層１４Ｂの積層構造でなる障壁金属層１４を形成す
る。次に、前記障壁金属層１４上にメイン金属層として
Ａ１系の金属層１５、例えばＡ１−Ｃｕ−Ｓｉ合金をＰ
ＶＤ法で蒸着し、さらにＡｌ系の金属層１５上にＴｉＮ
でなる反射防止膜１６を形成する。This will be specifically described. FIG.
It is sectional drawing which showed the metal wiring of the semiconductor element manufactured by the conventional metal wiring manufacturing method. An interlayer insulating film 12 is formed on a semiconductor substrate 11, and the interlayer insulating film 12 on a portion of the semiconductor substrate 11 which is to be a metal contact is removed to form a contact hole 13. Next, PV
The Ti layer 14 that contacts the semiconductor substrate 11 through the contact hole 13 by the D method sputtering method.
A and a TiN layer 14B are sequentially stacked to form a Ti layer 14A and a TN layer 14B.
The barrier metal layer 14 having a stacked structure of the iN layer 14B is formed. Next, an A1-based metal layer 15, for example, an A1-Cu-Si alloy is formed on the barrier metal layer 14 as a main metal layer by P
VD deposition, and TiN on the Al-based metal layer 15
Is formed.
【０００７】ここで、Ｔｉ層１４Ａは半導体基板１１と
導電配線間のコンタクト抵抗を減少させ、ＴｉＮ層１４
Ｂは導電配線のコンタクト領域でＡ１系の金属層のスパ
イク現象を防止する役目を果たす。Here, the Ti layer 14A reduces the contact resistance between the semiconductor substrate 11 and the conductive wiring, and the TiN layer 14A
B serves to prevent a spike phenomenon of the A1-based metal layer in the contact region of the conductive wiring.
【０００８】しかし、前記金属層１５を蒸着する際、ア
スペクト比が大きいコンタクトホール１３の場合は、前
記金属層１５の段差被覆性が低下しコンタクトホール１
３の内部にボイド１７が発生し金属配線の信頼性が低下
する。However, when the metal layer 15 is deposited, if the contact hole 13 has a large aspect ratio, the step coverage of the metal layer 15 is reduced, and the contact hole 1 is removed.
Voids 17 are generated inside 3 and the reliability of the metal wiring is reduced.
【０００９】本発明の目的は、前記のようにＰＶＤ法に
よって金属層を蒸着しコンタクトホールを満たす代り
に、段差被覆性が良好なＣＶＤ法を用いて低抵抗を有す
るＴｉＮ層でコンタクトホールを満たした後、Ａ１系の
金属層を蒸着し下部の半導体基板にコンタクトされる金
属配線製造方法を提供することにある。An object of the present invention is to fill a contact hole with a TiN layer having a low resistance by using a CVD method with good step coverage instead of depositing a metal layer by the PVD method as described above and filling the contact hole. After that, an object of the present invention is to provide a method for manufacturing a metal wiring in which an A1-based metal layer is deposited and contacted with a lower semiconductor substrate.
【００１０】[0010]
【課題を解決するための手段】以上の課題を解決すべ
く、請求項１に記載の発明は、下部導電性上に層間絶縁
膜を形成する工程と、前記層間絶縁膜の一定部分をエッ
チングしコンタクトホールを形成する工程と、 表面全
体に薄い窒化チタン層を化学的気相成長法によって形成
する工程と、前記窒化チタン層の抵抗を減少させるため
前記窒化チタン層をプラズマ処理する工程と、前記窒化
チタン層を化学的気相成長法によって形成する工程と前
記窒化チタン層をプラズマ処理する工程が繰り返し行わ
れ、プラズマ処理された窒化チタン層によってコンタク
トホールを十分に満たす工程と、前記プラズマ処理され
た窒化チタン層をエッチングし、コンタクトホールにの
み前記プラズマ処理された窒化チタン層が満たされたコ
ンタクトプラグを形成する工程と、表面全体に金属層を
形成する工程とを含むことを特徴とする半導体素子の金
属配線製造方法である。In order to solve the above problems, the invention according to claim 1 comprises a step of forming an interlayer insulating film on the lower conductive layer, and a step of etching a certain portion of the interlayer insulating film. Forming a contact hole, forming a thin titanium nitride layer on the entire surface by chemical vapor deposition, plasma treating the titanium nitride layer to reduce the resistance of the titanium nitride layer, and The step of forming a titanium nitride layer by a chemical vapor deposition method and the step of plasma-treating the titanium nitride layer are repeated, and the step of sufficiently filling the contact holes with the plasma-treated titanium nitride layer and the plasma-treating step are performed. Etching the titanium nitride layer to form a contact plug filled with the plasma-treated titanium nitride layer only in the contact hole And a step of forming a metal layer on the entire surface thereof, which is a method for manufacturing a metal wiring of a semiconductor element.
【００１１】請求項２に記載の発明は、請求項１記載の
半導体素子の金属配線製造方法において、前記層間絶縁
膜の一定部分をエッチングしコンタクトホールを形成す
る工程の後に表面全体にチタン層を形成する工程を行
い、該チタン層を形成する工程の後に前記の薄い窒化チ
タン層を化学的気相成長法によって形成する工程を行う
ことを特徴とする。According to a second aspect of the present invention, in the method of manufacturing a metal wiring of a semiconductor device according to the first aspect, after a step of etching a predetermined portion of the interlayer insulating film to form a contact hole, a titanium layer is formed on the entire surface. A step of forming the thin titanium nitride layer by a chemical vapor deposition method after the step of forming the titanium layer.
【００１２】請求項３に記載の発明は、請求項１又は２
に記載の半導体素子の金属配線製造方法において、１回
の化学的気相成長法によって形成される薄い窒化チタン
層の厚さは、１００〜１０００オングストローム（Å）
であることを特徴とする。[0012] The invention according to claim 3 is the invention according to claim 1 or 2.
Wherein the thickness of the thin titanium nitride layer formed by one chemical vapor deposition method is 100 to 1000 angstroms (Å).
It is characterized by being.
【００１３】請求項４に記載の発明は、請求項１〜３の
いずれかに記載の半導体素子の金属配線製造方法におい
て、前記窒化チタン層は、液体ソースとしてテトラキス
ジメチルアミノチタニウム(Tetrakis Dimethy1 Amino T
itanium)又はテトラキスジエチルアミノチタニウム（Te
trakis Diethy1 Amino Titanium）を用いて形成するこ
とを特徴とする。According to a fourth aspect of the present invention, in the method for producing a metal wiring of a semiconductor device according to any one of the first to third aspects, the titanium nitride layer serves as a liquid source of tetrakisdimethylaminotitanium (Tetrakis Dimethy1 Amino T).
itanium) or tetrakisdiethylaminotitanium (Te
It is characterized by being formed using trakis Diethy1 Amino Titanium).
【００１４】請求項５に記載の発明は、請求項４に記載
の半導体素子の金属配線製造方法において、前記窒化チ
タン層は前記テトラキスジメチルアミノチタニウム又は
前記テトラキスジエチルアミノチタニウムにＮＨ3及び
ＮＦ3との混合ガスを混合したものをソースとして形成
することを特徴とする。According to a fifth aspect of the present invention, in the method for manufacturing a metal wiring of a semiconductor device according to the fourth aspect, the titanium nitride layer is formed by adding tetrakisdimethylaminotitanium or tetrakisdiethylaminotitanium to NH 3 and NF 3 . It is characterized in that a mixture of mixed gases is formed as a source.
【００１５】請求項６に記載の発明は、請求項４又は５
に記載の半導体素子の金属配線製造方法において、前記
窒化チタン層は前記ソースを熱分解させ、ヘリウムまた
は窒素をキャリアガスとして用い、圧力０.１〜５０tor
r、形成温度３００〜６００℃、形成時間５０〜１００
０秒の条件で形成することを特徴とする。The invention according to claim 6 is the invention according to claim 4 or 5.
In the method for manufacturing a metal wiring of a semiconductor device according to the item 1, the titanium nitride layer thermally decomposes the source and uses helium or nitrogen as a carrier gas at a pressure of 0.1 to 50 torr.
r, forming temperature 300 to 600 ° C., forming time 50 to 100
It is characterized in that it is formed under the condition of 0 seconds.
【００１６】請求項７に記載の発明は、請求項１〜６の
いずれかに記載の半導体素子の金属配線製造方法におい
て、前記窒化チタン層をプラズマ処理する工程は、窒素
ガス又は水素ガス、又はそれらの混合ガス雰囲気のプラ
ズマを用いることを特徴とする。According to a seventh aspect of the present invention, in the method for manufacturing a metal wiring of a semiconductor element according to any of the first to sixth aspects, the step of plasma-treating the titanium nitride layer is performed with nitrogen gas or hydrogen gas, or It is characterized by using plasma in a mixed gas atmosphere thereof.
【００１７】請求項８に記載の発明は、請求項１〜７の
いずれかに記載の半導体素子の金属配線製造方法におい
て、前記窒化チタン層をプラズマ処理する工程によって
窒化チタン層の一部、又は全部が低抵抗化されることを
特徴とする。According to an eighth aspect of the present invention, in the method for manufacturing a metal wiring of a semiconductor device according to any one of the first to seventh aspects, a part of the titanium nitride layer is formed by a plasma treatment of the titanium nitride layer, or All are characterized by low resistance.
【００１８】請求項９に記載の発明は、請求項１〜８の
いずれかに記載の半導体素子の金属配線製造方法におい
て、前記プラズマ処理の条件は流量５０〜７００sccm
（Standard Cubic Centimeter）、圧力０.１〜２０tor
r、温度５０〜６００℃であることを特徴とする。According to a ninth aspect of the present invention, in the method for manufacturing a metal wiring of a semiconductor device according to any one of the first to eighth aspects, the plasma treatment condition is a flow rate of 50 to 700 sccm.
(Standard Cubic Centimeter), pressure 0.1-20tor
r, a temperature of 50 to 600 ° C.
【００１９】請求項１０に記載の発明は、請求項１〜９
のいずれかに記載の半導体素子の金属配線製造方法にお
いて、前記金属層は、アルミニウム系の金属層であるこ
とを特徴とする。The invention according to a tenth aspect is the first to ninth aspects.
In the method of manufacturing a metal wiring of a semiconductor device according to any one of the above, the metal layer is an aluminum-based metal layer.
【００２０】請求項１１に記載の発明は、請求項２〜１
０のいずれかに記載の半導体素子の金属配線製造方法に
おいて、前記チタン層を、物理的気相成長法によって５
０〜３００オングストローム（Å）の厚さに形成するこ
とを特徴とする。The invention as defined in claim 11 is defined by claims 2 to 1.
0. In the method for manufacturing a metal wiring of a semiconductor device according to any one of 0 to 5, the titanium layer is formed by physical vapor deposition.
It is characterized in that it is formed to a thickness of 0 to 300 angstroms (Å).
【００２１】本発明の半導体素子の金属配線製造方法に
よれば、ＣＶＤ法で形成されたＴｉＮ層は抵抗が数千か
ら数万μΩcmの高い抵抗を有するが、本発明によりＴｉ
Ｎ層をＣＶＤ法で厚さ１００〜１０００オングストロー
ム（Å）で蒸着し、水素／窒素ガス雰囲気でプラズマ処
理すれば数百μΩcm以下の抵抗を得ることができる。さ
らに、本発明はＴｉＮ層をＣＶＤ法で形成すればコンタ
クトホールを容易に満たすことができ、ボイドが発生し
ないため信頼性の高い金属配線を得ることができる。According to the method for manufacturing a metal wiring of a semiconductor device of the present invention, the TiN layer formed by the CVD method has a high resistance of several thousands to tens of thousands of .mu..OMEGA.cm.
If an N layer is deposited by a CVD method to a thickness of 100 to 1000 angstroms (法) and plasma-treated in a hydrogen / nitrogen gas atmosphere, a resistance of several hundred μΩcm or less can be obtained. Furthermore, according to the present invention, if the TiN layer is formed by the CVD method, the contact hole can be easily filled and no void is generated, so that a highly reliable metal wiring can be obtained.
【００２２】[0022]
【発明の実施の形態】以下、本発明の半導体素子の金属
配線製造方法を図面１〜６を参照して詳細に説明する。
図１〜図６は、本発明の半導体素子の金属配線製造方法
の工程を示した図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a metal wiring of a semiconductor device according to the present invention will be described in detail with reference to FIGS.
1 to 6 are views showing steps of a method for manufacturing a metal wiring of a semiconductor device according to the present invention.
【００２３】先ず、半導体基板１、又は導電配線に層間
絶縁膜２を形成し、上部金属配線とのコンタクトに予定
されている部分の層間絶縁膜２を除去しコンタクトホー
ル３を形成する。その次に、前記構造の全表面にコンタ
クト抵抗減少のための層として比較的薄い、例えば５０
〜３００オングストローム（Å）程度の厚さのＴｉ層４
をＰＶＤ法で形成する（図１参照）。First, an interlayer insulating film 2 is formed on a semiconductor substrate 1 or a conductive wiring, and a portion of the interlayer insulating film 2 which is to be in contact with an upper metal wiring is removed to form a contact hole 3. Next, a relatively thin layer, for example, 50, is formed on the entire surface of the structure as a layer for reducing contact resistance.
Ti layer 4 having a thickness of about 300 Å (ー ム)
Is formed by a PVD method (see FIG. 1).
【００２４】その後、図２に示すように、Ｔｉ層４上に
ＣＶＤ法で第１ＴｉＮ層９Ａを、例えば１００〜１００
０オングストローム（Å）程度の厚さに形成する。第１
ＴｉＮ層９Ａは、テトラキスジメチルアミノチタニウム
（Tetrakis Dimethy1 Amino Titanium、Ｔｉ(Ｎ(ＣＨ3)
2)4、以下ＴＤＭＡＴという）や、テトラキスジエチル
アミノチタニウム（Tetrakis Diethy1 Amino Titaniu
m、Ｔｉ(Ｎ(Ｃ2Ｈ5)2)4、以下ＴＤＥＡＴという）とい
った液体ソースそれぞれに、ＮＨ3／ＮＦ3混合ガスを混
合したものをソースにして高温熱分解させ、ＨｅやＮ2
をキャリアーガスにしてＣＶＤ法で形成し、このときの
蒸着条件はＴＤＭＡＴやＴＤＥＡＴを含むキャリアーガ
スの圧力を０.１〜５０torr、成長温度を３００〜６０
０℃、蒸着時間を５０〜１０００秒程度にする。その次
に、Ｎ2又はＨ2若しくはそれらの混合ガス雰囲気のプラ
ズマで第１ＴｉＮ層９Ａの表面を処理する。それによ
り、第１ＴｉＮ層９Ａの約５０〜６００オングストロー
ム（Å）厚さがプラズマ処理されこの処理によって抵抗
が低くなる。プラズマ処理時の条件はＮ2又はＨ2若しく
はその混合ガス流量を５０〜７００sccmにし、圧力は
０.１〜２０torr、処理温度は５０〜６００℃、プラズ
マのＲＦパワーは５０〜１０００Ｗである。After that, as shown in FIG. 2, a first TiN layer 9A is formed on the Ti
It is formed to a thickness of about 0 Å (ー ム). First
The TiN layer 9A is made of tetrakis dimethylamino titanium (Titrakis Dimethy1 Amino Titanium, Ti (N (CH 3 )).
2 ) 4 , hereinafter referred to as TDMAT) or tetrakis diethylaminotitanium (Tetrakis Diethy1 Amino Titaniu)
m, Ti (N (C 2 H 5 ) 2 ) 4 (hereinafter referred to as TDEAT), and a mixture of NH 3 / NF 3 mixed gas as a source is subjected to high-temperature pyrolysis to obtain He or N 2
Is formed as a carrier gas by a CVD method. At this time, the deposition conditions are such that the pressure of the carrier gas containing TDMAT or TDEAT is 0.1 to 50 torr, and the growth temperature is 300 to 60 torr.
At 0 ° C., the deposition time is about 50 to 1000 seconds. Then, the surface of the first TiN layer 9A is treated with plasma in an atmosphere of N 2 or H 2 or a mixed gas thereof. As a result, the thickness of the first TiN layer 9A is about 50 to 600 angstroms (Å), and the resistance is lowered by the plasma processing. Conditions for the plasma processing are as follows: N 2 or H 2 or a mixed gas flow rate of 50 to 700 sccm, a pressure of 0.1 to 20 torr, a processing temperature of 50 to 600 ° C., and a plasma RF power of 50 to 1000 W.
【００２５】その後、第１ＴｉＮ層９Ａと同様な方法で
第２ＴｉＮ層９Ｂを形成し、その一部又は全部をプラズ
マ処理する（図３参照）。Thereafter, a second TiN layer 9B is formed in the same manner as the first TiN layer 9A, and a part or all of the second TiN layer 9B is subjected to plasma processing (see FIG. 3).
【００２６】そして、第２ＴｉＮ層９Ｂ上に前記第１Ｔ
ｉＮ層９Ａと同様な方法で第３ＴｉＮ層９Ｃを形成し、
プラズマ処理して低抵抗化させる（図４参照）。Then, the first T layer is formed on the second TiN layer 9B.
A third TiN layer 9C is formed in the same manner as the iN layer 9A,
The resistance is reduced by plasma treatment (see FIG. 4).
【００２７】その次に、前記第１〜第３ＴｉＮ層９Ａ、
９Ｂ、９Ｃを上から順次Ｔｉ層４の上部面が露出される
まで全面異方性エッチングを実施し前記コンタクトホー
ル３が第１〜第３ＴｉＮ層９Ａ、９Ｂ、９Ｃで満たされ
ているコンタクトプラグ１０を形成する（図５参照）。Next, the first to third TiN layers 9A,
9B and 9C are sequentially anisotropically etched from the top until the upper surface of the Ti layer 4 is exposed, so that the contact hole 3 is filled with the first to third TiN layers 9A, 9B and 9C. Is formed (see FIG. 5).
【００２８】その後、前記構造の全表面にＡ１系の金属
層５をＰＶＤ法で形成した後（図６）、Ａ１系の金属層
５とＴｉ層４を共にパターニングし、コンタクトプラグ
１０と接触するＴｉ層４及びＡ１系の金属層５のパター
ンから成る導電配線を形成する。Thereafter, an A1-based metal layer 5 is formed on the entire surface of the structure by the PVD method (FIG. 6), and then the A1-based metal layer 5 and the Ti layer 4 are patterned together to make contact with the contact plug 10. A conductive wiring composed of a pattern of the Ti layer 4 and the A1-based metal layer 5 is formed.
【００２９】上記の本発明の実施の形態では、ＴｉＮ層
の形成及びプラズマ処理工程を３回繰り返したが、一回
で形成されるＴｉＮ層の厚さを薄くし一連の工程を多数
回実施すれば、低抵抗のＴｉＮ層の割合が増加し金属配
線の抵抗が減少する。In the above embodiment of the present invention, the formation of the TiN layer and the plasma treatment process were repeated three times. However, the thickness of the TiN layer formed at one time was reduced, and a series of processes were performed many times. For example, the ratio of the low-resistance TiN layer increases, and the resistance of the metal wiring decreases.
【００３０】本発明の金属配線製造方法の第２の実施の
形態は、Ｔｉ層４を形成せず層間絶縁膜２上に直接第１
ＴｉＮ層９Ａを蒸着し、前述の工程を行うことである。In the second embodiment of the method for manufacturing a metal wiring according to the present invention, the first layer is formed directly on the interlayer insulating film 2 without forming the Ti layer 4.
That is, a TiN layer 9A is deposited and the above-described steps are performed.
【００３１】前記のように、コンタクトホール上部にＴ
ｉＮ層を多数回に亘って形成しプラズマ処理を行う場
合、ＴｉＮ層の抵抗が約数千〜数万μΩcmから数百μΩ
cm以下に減少する。これはＴｉＮ層ソースの高温熱分解
気相成長の際、ソースの不完全な熱分解によりＴｉＮ薄
膜内に多量の炭素及び酸素が含まれていて抵抗が高まる
が、プラズマ処理をすればＴｉＮ薄膜内に不完全に結合
されている炭素や酸素原子等が水素イオンと結合されＣ
Ｈ3、ＣＨ4、Ｈ2Ｏ等が生成し、それらは外部に発散
し、空間が窒素イオン等によって満たされてＴｉＮ結合
がより多く作られ抵抗が減少するためである。As described above, T is over the contact hole.
When the iN layer is formed a number of times and the plasma processing is performed, the resistance of the TiN layer is about several thousands to several tens of thousands μΩcm to several hundred μΩ
cm or less. This is because during the high-temperature pyrolysis vapor deposition of the TiN layer source, a large amount of carbon and oxygen are contained in the TiN thin film due to incomplete thermal decomposition of the source, and the resistance is increased. Incompletely bonded carbon and oxygen atoms are combined with hydrogen ions to form C
This is because H 3 , CH 4 , H 2 O, and the like are generated, diverge to the outside, and the space is filled with nitrogen ions and the like, so that more TiN bonds are formed and the resistance is reduced.
【００３２】前記では金属配線コンタクトのメタルコン
タクトを例に挙げたが、金属配線間コンタクトのビアコ
ンタクトでも本発明の製造方法を適用することができる
ことは勿論である。In the above description, the metal contact of the metal wiring contact has been described as an example. However, it goes without saying that the manufacturing method of the present invention can be applied to a via contact as a contact between metal wirings.
【００３３】[0033]
【発明の効果】以上で説明したように、本発明はコンタ
クトホールを介し下部導電層とコンタクトするＴｉＮ層
をＣＶＤ法で形成し、このＴｉＮ層をＮ2やＨ2、又はそ
の混合ガス雰囲気のプラズマで表面を処理する一連の工
程を繰り返し行いコンタクトホールを完全に満たすこと
により、コンタクトホールでボイドの発生を防止するこ
とができると共に、コンタクト抵抗を最小化させて金属
配線工程の収率を向上させ半導体素子の信頼性を向上さ
せることができる。As described above, according to the present invention, a TiN layer which is in contact with a lower conductive layer through a contact hole is formed by a CVD method, and this TiN layer is formed in an atmosphere of N 2 , H 2 , or a mixed gas atmosphere thereof. By repeating a series of processes that treat the surface with plasma to completely fill the contact hole, it is possible to prevent the occurrence of voids in the contact hole and minimize the contact resistance to improve the yield of the metal wiring process As a result, the reliability of the semiconductor element can be improved.
【図１】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 1 is a sectional view showing steps of a method for manufacturing a metal wiring of a semiconductor device according to the present invention in a stepwise manner.
【図２】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 2 is a sectional view showing steps of a method for manufacturing a metal wiring of a semiconductor device according to the present invention in a stepwise manner.
【図３】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 3 is a sectional view showing steps of a method for manufacturing a metal wiring of a semiconductor element according to the present invention in a stepwise manner.
【図４】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 4 is a sectional view showing steps of a method for manufacturing a metal wiring of a semiconductor element according to the present invention in a stepwise manner.
【図５】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 5 is a sectional view showing step by step the method of the present invention for producing a metal wiring of a semiconductor element.
【図６】本発明の半導体素子の金属配線製造方法の工程
を段階的に示す断面図である。FIG. 6 is a sectional view showing step by step the method of the present invention for producing a metal wiring of a semiconductor element.
【図７】従来技術による金属配線製造方法により製造し
た半導体素子の断面図である。FIG. 7 is a cross-sectional view of a semiconductor device manufactured by a conventional metal wiring manufacturing method.
１ 半導体基板 ２ 層間絶縁膜 ３ コンタクトホール ４ Ｔｉ層 ５ Ａ１系の金属層 ９Ａ、９Ｂ、９Ｃ ＴｉＮ層 １０ コンタクトプラグ REFERENCE SIGNS LIST 1 semiconductor substrate 2 interlayer insulating film 3 contact hole 4 Ti layer 5 Al-based metal layer 9A, 9B, 9C TiN layer 10 contact plug
Claims (11)
程と、 前記層間絶縁膜の一定部分をエッチングしコンタクトホ
ールを形成する工程と、 表面全体に薄い窒化チタン層
を化学的気相成長法によって形成する工程と、 前記窒化チタン層の抵抗を減少させるため前記窒化チタ
ン層をプラズマ処理する工程と、 前記窒化チタン層を化学的気相成長法によって形成する
工程と前記窒化チタン層をプラズマ処理する工程が繰り
返し行われ、プラズマ処理された窒化チタン層によって
コンタクトホールを十分に満たす工程と、 前記プラズマ処理された窒化チタン層をエッチングし、
コンタクトホールにのみ前記プラズマ処理された窒化チ
タン層が満たされたコンタクトプラグを形成する工程
と、 表面全体に金属層を形成する工程とを含むことを特徴と
する半導体素子の金属配線製造方法。1. A step of forming an interlayer insulating film on the lower conductive layer, a step of etching a certain portion of the interlayer insulating film to form a contact hole, and a chemical vapor deposition of a thin titanium nitride layer on the entire surface. Forming the titanium nitride layer by plasma, treating the titanium nitride layer by plasma to reduce the resistance of the titanium nitride layer, forming the titanium nitride layer by chemical vapor deposition, and plasma-treating the titanium nitride layer. The step of treating is repeated, the step of sufficiently filling the contact hole with the plasma-treated titanium nitride layer, and etching the plasma-treated titanium nitride layer,
A method of manufacturing a metal wiring of a semiconductor device, comprising: a step of forming a contact plug in which only the contact hole is filled with the plasma-treated titanium nitride layer; and a step of forming a metal layer on the entire surface.
コンタクトホールを形成する工程の後に表面全体にチタ
ン層を形成する工程を行い、該チタン層を形成する工程
の後に前記の薄い窒化チタン層を化学的気相成長法によ
って形成する工程を行うことを特徴とする請求項１記載
の半導体素子の金属配線製造方法。2. A step of forming a titanium layer on the entire surface after the step of etching a predetermined portion of the interlayer insulating film to form a contact hole, and the step of forming the titanium layer after the step of forming the titanium layer. 2. The method according to claim 1, wherein a step of forming the metal wiring by chemical vapor deposition is performed.
る薄い窒化チタン層の厚さは、１００〜１０００オング
ストロームであることを特徴とする請求項１又は２に記
載の半導体素子の金属配線製造方法。3. The metal according to claim 1, wherein the thickness of the thin titanium nitride layer formed by one chemical vapor deposition is 100 to 1000 Å. Wiring manufacturing method.
トラキスジメチルアミノチタニウム(Tetrakis Dimethy1
Amino Titanium)又はテトラキスジエチルアミノチタニ
ウム（Tetrakis Diethy1 Amino Titanium）を用いて形
成することを特徴とする請求項１〜３のいずれかに記載
の半導体素子の金属配線製造方法。4. The titanium nitride layer is used as a liquid source for tetrakisdimethylaminotitanium (Tetrakis Dimethy1).
Amino Titanium) or tetrakis diethylamino titanium (Tetrakis Diethy1 Amino Titanium) is used, The metal wiring manufacturing method of the semiconductor element in any one of Claims 1-3 characterized by the above-mentioned.
ルアミノチタニウム又は前記テトラキスジエチルアミノ
チタニウムにＮＨ3及びＮＦ3との混合ガスを混合したも
のをソースとして形成することを特徴とする請求項４に
記載の半導体素子の金属配線製造方法。5. The titanium nitride layer is formed by using, as a source, the tetrakisdimethylaminotitanium or the tetrakisdiethylaminotitanium mixed with a mixed gas of NH 3 and NF 3 . Method for manufacturing metal wiring of semiconductor device.
せ、ヘリウムまたは窒素をキャリアガスとして用い、圧
力０.１〜５０torr、形成温度３００〜６００℃、形成
時間５０〜１０００秒の条件で形成することを特徴とす
る請求項４又は５に記載の半導体素子の金属配線製造方
法。6. The titanium nitride layer is formed by thermally decomposing the source and using helium or nitrogen as a carrier gas under the conditions of a pressure of 0.1 to 50 torr, a forming temperature of 300 to 600 ° C., and a forming time of 50 to 1000 seconds. The method for manufacturing metal wiring of a semiconductor device according to claim 4 or 5, wherein
は、窒素ガス又は水素ガス、又はそれらの混合ガス雰囲
気のプラズマを用いることを特徴とする請求項１〜６の
いずれかに記載の半導体素子の金属配線製造方法。7. The semiconductor element according to claim 1, wherein the step of plasma-treating the titanium nitride layer uses plasma of nitrogen gas, hydrogen gas, or a mixed gas atmosphere thereof. Method for manufacturing metal wiring of.
によって窒化チタン層の一部、又は全部が低抵抗化され
ることを特徴とする請求項１〜７のいずれかに記載の半
導体素子の金属配線製造方法。8. The metal of a semiconductor device according to claim 1, wherein a part or all of the titanium nitride layer has a low resistance in the step of plasma-treating the titanium nitride layer. Wiring manufacturing method.
０sccm、圧力０.１〜２０torr、温度５０〜６００℃で
あることを特徴とする請求項１〜８のいずれかに記載の
半導体素子の金属配線製造方法。9. The condition of the plasma treatment is a flow rate of 50 to 70.
The method for producing metal wiring of a semiconductor device according to claim 1, wherein the pressure is 0 sccm, the pressure is 0.1 to 20 torr, and the temperature is 50 to 600 ° C. 9.
であることを特徴とする請求項１〜９のいずれかに記載
の半導体素子の金属配線製造方法。10. The method of manufacturing a metal wiring of a semiconductor element according to claim 1, wherein the metal layer is an aluminum-based metal layer.
って５０〜３００オングストロームの厚さに形成するこ
とを特徴とする請求項２〜１０のいずれかに記載の半導
体素子の金属配線製造方法。11. The method for producing metal wiring of a semiconductor device according to claim 2, wherein the titanium layer is formed to a thickness of 50 to 300 angstroms by a physical vapor deposition method. .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1995P-39165 | 1995-11-01 | ||
| KR1019950039165A KR100218728B1 (en) | 1995-11-01 | 1995-11-01 | Manufacturing method of metal interconnection of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09172083A true JPH09172083A (en) | 1997-06-30 |
| JP2760490B2 JP2760490B2 (en) | 1998-05-28 |
Family
ID=19432609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8292015A Expired - Fee Related JP2760490B2 (en) | 1995-11-01 | 1996-11-01 | Method for manufacturing metal wiring of semiconductor element |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP2760490B2 (en) |
| KR (1) | KR100218728B1 (en) |
| CN (1) | CN1075244C (en) |
| DE (1) | DE19645033C2 (en) |
| GB (1) | GB2306777B (en) |
| TW (1) | TW382764B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001257177A (en) * | 2000-02-01 | 2001-09-21 | Applied Materials Inc | Treatment of metal nitride/metal stack |
| JP2001516153A (en) * | 1997-09-05 | 2001-09-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Borderless via with CVD barrier layer |
| JP2002510145A (en) * | 1998-01-20 | 2002-04-02 | アプライド マテリアルズ インコーポレイテッド | Plasma annealing of substrates to improve adhesion |
| JP2008277837A (en) * | 2007-05-03 | 2008-11-13 | Samsung Electronics Co Ltd | Method of forming semiconductor device including diffusion barrier film |
| WO2013103076A1 (en) * | 2012-01-05 | 2013-07-11 | 東京エレクトロン株式会社 | Method for forming tin film and storage medium |
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|---|---|---|---|---|
| GB2322963B (en) * | 1996-09-07 | 1999-02-24 | United Microelectronics Corp | Method of fabricating a conductive plug |
| KR100226742B1 (en) * | 1996-12-24 | 1999-10-15 | 구본준 | Method for forming metal interconnection layer of semiconductor device |
| NL1005653C2 (en) * | 1997-03-26 | 1998-09-29 | United Microelectronics Corp | Conductive plug manufacture |
| US6037252A (en) * | 1997-11-05 | 2000-03-14 | Tokyo Electron Limited | Method of titanium nitride contact plug formation |
| US6432479B2 (en) | 1997-12-02 | 2002-08-13 | Applied Materials, Inc. | Method for in-situ, post deposition surface passivation of a chemical vapor deposited film |
| KR100458295B1 (en) * | 1997-12-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Contact plug formation method of semiconductor device |
| KR100558034B1 (en) * | 1999-06-30 | 2006-03-07 | 주식회사 하이닉스반도체 | Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process |
| DE10208714B4 (en) | 2002-02-28 | 2006-08-31 | Infineon Technologies Ag | Manufacturing method for a contact for an integrated circuit |
| JP2006344684A (en) | 2005-06-07 | 2006-12-21 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| CN101459121B (en) * | 2007-12-13 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Through hole and through hole forming method |
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|---|---|---|---|---|
| US5278099A (en) * | 1985-05-13 | 1994-01-11 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having wiring electrodes |
| JPS62265718A (en) * | 1986-05-13 | 1987-11-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04216621A (en) * | 1990-12-18 | 1992-08-06 | Seiko Instr Inc | Depositing method for thin film |
| US5175126A (en) * | 1990-12-27 | 1992-12-29 | Intel Corporation | Process of making titanium nitride barrier layer |
| US5089438A (en) * | 1991-04-26 | 1992-02-18 | At&T Bell Laboratories | Method of making an article comprising a TiNx layer |
| US5312774A (en) * | 1991-12-05 | 1994-05-17 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device comprising titanium |
| WO1993017453A2 (en) * | 1992-02-26 | 1993-09-02 | Materials Research Corporation | Ammonia plasma treatment of silicide contact surfaces in semiconductor devices |
| EP0571691B1 (en) * | 1992-05-27 | 1996-09-18 | STMicroelectronics S.r.l. | Metallization over tungsten plugs |
| US5416045A (en) * | 1993-02-18 | 1995-05-16 | Micron Technology, Inc. | Method for chemical vapor depositing a titanium nitride layer on a semiconductor wafer and method of annealing tin films |
| KR0144956B1 (en) * | 1994-06-10 | 1998-08-17 | 김광호 | Forming method of wiring |
| JPH0926387A (en) * | 1995-07-11 | 1997-01-28 | Tokyo Seimitsu Co Ltd | Liquid specific gravity detecting method and working fluid specific gravity detector |
-
1995
- 1995-11-01 KR KR1019950039165A patent/KR100218728B1/en not_active IP Right Cessation
-
1996
- 1996-10-30 GB GB9622538A patent/GB2306777B/en not_active Expired - Fee Related
- 1996-10-30 TW TW085113237A patent/TW382764B/en not_active IP Right Cessation
- 1996-10-31 DE DE19645033A patent/DE19645033C2/en not_active Expired - Fee Related
- 1996-11-01 CN CN96120181A patent/CN1075244C/en not_active Expired - Fee Related
- 1996-11-01 JP JP8292015A patent/JP2760490B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001516153A (en) * | 1997-09-05 | 2001-09-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Borderless via with CVD barrier layer |
| JP2002510145A (en) * | 1998-01-20 | 2002-04-02 | アプライド マテリアルズ インコーポレイテッド | Plasma annealing of substrates to improve adhesion |
| JP2001257177A (en) * | 2000-02-01 | 2001-09-21 | Applied Materials Inc | Treatment of metal nitride/metal stack |
| JP2008277837A (en) * | 2007-05-03 | 2008-11-13 | Samsung Electronics Co Ltd | Method of forming semiconductor device including diffusion barrier film |
| WO2013103076A1 (en) * | 2012-01-05 | 2013-07-11 | 東京エレクトロン株式会社 | Method for forming tin film and storage medium |
| JP2013139609A (en) * | 2012-01-05 | 2013-07-18 | Tokyo Electron Ltd | Method for forming tin film and storage medium |
| US9257278B2 (en) | 2012-01-05 | 2016-02-09 | Tokyo Electron Limited | Method for forming TiN and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1151610A (en) | 1997-06-11 |
| GB2306777A (en) | 1997-05-07 |
| TW382764B (en) | 2000-02-21 |
| CN1075244C (en) | 2001-11-21 |
| GB9622538D0 (en) | 1997-01-08 |
| KR100218728B1 (en) | 1999-09-01 |
| DE19645033C2 (en) | 2002-09-12 |
| GB2306777B (en) | 2000-03-08 |
| KR970030327A (en) | 1997-06-26 |
| JP2760490B2 (en) | 1998-05-28 |
| DE19645033A1 (en) | 1997-05-07 |
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