DE19548053A1 - Verfahren zum Betrieb einer SRAM MOS-Transistor Speicherzelle - Google Patents
Verfahren zum Betrieb einer SRAM MOS-Transistor SpeicherzelleInfo
- Publication number
- DE19548053A1 DE19548053A1 DE19548053A DE19548053A DE19548053A1 DE 19548053 A1 DE19548053 A1 DE 19548053A1 DE 19548053 A DE19548053 A DE 19548053A DE 19548053 A DE19548053 A DE 19548053A DE 19548053 A1 DE19548053 A1 DE 19548053A1
- Authority
- DE
- Germany
- Prior art keywords
- memory cell
- transistor
- sram
- vdd
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19548053A DE19548053A1 (de) | 1995-12-21 | 1995-12-21 | Verfahren zum Betrieb einer SRAM MOS-Transistor Speicherzelle |
DE59602127T DE59602127D1 (de) | 1995-12-21 | 1996-12-12 | Verfahren zum betrieb einer sram mos-transistor speicherzelle |
US09/091,713 US5973965A (en) | 1995-12-21 | 1996-12-12 | Method for operating a SRAM MOS transistor memory cell |
JP9523207A JPH11510300A (ja) | 1995-12-21 | 1996-12-12 | Sram―mosトランジスタメモリセルの駆動方法 |
PCT/DE1996/002394 WO1997023878A2 (fr) | 1995-12-21 | 1996-12-12 | Procede d'actionnement d'une cellule de memoire ram statique a transistors mos |
EP96946189A EP0868725B1 (fr) | 1995-12-21 | 1996-12-12 | Procede d'actionnement d'une cellule de memoire ram statique a transistors mos |
KR10-1998-0703764A KR100491578B1 (ko) | 1995-12-21 | 1996-12-12 | Srammos트랜지스터메모리셀의구동방법 |
HK98111909A HK1010935A1 (en) | 1995-12-21 | 1998-11-10 | Method of operating an sram mos transistor storage cell sram |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19548053A DE19548053A1 (de) | 1995-12-21 | 1995-12-21 | Verfahren zum Betrieb einer SRAM MOS-Transistor Speicherzelle |
Publications (1)
Publication Number | Publication Date |
---|---|
DE19548053A1 true DE19548053A1 (de) | 1997-07-03 |
Family
ID=7780961
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19548053A Withdrawn DE19548053A1 (de) | 1995-12-21 | 1995-12-21 | Verfahren zum Betrieb einer SRAM MOS-Transistor Speicherzelle |
DE59602127T Expired - Lifetime DE59602127D1 (de) | 1995-12-21 | 1996-12-12 | Verfahren zum betrieb einer sram mos-transistor speicherzelle |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE59602127T Expired - Lifetime DE59602127D1 (de) | 1995-12-21 | 1996-12-12 | Verfahren zum betrieb einer sram mos-transistor speicherzelle |
Country Status (7)
Country | Link |
---|---|
US (1) | US5973965A (fr) |
EP (1) | EP0868725B1 (fr) |
JP (1) | JPH11510300A (fr) |
KR (1) | KR100491578B1 (fr) |
DE (2) | DE19548053A1 (fr) |
HK (1) | HK1010935A1 (fr) |
WO (1) | WO1997023878A2 (fr) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6804143B1 (en) | 2003-04-02 | 2004-10-12 | Cogent Chipware Inc. | Write-assisted SRAM bit cell |
US7915681B2 (en) | 2007-06-18 | 2011-03-29 | Infineon Technologies Ag | Transistor with reduced charge carrier mobility |
US7948791B1 (en) * | 2009-01-15 | 2011-05-24 | Xilinx, Inc. | Memory array and method of implementing a memory array |
FR2970589B1 (fr) | 2011-01-19 | 2013-02-15 | Centre Nat Rech Scient | Cellule mémoire volatile/non volatile |
FR2970593B1 (fr) | 2011-01-19 | 2013-08-02 | Centre Nat Rech Scient | Cellule mémoire volatile/non volatile compacte |
FR2970592B1 (fr) | 2011-01-19 | 2013-02-15 | Centre Nat Rech Scient | Cellule mémoire volatile/non volatile programmable |
FR2976712B1 (fr) | 2011-06-15 | 2014-01-31 | Centre Nat Rech Scient | Element de memoire non-volatile |
FR2976711B1 (fr) * | 2011-06-15 | 2014-01-31 | Centre Nat Rech Scient | Cellule memoire avec memorisation volatile et non volatile |
US8593861B2 (en) | 2011-10-10 | 2013-11-26 | International Business Machines Corporation | Asymmetric memory cells |
JP6115059B2 (ja) * | 2012-09-20 | 2017-04-19 | 富士通株式会社 | 半導体記憶装置、及び、情報処理装置 |
FR3004576B1 (fr) | 2013-04-15 | 2019-11-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Cellule memoire avec memorisation de donnees non volatile |
FR3004577A1 (fr) | 2013-04-15 | 2014-10-17 | Commissariat Energie Atomique | |
FR3008219B1 (fr) | 2013-07-05 | 2016-12-09 | Commissariat Energie Atomique | Dispositif a memoire non volatile |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4447891A (en) * | 1980-09-26 | 1984-05-08 | Matsushita Electric Industrial Co., Ltd. | Simultaneous read-write IGFET memory cell |
US5040146A (en) * | 1989-04-21 | 1991-08-13 | Siemens Aktiengesellschaft | Static memory cell |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0233968B1 (fr) * | 1986-02-21 | 1990-11-28 | Ibm Deutschland Gmbh | Cellule de mémoire statique sans commande d'horloge |
JP3373632B2 (ja) * | 1993-03-31 | 2003-02-04 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3253745B2 (ja) * | 1993-04-28 | 2002-02-04 | 富士通株式会社 | 半導体記憶装置 |
JP3609868B2 (ja) * | 1995-05-30 | 2005-01-12 | 株式会社ルネサステクノロジ | スタティック型半導体記憶装置 |
US5715191A (en) * | 1995-10-25 | 1998-02-03 | Matsushita Electric Industrial Co., Ltd. | Static random access memory having variable supply voltages to the memory cells and method of operating thereof |
-
1995
- 1995-12-21 DE DE19548053A patent/DE19548053A1/de not_active Withdrawn
-
1996
- 1996-12-12 EP EP96946189A patent/EP0868725B1/fr not_active Expired - Lifetime
- 1996-12-12 US US09/091,713 patent/US5973965A/en not_active Expired - Lifetime
- 1996-12-12 KR KR10-1998-0703764A patent/KR100491578B1/ko not_active IP Right Cessation
- 1996-12-12 DE DE59602127T patent/DE59602127D1/de not_active Expired - Lifetime
- 1996-12-12 WO PCT/DE1996/002394 patent/WO1997023878A2/fr active IP Right Grant
- 1996-12-12 JP JP9523207A patent/JPH11510300A/ja active Pending
-
1998
- 1998-11-10 HK HK98111909A patent/HK1010935A1/xx not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4447891A (en) * | 1980-09-26 | 1984-05-08 | Matsushita Electric Industrial Co., Ltd. | Simultaneous read-write IGFET memory cell |
US5040146A (en) * | 1989-04-21 | 1991-08-13 | Siemens Aktiengesellschaft | Static memory cell |
Also Published As
Publication number | Publication date |
---|---|
EP0868725B1 (fr) | 1999-06-02 |
WO1997023878A2 (fr) | 1997-07-03 |
KR100491578B1 (ko) | 2005-08-05 |
KR19990071492A (ko) | 1999-09-27 |
JPH11510300A (ja) | 1999-09-07 |
US5973965A (en) | 1999-10-26 |
HK1010935A1 (en) | 1999-07-02 |
EP0868725A2 (fr) | 1998-10-07 |
DE59602127D1 (de) | 1999-07-08 |
WO1997023878A3 (fr) | 1997-08-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8130 | Withdrawal |