DE1904503B2 - Verfahren zum herstellen monolithischer halbleiteranordnungen - Google Patents

Verfahren zum herstellen monolithischer halbleiteranordnungen

Info

Publication number
DE1904503B2
DE1904503B2 DE19691904503 DE1904503A DE1904503B2 DE 1904503 B2 DE1904503 B2 DE 1904503B2 DE 19691904503 DE19691904503 DE 19691904503 DE 1904503 A DE1904503 A DE 1904503A DE 1904503 B2 DE1904503 B2 DE 1904503B2
Authority
DE
Germany
Prior art keywords
zones
conductivity type
epitaxial layer
diffusion
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19691904503
Other languages
German (de)
English (en)
Other versions
DE1904503A1 (de
Inventor
Vincent John Murray Hill Murphy Bernard Thomas New Providence. NJ Ghnski (V St A )
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE1904503A1 publication Critical patent/DE1904503A1/de
Publication of DE1904503B2 publication Critical patent/DE1904503B2/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • H10D84/403Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/406Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/765Making of isolation regions between components by field effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Recrystallisation Techniques (AREA)
DE19691904503 1968-02-05 1969-01-30 Verfahren zum herstellen monolithischer halbleiteranordnungen Pending DE1904503B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70316568A 1968-02-05 1968-02-05

Publications (2)

Publication Number Publication Date
DE1904503A1 DE1904503A1 (de) 1969-11-27
DE1904503B2 true DE1904503B2 (de) 1971-06-03

Family

ID=24824294

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19691904503 Pending DE1904503B2 (de) 1968-02-05 1969-01-30 Verfahren zum herstellen monolithischer halbleiteranordnungen

Country Status (7)

Country Link
BE (1) BE726353A (en, 2012)
CH (1) CH502000A (en, 2012)
DE (1) DE1904503B2 (en, 2012)
ES (1) ES363184A1 (en, 2012)
FR (1) FR1600658A (en, 2012)
IL (1) IL31355A (en, 2012)
NL (1) NL6901819A (en, 2012)

Also Published As

Publication number Publication date
BE726353A (en, 2012) 1969-05-29
ES363184A1 (es) 1970-11-16
IL31355A0 (en) 1969-02-27
DE1904503A1 (de) 1969-11-27
NL6901819A (en, 2012) 1969-08-07
CH502000A (de) 1971-01-15
FR1600658A (en, 2012) 1970-07-27
IL31355A (en) 1971-11-29

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