DE1614877B2 - Verfahren zum herstellen eines planartransistors - Google Patents

Verfahren zum herstellen eines planartransistors

Info

Publication number
DE1614877B2
DE1614877B2 DE1967T0035057 DET0035057A DE1614877B2 DE 1614877 B2 DE1614877 B2 DE 1614877B2 DE 1967T0035057 DE1967T0035057 DE 1967T0035057 DE T0035057 A DET0035057 A DE T0035057A DE 1614877 B2 DE1614877 B2 DE 1614877B2
Authority
DE
Germany
Prior art keywords
diffusion
base
zone
emitter
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE1967T0035057
Other languages
German (de)
English (en)
Other versions
DE1614877A1 (de
DE1614877C3 (enrdf_load_stackoverflow
Inventor
Peter; Hefner Heinz-Achim Dipl.-Ing.; 7100 Heilbronn; Ehlbeck Heinz-Wilhelm 7103 Schwaigern Conze
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Patentverwertungs GmbH
Original Assignee
Telefunken Patentverwertungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Patentverwertungs GmbH filed Critical Telefunken Patentverwertungs GmbH
Priority to DE1967T0035057 priority Critical patent/DE1614877B2/de
Publication of DE1614877A1 publication Critical patent/DE1614877A1/de
Publication of DE1614877B2 publication Critical patent/DE1614877B2/de
Application granted granted Critical
Publication of DE1614877C3 publication Critical patent/DE1614877C3/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
DE1967T0035057 1967-10-19 1967-10-19 Verfahren zum herstellen eines planartransistors Granted DE1614877B2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE1967T0035057 DE1614877B2 (de) 1967-10-19 1967-10-19 Verfahren zum herstellen eines planartransistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1967T0035057 DE1614877B2 (de) 1967-10-19 1967-10-19 Verfahren zum herstellen eines planartransistors

Publications (3)

Publication Number Publication Date
DE1614877A1 DE1614877A1 (de) 1970-12-23
DE1614877B2 true DE1614877B2 (de) 1978-02-02
DE1614877C3 DE1614877C3 (enrdf_load_stackoverflow) 1978-10-19

Family

ID=7558944

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1967T0035057 Granted DE1614877B2 (de) 1967-10-19 1967-10-19 Verfahren zum herstellen eines planartransistors

Country Status (1)

Country Link
DE (1) DE1614877B2 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2417854A1 (fr) * 1978-02-21 1979-09-14 Radiotechnique Compelec Transistor comportant une zone resistive integree dans sa region d'emetteur

Also Published As

Publication number Publication date
DE1614877A1 (de) 1970-12-23
DE1614877C3 (enrdf_load_stackoverflow) 1978-10-19

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
EHJ Ceased/non-payment of the annual fee