DE112007001578T5 - Lateraler Fet mit Trench-Gate mit direktem Source-Drain-Strompfad - Google Patents

Lateraler Fet mit Trench-Gate mit direktem Source-Drain-Strompfad Download PDF

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Publication number
DE112007001578T5
DE112007001578T5 DE112007001578T DE112007001578T DE112007001578T5 DE 112007001578 T5 DE112007001578 T5 DE 112007001578T5 DE 112007001578 T DE112007001578 T DE 112007001578T DE 112007001578 T DE112007001578 T DE 112007001578T DE 112007001578 T5 DE112007001578 T5 DE 112007001578T5
Authority
DE
Germany
Prior art keywords
conductivity type
stack
silicon layers
region
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE112007001578T
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German (de)
English (en)
Inventor
Chang-ki Pungnyun Jeon
Gary Dolny
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE112007001578T5 publication Critical patent/DE112007001578T5/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/658—Lateral DMOS [LDMOS] FETs having trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE112007001578T 2006-06-29 2007-06-25 Lateraler Fet mit Trench-Gate mit direktem Source-Drain-Strompfad Withdrawn DE112007001578T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/479,149 2006-06-29
US11/479,149 US7804150B2 (en) 2006-06-29 2006-06-29 Lateral trench gate FET with direct source-drain current path
PCT/US2007/072034 WO2008002879A2 (en) 2006-06-29 2007-06-25 Lateral trench gate fet with direct source-drain current path

Publications (1)

Publication Number Publication Date
DE112007001578T5 true DE112007001578T5 (de) 2009-05-14

Family

ID=38846448

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112007001578T Withdrawn DE112007001578T5 (de) 2006-06-29 2007-06-25 Lateraler Fet mit Trench-Gate mit direktem Source-Drain-Strompfad

Country Status (7)

Country Link
US (2) US7804150B2 (enExample)
JP (1) JP2009543353A (enExample)
KR (1) KR101375887B1 (enExample)
CN (1) CN101479851B (enExample)
DE (1) DE112007001578T5 (enExample)
TW (1) TW200810121A (enExample)
WO (1) WO2008002879A2 (enExample)

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US7804150B2 (en) 2006-06-29 2010-09-28 Fairchild Semiconductor Corporation Lateral trench gate FET with direct source-drain current path
US8674434B2 (en) * 2008-03-24 2014-03-18 Micron Technology, Inc. Impact ionization devices
KR101418398B1 (ko) 2008-07-04 2014-07-11 페어차일드코리아반도체 주식회사 필드 형성층을 구비하는 고전압 반도체소자 및 그 제조방법
US8482065B2 (en) * 2008-11-25 2013-07-09 Newport Fab, Llc MOS transistor with a reduced on-resistance and area product
US8004051B2 (en) 2009-02-06 2011-08-23 Texas Instruments Incorporated Lateral trench MOSFET having a field plate
US7943445B2 (en) 2009-02-19 2011-05-17 International Business Machines Corporation Asymmetric junction field effect transistor
US20120044796A1 (en) 2009-04-10 2012-02-23 Pantech Co., Ltd. Method for generating signal pattern using modulus or sequence, and device thereof
US8575695B2 (en) * 2009-11-30 2013-11-05 Alpha And Omega Semiconductor Incorporated Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode
JP5636254B2 (ja) * 2009-12-15 2014-12-03 株式会社東芝 半導体装置
CN101916783B (zh) * 2010-08-13 2012-07-04 复旦大学 一种凹陷沟道的横向和纵向扩散型场效应晶体管及其制造方法
CN103035674B (zh) * 2012-10-22 2015-10-14 上海华虹宏力半导体制造有限公司 射频横向双扩散场效应晶体管及其制造方法
US9059324B2 (en) * 2013-06-30 2015-06-16 Texas Instruments Incorporated Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
CN105556647B (zh) * 2013-07-19 2017-06-13 日产自动车株式会社 半导体装置及其制造方法
CN103762241B (zh) * 2014-01-02 2016-08-24 杭州电子科技大学 一种梳状栅纵向沟道soi ldmos单元
JP6340200B2 (ja) * 2014-01-27 2018-06-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10186573B2 (en) * 2015-09-14 2019-01-22 Maxpower Semiconductor, Inc. Lateral power MOSFET with non-horizontal RESURF structure
US10243039B2 (en) * 2016-03-22 2019-03-26 General Electric Company Super-junction semiconductor power devices with fast switching capability
US11329150B2 (en) * 2020-04-14 2022-05-10 Nxp Usa, Inc. Termination for trench field plate power MOSFET
US11837658B1 (en) * 2022-06-21 2023-12-05 K. Eklund Innovation Semiconductor device comprising a lateral super junction field effect transistor
US20230411447A1 (en) * 2022-06-21 2023-12-21 K. Eklund Innovation Semiconductor device comprising a lateral super junction field effect transistor

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US4626879A (en) * 1982-12-21 1986-12-02 North American Philips Corporation Lateral double-diffused MOS transistor devices suitable for source-follower applications
US5640034A (en) * 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
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US5629543A (en) * 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US6163051A (en) * 1995-08-24 2000-12-19 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
JPH09266311A (ja) * 1996-01-22 1997-10-07 Fuji Electric Co Ltd 半導体装置及びその製造方法
US6734496B2 (en) * 1996-01-22 2004-05-11 Fuji Electric Co., Ltd. Semiconductor device
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
DE19818300C1 (de) * 1998-04-23 1999-07-22 Siemens Ag Lateraler Hochvolt-Seitenwandtransistor
JP3356162B2 (ja) * 1999-10-19 2002-12-09 株式会社デンソー 半導体装置及びその製造方法
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JP4764987B2 (ja) * 2000-09-05 2011-09-07 富士電機株式会社 超接合半導体素子
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US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
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JP4225177B2 (ja) * 2002-12-18 2009-02-18 株式会社デンソー 半導体装置およびその製造方法
DE10309400B4 (de) * 2003-03-04 2009-07-30 Infineon Technologies Ag Halbleiterbauelement mit erhöhter Spannungsfestigkeit und/oder verringertem Einschaltwiderstand
JP4590884B2 (ja) * 2003-06-13 2010-12-01 株式会社デンソー 半導体装置およびその製造方法
US7126166B2 (en) * 2004-03-11 2006-10-24 Semiconductor Components Industries, L.L.C. High voltage lateral FET structure with improved on resistance performance
KR101254835B1 (ko) * 2005-05-26 2013-04-15 페어차일드 세미컨덕터 코포레이션 트랜치-게이트 전계 효과 트랜지스터 및 그 형성 방법
US7804150B2 (en) 2006-06-29 2010-09-28 Fairchild Semiconductor Corporation Lateral trench gate FET with direct source-drain current path

Also Published As

Publication number Publication date
WO2008002879A2 (en) 2008-01-03
US8097510B2 (en) 2012-01-17
KR101375887B1 (ko) 2014-03-18
US20110014760A1 (en) 2011-01-20
CN101479851B (zh) 2011-01-12
TW200810121A (en) 2008-02-16
CN101479851A (zh) 2009-07-08
US7804150B2 (en) 2010-09-28
US20080001198A1 (en) 2008-01-03
JP2009543353A (ja) 2009-12-03
WO2008002879A3 (en) 2008-08-07
KR20090031548A (ko) 2009-03-26

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Representative=s name: MUELLER-BORE & PARTNER PATENTANWAELTE PARTG MB, DE

Representative=s name: MUELLER-BORE & PARTNER PATENTANWAELTE, EUROPEA, DE

R005 Application deemed withdrawn due to failure to request examination
R005 Application deemed withdrawn due to failure to request examination

Effective date: 20140626