DE102014221620B4 - Halbleitervorrichtung - Google Patents
Halbleitervorrichtung Download PDFInfo
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- DE102014221620B4 DE102014221620B4 DE102014221620.6A DE102014221620A DE102014221620B4 DE 102014221620 B4 DE102014221620 B4 DE 102014221620B4 DE 102014221620 A DE102014221620 A DE 102014221620A DE 102014221620 B4 DE102014221620 B4 DE 102014221620B4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
- H01L2224/05564—Only on the bonding interface of the bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29022—Disposition the layer connector being at least partially embedded in the surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Applications Claiming Priority (2)
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|---|---|---|---|
| JP2013247862A JP6277693B2 (ja) | 2013-11-29 | 2013-11-29 | 半導体装置 |
| JP2013-247862 | 2013-11-29 |
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| DE102014221620A1 DE102014221620A1 (de) | 2015-06-03 |
| DE102014221620B4 true DE102014221620B4 (de) | 2018-08-02 |
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| JP (1) | JP6277693B2 (enExample) |
| KR (1) | KR101596232B1 (enExample) |
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| CN107980171B (zh) * | 2016-12-23 | 2022-06-24 | 苏州能讯高能半导体有限公司 | 半导体芯片、半导体晶圆及半导体晶圆的制造方法 |
| JP6863574B2 (ja) * | 2017-02-22 | 2021-04-21 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
| JP2019145546A (ja) * | 2018-02-16 | 2019-08-29 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
| US10967463B2 (en) * | 2018-04-11 | 2021-04-06 | The University Of Toledo | Sn whisker growth mitigation using NiO sublayers |
| CN113228256B (zh) * | 2018-12-27 | 2024-03-22 | 株式会社大真空 | 压电振动器件 |
| CN109920757B (zh) * | 2019-01-31 | 2020-08-25 | 厦门市三安集成电路有限公司 | 一种提高化合物半导体器件可靠性能的背段工艺 |
| US10861792B2 (en) * | 2019-03-25 | 2020-12-08 | Raytheon Company | Patterned wafer solder diffusion barrier |
| CN113809030B (zh) * | 2021-11-16 | 2022-03-15 | 深圳市时代速信科技有限公司 | 半导体器件和半导体器件的制备方法 |
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| JPH0766384A (ja) | 1993-08-23 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| US5483092A (en) | 1993-06-24 | 1996-01-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a via-hole with a void area for reduced cracking |
| DE19811042A1 (de) | 1997-04-24 | 1998-10-29 | Mitsubishi Electric Corp | Halbleiterbauelement, Verfahren zu seiner Herstellung und dafür verwendetes Ätzmittel |
| JP2007095853A (ja) | 2005-09-27 | 2007-04-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US20100164122A1 (en) | 2008-12-26 | 2010-07-01 | Canon Kabushiki Kaisha | Method of forming conductive layer and semiconductor device |
| DE102009044086A1 (de) | 2009-09-23 | 2011-03-24 | United Monolithic Semiconductors Gmbh | Verfahren zur Herstellung eines elektronischen Bauteils und nach diesem Verfahren hergestelltes elektronisches Bauteil |
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| JPS63127550A (ja) * | 1986-11-17 | 1988-05-31 | Nec Corp | 半導体装置の製造方法 |
| US4827610A (en) * | 1987-08-31 | 1989-05-09 | Texas Instruments Incorporated | Method of creating solder or brazing barriers |
| JPH07193214A (ja) * | 1993-12-27 | 1995-07-28 | Mitsubishi Electric Corp | バイアホール及びその形成方法 |
| US6541301B1 (en) * | 1999-02-12 | 2003-04-01 | Brook David Raymond | Low RF loss direct die attach process and apparatus |
| JP2003045877A (ja) * | 2001-08-01 | 2003-02-14 | Sharp Corp | 半導体装置およびその製造方法 |
| US6764810B2 (en) * | 2002-04-25 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for dual-damascene formation using a via plug |
| US20030203210A1 (en) * | 2002-04-30 | 2003-10-30 | Vitex Systems, Inc. | Barrier coatings and methods of making same |
| JP5162909B2 (ja) * | 2006-04-03 | 2013-03-13 | 豊田合成株式会社 | 半導体発光素子 |
| CN102237339B (zh) * | 2010-04-28 | 2013-07-03 | 中国科学院微电子研究所 | 一种芯片背面金属起镀层结构及其制备方法 |
| KR101781620B1 (ko) * | 2010-09-01 | 2017-09-25 | 삼성전자주식회사 | 모오스 트랜지스터의 제조방법 |
| TWI497602B (zh) * | 2011-02-15 | 2015-08-21 | Tzu Hsiung Chen | 溝渠式蕭基二極體及其製作方法 |
| US20120273948A1 (en) * | 2011-04-27 | 2012-11-01 | Nanya Technology Corporation | Integrated circuit structure including a copper-aluminum interconnect and method for fabricating the same |
| JP2013128062A (ja) * | 2011-12-19 | 2013-06-27 | Elpida Memory Inc | 半導体装置の製造方法 |
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- 2014-08-22 US US14/465,884 patent/US9355937B2/en active Active
- 2014-10-24 DE DE102014221620.6A patent/DE102014221620B4/de active Active
- 2014-11-24 KR KR1020140164164A patent/KR101596232B1/ko active Active
- 2014-11-28 CN CN201410709725.8A patent/CN104681541B/zh active Active
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| US5378926A (en) | 1991-09-30 | 1995-01-03 | Hughes Aircraft Company | Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal nitride barrier layer to block migration of tin through via holes |
| US5483092A (en) | 1993-06-24 | 1996-01-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a via-hole with a void area for reduced cracking |
| JPH0766384A (ja) | 1993-08-23 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| DE19811042A1 (de) | 1997-04-24 | 1998-10-29 | Mitsubishi Electric Corp | Halbleiterbauelement, Verfahren zu seiner Herstellung und dafür verwendetes Ätzmittel |
| JPH10303198A (ja) | 1997-04-24 | 1998-11-13 | Mitsubishi Electric Corp | 半導体装置及びその製造方法とエッチャント |
| JP2007095853A (ja) | 2005-09-27 | 2007-04-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US20100164122A1 (en) | 2008-12-26 | 2010-07-01 | Canon Kabushiki Kaisha | Method of forming conductive layer and semiconductor device |
| DE102009044086A1 (de) | 2009-09-23 | 2011-03-24 | United Monolithic Semiconductors Gmbh | Verfahren zur Herstellung eines elektronischen Bauteils und nach diesem Verfahren hergestelltes elektronisches Bauteil |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102014221620A1 (de) | 2015-06-03 |
| KR101596232B1 (ko) | 2016-02-22 |
| CN104681541B (zh) | 2018-06-29 |
| US20150155224A1 (en) | 2015-06-04 |
| KR20150062963A (ko) | 2015-06-08 |
| JP2015106638A (ja) | 2015-06-08 |
| CN104681541A (zh) | 2015-06-03 |
| JP6277693B2 (ja) | 2018-02-14 |
| US9355937B2 (en) | 2016-05-31 |
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