CN104681541A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN104681541A
CN104681541A CN201410709725.8A CN201410709725A CN104681541A CN 104681541 A CN104681541 A CN 104681541A CN 201410709725 A CN201410709725 A CN 201410709725A CN 104681541 A CN104681541 A CN 104681541A
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Prior art keywords
layer
metal layer
barrier metal
semiconductor device
opening
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CN201410709725.8A
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CN104681541B (zh
Inventor
小山英寿
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明提供一种半导体装置，其能够抑制在通路孔内产生空隙。半导体装置(100)具备半导体衬底(12)。半导体衬底具备表面(12a)和背面(12b)，在表面设置有晶体管(26)的源极电极(20)、栅极电极(22)及漏极电极(24)。源极电极具有上表面(20a)及下表面(20b)。到达下表面(20b)的开口设置于背面(12b)。Au层(14)覆盖开口的侧面及底面。Ni层(16)设置为在开口内覆盖Au层(14)。Au层(19)由与Ni层的材料相比对焊料的密接性更高的材料形成，以在开口内覆盖Ni层的至少一部分的方式层叠于Ni层。焊料层(32)设置为填埋开口内部，与Ni层的一部分及Au层(19)接触。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
当前，例如日本特开平10-303198号公报中公开所示，已知一种半导体装置，其具备通路孔(Via Hole)，该通路孔从背面侧贯穿半导体衬底而到达表面的电极焊盘，在该通路孔内设置焊料。该公报所涉及的半导体装置构成为，在半导体衬底的表面设置半导体元件的电极，到达电极下表面的开口设置于半导体衬底的背面。在该开口内依次层叠Au膜和Ni膜后，利用AuSn焊料将半导体衬底和封装件基板粘接。
专利文献1：日本特开平10-303198号公报
专利文献2：日本特开平7-066384号公报
专利文献3：日本特开2007-095853号公报
镍具有排斥焊料的性质。因此，在上述现有技术所涉及的半导体装置中，由于Ni膜和焊料之间的密接性下降，所以可能在焊料内产生残留有空气的区域。焊料内残留有空气的区域也称为空隙(void)。
通路孔内的焊料还具有使在半导体元件动作时产生的热扩散的作用。如果在焊料内存在空隙，则会妨碍上述热扩散。其结果，无法进行经由焊料的散热，热量在半导体元件中蓄积，使半导体元件的特性下降。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于，提供一种能够抑制在通路孔内设置有焊料时的空隙的产生的半导体装置。
本发明所涉及的半导体装置的特征在于，
具备：
半导体衬底，其具备表面和背面，在所述表面设置半导体元件以及所述半导体元件的电极，到达所述电极下表面的开口设置于所述背面；
第1金属层，其覆盖所述开口的侧面以及底面；
阻挡金属层，其设置为在所述开口内覆盖所述第1金属层；以及
第2金属层，其由与所述阻挡金属层的材料相比，对焊料的密接性更高的材料形成，该第2金属层以在所述开口内将所述阻挡金属层的至少一部分覆盖的方式，层叠于所述阻挡金属层。
发明的效果
根据本发明，通过在通路孔内在阻挡金属层表面设置第2金属层，从而在防止第1金属层和焊料之间的反应的同时，提高焊料的密接性，因此，能够抑制在通路孔内设置有焊料时的空隙的产生。
附图说明
图1是表示本发明的实施方式所涉及的半导体装置的剖面图。
图2是表示本发明的实施方式所涉及的半导体装置的制造工序的剖面图。
图3是表示本发明的实施方式所涉及的半导体装置的制造工序的剖面图。
图4是表示本发明的实施方式所涉及的半导体装置的制造工序的剖面图。
图5是表示本发明的实施方式所涉及的半导体装置的制造工序的剖面图。
图6是表示本发明的实施方式的变形例所涉及的半导体装置的剖面图。
图7是表示本发明的实施方式的变形例所涉及的半导体装置的剖面图。
图8是表示本发明的实施方式的变形例所涉及的半导体装置的剖面图。
图9是表示本发明的实施方式的变形例所涉及的半导体装置的剖面图。
图10是表示本发明的实施方式的变形例所涉及的半导体装置的剖面图。
图11是表示与实施方式相对的对比例所涉及的半导体装置的剖面图。
图12是表示与实施方式相对的对比例所涉及的半导体装置的剖面图。
标号的说明
12半导体衬底，12a表面，12b背面，12c侧面，12d开口，14、18、19、38Au层，16Ni层，16a露出部，20源极电极，20a上表面，20b下表面，22栅极电极，24漏极电极，26晶体管，30、40通路孔，32焊料层，42氧化Ni层，42a露出部，50阻挡金属层，50a露出部，100、111、112、113、114、115半导体装置，132空隙。
具体实施方式
图1是表示本发明的实施方式所涉及的半导体装置100的剖面图。图2～5是表示本发明的实施方式所涉及的半导体装置的制造工序的剖面图。半导体装置100具备：半导体衬底12，其形成有晶体管26；通路孔30；Au层18，其设置于半导体衬底12的背面12b；以及焊料层32，其填埋通路孔30内部。
通路孔30在半导体衬底12的开口12d内设置有Au层14、Ni层16以及Au层19。Ni层16是如后述所示用于对焊料和Au层14之间的AuSn反应进行阻挡的阻挡金属层。
实施方式所涉及的半导体装置100中设置的半导体元件是晶体管26。晶体管26是场效应晶体管(FET)，在半导体衬底12的表面12a按顺序排列地设置栅极、源极、漏极，分别在源极的上方设置有源极电极20，在栅极的上方设置有栅极电极22，在漏极的上方设置有漏极电极24。此外，本发明并不限定于FET，能够应用于形成在半导体衬底的公知的半导体元件。
半导体衬底12具备表面12a和背面12b。在表面12a设置有晶体管26的源极电极20、栅极电极22以及漏极电极24。源极电极20具有上表面20a以及下表面20b。到达下表面20b的开口12d设置于背面12b。Au层14覆盖开口12d的侧面12c以及底面即下表面20b。
Ni层16设置为在开口12d内将Au层14全部覆盖。Ni层16具有排斥焊料的性质，对焊料作为阻挡金属起作用。即使在Au层18、19和焊料层32之间发生AuSn反应，由于Ni层16作为阻挡金属起作用，因此使AuSn反应停止。因此，能够防止焊料爬升至晶体管26的源极电极20。
在本实施方式中，Ni层16设置于从开口12d的内部至背面12b的开口12d的缘部，但不设置于开口12d的缘部的外侧。在半导体衬底12中，通过在凹凸更少的背面12b局部地设置Ni层16，而不是在设置有晶体管26的表面12a进行设置，从而在平滑的面上设置较少量的Ni层而减少应力。由于这样对设置Ni层16的位置以及范围进行改进，所以能够抑制Ni层16的剥落。
Au层19在开口12d内以将Ni层16的一部分覆盖的方式层叠于Ni层16上。Au与Ni相比，对焊料的密接性高。在本实施方式中，Au层19将Ni层16中的与开口12d的底面重叠的部分覆盖，使Ni层16中的与侧面12c重叠的部分露出。其结果，Ni层16具有露出部16a。该露出部16a构成通路孔30的侧面。此外，并不是必须使Ni层16中的与侧面12c重叠的部分全部露出，也可以仅使Ni层16中的与侧面12c重叠的部分的一部分露出。
焊料层32设置为填埋开口12d内部，与Ni层16的一部分以及Au层19抵接。该焊料层32是下述焊料，即，当将形成了半导体装置100的半导体衬底12在后续处理中切割而进行半导体芯片化后，将该半导体芯片向封装件基板(未图示)等进行芯片接合时夹在它们之间的焊料。由于存在Au层19而确保了通路孔30内的焊料的密接性，因此，使焊料填充至通路孔30内的各个角落，抑制了空隙的产生。
另外，在比Au层19低1层的位置处存在Ni层16，并且，在通路孔30内Ni层16具备露出部16a。Ni层16相对于焊料成为阻挡金属，能够防止焊料爬升至晶体管26的源极电极20。
如以上说明所示，通路孔30内在Ni层16的表面局部地设置Au层19，在防止Au层14和焊料之间的反应的同时，提高焊料的密接性，因此，能够抑制在通路孔30内产生空隙。
〔实施方式所涉及的制造方法〕
以下，作为利用图2～图5进行说明的制造工艺中使用的金属形成方法，只要适当地利用电解镀、无电解镀、蒸镀、以及喷镀等公知的金属层叠技术即可。
首先，在半导体衬底12的表面12a，形成未图示的源极、漏极、栅极，进而在它们上方设置源极电极20、漏极电极24、栅极电极22，形成晶体管26。然后，为了在源极电极20的正下方形成通路孔30，从背面12b侧对半导体衬底12进行蚀刻。由此，在半导体衬底12形成开口12d。其结果，得到图2的构造。
在形成开口12d之后，在背面12b侧，以将包含开口12d在内的背面12b整体覆盖的方式，形成Au层14。其结果，得到图3的构造。Au层14将开口12d的侧面12c以及开口12d的底面即源极电极20的下表面20b覆盖。此外，也可以取代Au层14，而在与Au层14相同的位置上层叠Ti/Au层、或者Ti/Pt/Au层。
然后，将Ni层16在背面12b侧层叠于Au层14的上方。具体而言，在包含开口12d在内的背面12b的整体层叠Ni之后，进行图案化，以使得Ni仅残留在开口12d内以及该开口12d的缘周边部。通过蚀刻将除了该缘周缘部以外的Ni去除。由此，形成Ni层16。其结果，得到图4的构造。
然后，形成Au层18、19。Au层18形成为在背面12b的整个面处于最表面侧。Au层19局部地设置于开口12d的底面侧。Au层19覆盖Ni层16中的开口12d的底面侧部分，但不覆盖Ni层16中的与开口12d的侧面12c重叠的部分。其结果，得到图5的构造。通过使用各向异性较强的喷镀或者蒸镀装置等，在与开口12d的底面垂直的方向上层叠Au，从而能够在侧面12c侧不形成Au层，在开口12d的底面侧局部地设置Au层19。此外，也可以取代Au层18、19，在与Au层18、19相同的位置层叠例如Ti/Au层或者Ti/Pt/Au层。
然后，进行使用了焊料的芯片接合。关于作为芯片接合目标的封装件基板等，省略了图示。通过以填埋通路孔30的方式在背面12b整体设置焊料，从而形成焊料层32。其结果，得到图1的构造。
〔对比例的说明〕
图11及图12是表示与实施方式相对的对比例所涉及的半导体装置200的剖面图。图11是对比例所涉及的半导体装置200的剖面图，与实施方式所涉及的半导体装置100的区别在于不具备Au层18、19。图12示出利用焊料对形成半导体装置200后的半导体衬底12进行芯片接合的情况下，由于Ni层16和焊料的密接性较差而在焊料层32内的Ni层16周边产生了空隙132的状态。
作为用于进行晶体管的源极接地的电连接方法，存在对源极电极进行接线的方法、以及以与源极电极连接的方式形成通路孔的方法。在对源极电极形成通路孔30的情况下，作为设置于通路孔30的内表面的金属，通常使用Au。
如果焊料和Au层(通路孔30内以及源极电极部分)接触，则引起AuSn反应。在芯片接合时，如果在通路孔30内Au层14与焊料接触，则产生AuSn反应。存在由于该AuSn反应，焊料爬升至源极电极表面的问题。该焊料的爬升，使AuSn反应扩散至晶体管区域，使晶体管26无法正常地动作。
对比例所涉及的半导体装置200中，作为该爬升的对策，在通路孔30内形成有能够阻挡与焊料的反应的Ni层16。利用Ni层16，能够防止焊料的爬升。
但是，另一方面，由于Ni层16与焊料的密接性较差，因此具有在焊料内产生残留有空气的区域的问题。在焊料内残留有空气的该区域也被称为空隙。空隙132妨碍在晶体管26动作时所产生的热量的扩散，其结果，使晶体管26的特性下降。另外，还可以想到：由于存在空隙132，焊料和半导体衬底12侧的密接性降低，诱发剥落。
对于这一点，根据实施方式所涉及的半导体装置100，在通路孔30内，在Ni层16的表面12a侧部分局部地设置有Au层19。在利用Ni层16防止Au层14和焊料之间的反应的同时，利用通路孔30内的Au层19提高焊料的密接性，因此能够抑制在通路孔30内产生空隙这样情况。
此外，在实施方式中，Au层19仅局部地设置于源极电极20的下表面20b的上方(即，通路孔30的底面的上方)，其中，源极电极20的下表面20b构成开口12d的底面。此外，这里所指的“下表面20b的上方”不是指图1的纸面上方，而是指下表面20b的法线方向。另一方面，由于在通路孔30的侧面(即，开口12d的侧面12c)没有设置Au层19，因此Ni层16露出。但是，本发明并不限定于此。也可以在通路孔30内的至少一部分设置Au层，其位置不必限定于开口12d的底面侧。
图6是表示本发明的实施方式的变形例所涉及的半导体装置111的剖面图。半导体装置111除了具备通路孔40这一点以外，与半导体装置100相同。通路孔40具备以在开口12d内将Ni层16的全部覆盖的方式设置的Au层38。Au层38将源极电极20的下表面20b的上方(即，通路孔40的底面的上方)、和通路孔40的侧面(即，开口12d的侧面12c)二者一起覆盖，其中，源极电极20的下表面20b构成开口12d的底面。通过上述方式，能够消除Ni层16和焊料层32接触的部分，能够使焊料填充至通路孔40内各个角落，能够抑制空隙。
此外，作为阻挡金属层设置有Ni层16，但本发明并不限定于此。也可以取代Ni层16，在与Ni层16相同的位置，设置由从由铂(Pt)、铅(Pb)、钛(Ti)以及钴(Co)构成的组中选择出的1种材料形成的阻挡金属层。其原因在于，这些材料与镍相同地，与焊料的反应性较低。
图7是表示本发明的实施方式的变形例所涉及的半导体装置112的剖面图。半导体装置112除了将Ni层16置换为氧化Ni层42这一点以外，与半导体装置100相同。即，在半导体装置112中，Au层19覆盖氧化Ni层42中的与底面重叠的部分，不覆盖氧化Ni层42中的与侧面重叠的部分。其结果，氧化Ni层42具有露出部42a。该露出部42a构成半导体装置112中的通路孔30的侧面。
通常，与Au层相比，Ni层的金属应力较高。如果为了提高阻挡性而使Ni层16变厚，则Ni层16容易从半导体衬底12剥落。如果为了抑制该剥落而单纯地使Ni层16变薄，则作为阻挡金属层的效果变得不充分。由于虽然Ni层16和焊料反应速度与Au层和焊料的反应相比非常慢，但依然能够发生反应，因此，不能够单纯地使Ni层16变薄。
与镍相比，氧化镍具有较强地排斥焊料的性质。因此，氧化Ni层42与Ni层16相比，能够使膜厚变薄。
因此，在半导体装置112中，将由阻挡性更高的氧化镍形成的氧化Ni层42作为阻挡金属层使用。氧化Ni层42与Ni层16相比能够较强地排斥焊料，因此即便使阻挡金属层的层厚变薄，也能够充分得到阻挡Au层14与焊料反应的效果。由此，能够在确保阻挡金属的同时，使氧化Ni层42变薄，并能够抑制剥落的问题。
作为半导体装置112的制造工艺，在与实施方式1所涉及的Ni层16同样地形成Ni层之后，使该Ni层氧化，形成氧化镍(NiOx)。然后，与实施方式1相同地对Au层18、19进行层叠。
此外，也可以取代氧化Ni层42，设置从由铂(Pt)、铅(Pb)、钛(Ti)、以及钴(Co)构成的组中选择出的1种材料的氧化物层。
图8是表示本发明的实施方式的变形例所涉及的半导体装置113的剖面图。半导体装置113是在图6所示的半导体装置111中，将Ni层16置换为氧化Ni层42的结构。
图9是表示本发明的实施方式的变形例所涉及的半导体装置114的剖面图。半导体装置114除了将Ni层16置换为阻挡金属层50这一点以外，与半导体装置100相同。阻挡金属层50具有多层膜构造，该多层膜构造是通过使Ni层、和由除了镍以外的后述材料构成的中间层至少大于或等于1次地彼此重叠地层叠而形成的。在阻挡金属层50中，Ni层比中间层厚。
阻挡金属层50形成为，Ni层/中间层/Ni层/中间层/···多次彼此重叠地层叠，形成Ni层和中间层的多层构造。中间层的材料是与镍相比层内的应力较低的材料，具体而言，可以利用从由钛(Ti)、金(Au)、铂(Pt)、铝(Al)、铌(Nb)、铅(Pb)以及铜(Cu)构成的组中选择出的1种材料。
通过形成为多层构造，从而使每个Ni层变薄，并且，在Ni层之间，插入由与镍相比应力较低的金属构成的中间层。由此，即使在阻挡金属层50和实施方式1的Ni层16之间在以Ni层来看待的情况下的最终的总厚度相同，阻挡金属层50与Ni层16相比，也能够使内部的应力降低。
例如，设想在半导体装置100中将Ni层16形成为单层100nm的情况。与此相对，在半导体装置114中，以Ni层/中间层/Ni层/中间层/Ni层/中间层/Ni层/中间层/Ni层的方式，Ni层为5层、中间层为4层，Ni层平均每层为20nm，中间层平均每层为10nm。阻挡金属层50是Ni层平均每层为20nm的结构，但由于合计有5层，因此作为总厚度，与Ni层16相同地具有100nm的厚度的Ni层。如上述所示，优选在充分确保Ni层的厚度且对焊料的阻挡性相同的同时，降低内部的应力。
此外，在半导体装置114中，Au层19也覆盖阻挡金属层50中的与开口12d的底面重叠的部分，不覆盖阻挡金属层50中的与侧面12c重叠的部分。其结果，阻挡金属层50具有露出部50a。该露出部50a构成通路孔30的侧面。
图10是表示本发明的实施方式的变形例所涉及的半导体装置115的剖面图。半导体装置115除了将Ni层16置换为阻挡金属层50这一点以外，与半导体装置111相同。
此外，在图6～图10中，为了便于说明，省略了焊料层32的图示，但实际上，半导体装置111～115也与半导体装置100相同地具有焊料层32。

Claims (12)

1.一种半导体装置，其特征在于，具备：
半导体衬底，其具备表面和背面，在所述表面设置半导体元件以及所述半导体元件的电极，到达所述电极下表面的开口设置于所述背面；
第1金属层，其覆盖所述开口的侧面以及底面；
阻挡金属层，其设置为在所述开口内覆盖所述第1金属层；以及
第2金属层，其由与所述阻挡金属层的材料相比，对焊料的密接性更高的材料形成，该第2金属层以在所述开口内将所述阻挡金属层的至少一部分覆盖的方式，层叠于所述阻挡金属层。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第2金属层在所述开口内覆盖所述阻挡金属层的一部分但不覆盖其余部分。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第2金属层覆盖所述阻挡金属层中的与所述底面重叠的部分，使所述阻挡金属层中的与所述侧面重叠的部分的至少一部分露出。
4.根据权利要求1所述的半导体装置，其特征在于，
所述第2金属层在所述开口内覆盖所述阻挡金属层的全部。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述阻挡金属层由从由镍、铂、铅、钛以及钴构成的组中选择出的1种材料形成。
6.根据权利要求1或2所述的半导体装置，其特征在于，
所述阻挡金属层由从由镍、铂、铅、钛以及钴构成的组中选择出的1种材料的氧化物形成。
7.根据权利要求1或2所述的半导体装置，其特征在于，
所述阻挡金属层是将第1阻挡金属层和第2阻挡金属层至少大于或等于1次地彼此重叠地层叠而得到的，其中，该第2阻挡金属层由与所述第1阻挡金属层的材料相比，层内的应力更低的材料构成。
8.根据权利要求7所述的半导体装置，其特征在于，
所述第1阻挡金属层由镍形成，
所述第2阻挡金属层由从由铂、铅、钛、金、铝、铌以及铜构成的组中选择出的1种材料形成。
9.根据权利要求7所述的半导体装置，其特征在于，
所述第1阻挡金属层比所述第2阻挡金属层厚。
10.根据权利要求1或2所述的半导体装置，其特征在于，
所述阻挡金属层设置在从所述开口的内部直至所述背面的所述开口的缘部为止，不设置于所述缘部的外侧。
11.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体元件为晶体管，在所述表面按顺序排列地设置栅极、源极、漏极，
所述电极是设置于所述源极的上方的源极电极。
12.根据权利要求1或2所述的半导体装置，其特征在于，
所述第1金属层以及所述第2金属层包含金，所述阻挡金属层包含镍。
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