DE102011122918B3 - Halbleitervorrichtung - Google Patents
Halbleitervorrichtung Download PDFInfo
- Publication number
- DE102011122918B3 DE102011122918B3 DE102011122918.7A DE102011122918A DE102011122918B3 DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3 DE 102011122918 A DE102011122918 A DE 102011122918A DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3
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- Germany
- Prior art keywords
- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01005—Boron [B]
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- H01L2924/01006—Carbon [C]
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- H01L2924/01079—Gold [Au]
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- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dicing (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-170570 | 2010-07-29 | ||
| JP2010170570A JP5521862B2 (ja) | 2010-07-29 | 2010-07-29 | 半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102011122918B3 true DE102011122918B3 (de) | 2016-05-19 |
Family
ID=45525895
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102011079105A Withdrawn DE102011079105A1 (de) | 2010-07-29 | 2011-07-13 | Halbleitervorrichtung und Verfahren zum Herstellen derselben |
| DE102011122918.7A Expired - Fee Related DE102011122918B3 (de) | 2010-07-29 | 2011-07-13 | Halbleitervorrichtung |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102011079105A Withdrawn DE102011079105A1 (de) | 2010-07-29 | 2011-07-13 | Halbleitervorrichtung und Verfahren zum Herstellen derselben |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8728866B2 (enExample) |
| JP (1) | JP5521862B2 (enExample) |
| CN (1) | CN102347243B (enExample) |
| DE (2) | DE102011079105A1 (enExample) |
| TW (1) | TWI446429B (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227116B (zh) * | 2013-03-29 | 2016-01-20 | 日月光半导体制造股份有限公司 | 透光壳体及其制造方法与应用其的光学组件 |
| JP2015115446A (ja) * | 2013-12-11 | 2015-06-22 | 株式会社東芝 | 半導体装置の製造方法 |
| JP6221736B2 (ja) * | 2013-12-25 | 2017-11-01 | 三菱電機株式会社 | 半導体装置 |
| JP6215755B2 (ja) * | 2014-04-14 | 2017-10-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| TWI566288B (zh) * | 2014-07-14 | 2017-01-11 | 矽品精密工業股份有限公司 | 切割用載具及切割方法 |
| JP6314731B2 (ja) | 2014-08-01 | 2018-04-25 | 株式会社ソシオネクスト | 半導体装置及び半導体装置の製造方法 |
| JP6511141B2 (ja) * | 2015-07-28 | 2019-05-15 | 日本電信電話株式会社 | 光スイッチ |
| US10224294B2 (en) | 2015-08-18 | 2019-03-05 | Mitsubishi Electric Corporation | Semiconductor device |
| US10393532B2 (en) * | 2015-10-20 | 2019-08-27 | International Business Machines Corporation | Emergency responsive navigation |
| US10825694B2 (en) * | 2017-02-02 | 2020-11-03 | Hitachi Chemical Company, Ltd. | Method for manufacturing electronic component, resin composition for temporary protection, and resin film for temporary protection |
| JP2019192729A (ja) * | 2018-04-23 | 2019-10-31 | 株式会社村田製作所 | 半導体装置 |
| DE112018007677B4 (de) * | 2018-05-28 | 2023-10-12 | Mitsubishi Electric Corporation | Verfahren zur Herstellung eines Halbleitergerätes |
| JP7034105B2 (ja) | 2019-01-18 | 2022-03-11 | 三菱電機株式会社 | 電力用半導体装置の製造方法、電力用半導体装置および電力変換装置 |
| KR102785840B1 (ko) | 2019-12-13 | 2025-03-26 | 삼성전자주식회사 | 반도체 패키지 |
| US11948893B2 (en) | 2021-12-21 | 2024-04-02 | Qorvo Us, Inc. | Electronic component with lid to manage radiation feedback |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080081398A1 (en) * | 2006-10-02 | 2008-04-03 | Fionix Inc. | Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0544329A3 (en) | 1991-11-28 | 1993-09-01 | Kabushiki Kaisha Toshiba | Semiconductor package |
| JP2501279B2 (ja) | 1991-11-29 | 1996-05-29 | 株式会社東芝 | 半導体パッケ―ジ |
| JP2001024079A (ja) | 1999-07-05 | 2001-01-26 | Seiko Epson Corp | 電子部品の封止構造 |
| US7026223B2 (en) | 2002-03-28 | 2006-04-11 | M/A-Com, Inc | Hermetic electric component package |
| JP4342174B2 (ja) | 2002-12-27 | 2009-10-14 | 新光電気工業株式会社 | 電子デバイス及びその製造方法 |
| JP2005057136A (ja) | 2003-08-06 | 2005-03-03 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JP4312631B2 (ja) | 2004-03-03 | 2009-08-12 | 三菱電機株式会社 | ウエハレベルパッケージ構造体とその製造方法、及びそのウエハレベルパッケージ構造体から分割された素子 |
| JP4993848B2 (ja) * | 2004-05-28 | 2012-08-08 | 三洋電機株式会社 | 配線基材 |
| KR100594716B1 (ko) | 2004-07-27 | 2006-06-30 | 삼성전자주식회사 | 공동부를 구비한 캡 웨이퍼, 이를 이용한 반도체 칩, 및그 제조방법 |
| FR2879889B1 (fr) | 2004-12-20 | 2007-01-26 | United Monolithic Semiconduct | Boitier miniature hyperfrequence et procede de fabrication du boitier |
| US20080150118A1 (en) * | 2005-03-02 | 2008-06-26 | Koninklijke Philips Electronics, N.V. | Method of Manufacturing a Semiconductor Packages and Packages Made |
| US7495462B2 (en) | 2005-03-24 | 2009-02-24 | Memsic, Inc. | Method of wafer-level packaging using low-aspect ratio through-wafer holes |
| JP2007005948A (ja) * | 2005-06-22 | 2007-01-11 | Alps Electric Co Ltd | 電子部品及びその製造方法 |
| US20070004079A1 (en) | 2005-06-30 | 2007-01-04 | Geefay Frank S | Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of FBAR chips |
| JP2007019107A (ja) * | 2005-07-05 | 2007-01-25 | Shinko Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
| KR100752713B1 (ko) * | 2005-10-10 | 2007-08-29 | 삼성전기주식회사 | 이미지센서의 웨이퍼 레벨 칩 스케일 패키지 및 그제조방법 |
| US7393758B2 (en) * | 2005-11-03 | 2008-07-01 | Maxim Integrated Products, Inc. | Wafer level packaging process |
| JP4860552B2 (ja) | 2007-06-08 | 2012-01-25 | 日本オプネクスト株式会社 | 半導体装置 |
| JP5344336B2 (ja) * | 2008-02-27 | 2013-11-20 | 株式会社ザイキューブ | 半導体装置 |
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2010
- 2010-07-29 JP JP2010170570A patent/JP5521862B2/ja not_active Expired - Fee Related
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2011
- 2011-04-04 US US13/079,055 patent/US8728866B2/en active Active
- 2011-04-06 TW TW100111754A patent/TWI446429B/zh not_active IP Right Cessation
- 2011-07-13 DE DE102011079105A patent/DE102011079105A1/de not_active Withdrawn
- 2011-07-13 DE DE102011122918.7A patent/DE102011122918B3/de not_active Expired - Fee Related
- 2011-07-28 CN CN201110213254.8A patent/CN102347243B/zh not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080081398A1 (en) * | 2006-10-02 | 2008-04-03 | Fionix Inc. | Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102347243A (zh) | 2012-02-08 |
| CN102347243B (zh) | 2014-08-20 |
| JP2012033615A (ja) | 2012-02-16 |
| US8728866B2 (en) | 2014-05-20 |
| TWI446429B (zh) | 2014-07-21 |
| TW201205656A (en) | 2012-02-01 |
| US20120025366A1 (en) | 2012-02-02 |
| DE102011079105A1 (de) | 2012-04-12 |
| JP5521862B2 (ja) | 2014-06-18 |
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