DE102006058795B4 - Verfahren zum Ausbilden einer Resiststruktur und Herstellungsverfahren für eine Halbleiter-Vorrichtung - Google Patents

Verfahren zum Ausbilden einer Resiststruktur und Herstellungsverfahren für eine Halbleiter-Vorrichtung Download PDF

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Publication number
DE102006058795B4
DE102006058795B4 DE200610058795 DE102006058795A DE102006058795B4 DE 102006058795 B4 DE102006058795 B4 DE 102006058795B4 DE 200610058795 DE200610058795 DE 200610058795 DE 102006058795 A DE102006058795 A DE 102006058795A DE 102006058795 B4 DE102006058795 B4 DE 102006058795B4
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Prior art keywords
resist pattern
group
resist
forming
thickened
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Expired - Fee Related
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DE200610058795
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German (de)
English (en)
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DE102006058795A1 (de
Inventor
Miwa Kozawa
Koji Nozaki
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Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
DE200610058795 2006-08-17 2006-12-12 Verfahren zum Ausbilden einer Resiststruktur und Herstellungsverfahren für eine Halbleiter-Vorrichtung Expired - Fee Related DE102006058795B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006222498A JP4724073B2 (ja) 2006-08-17 2006-08-17 レジストパターンの形成方法、半導体装置及びその製造方法
JP2006-222498 2006-08-17

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DE102006058795A1 DE102006058795A1 (de) 2008-02-28
DE102006058795B4 true DE102006058795B4 (de) 2012-12-20

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US (2) US8119325B2 (US08119325-20120221-C00001.png)
JP (1) JP4724073B2 (US08119325-20120221-C00001.png)
KR (1) KR100845486B1 (US08119325-20120221-C00001.png)
CN (1) CN101226335B (US08119325-20120221-C00001.png)
DE (1) DE102006058795B4 (US08119325-20120221-C00001.png)
TW (1) TWI358748B (US08119325-20120221-C00001.png)

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JP5018307B2 (ja) * 2006-09-26 2012-09-05 富士通株式会社 レジストパターン厚肉化材料、レジストパターンの形成方法、半導体装置及びその製造方法
WO2009110166A1 (ja) * 2008-03-06 2009-09-11 パナソニック株式会社 レジスト材料及びそれを用いたパターン形成方法
JP5321415B2 (ja) * 2009-11-04 2013-10-23 富士通株式会社 レジストパターン厚肉化材料、並びに、半導体装置及びその製造方法
US20130189495A1 (en) * 2010-11-12 2013-07-25 The Regents Of The University Of Michigan Nanoscale Photolithography
JP6075724B2 (ja) * 2012-10-01 2017-02-08 アーゼッド・エレクトロニック・マテリアルズ（ルクセンブルグ）ソシエテ・ア・レスポンサビリテ・リミテ 微細レジストパターン形成用組成物およびそれを用いたパターン形成方法
CN103871846B (zh) * 2012-12-18 2017-06-13 中芯国际集成电路制造(上海)有限公司 自对准多重图形化方法及硅基硬掩模组合物的应用
US10162265B2 (en) * 2015-12-09 2018-12-25 Rohm And Haas Electronic Materials Llc Pattern treatment methods
KR102398664B1 (ko) * 2016-01-26 2022-05-16 삼성전자주식회사 반도체 소자의 제조 방법
JP7065311B2 (ja) * 2017-11-22 2022-05-12 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
CN108490739A (zh) * 2018-03-29 2018-09-04 上海华力集成电路制造有限公司 光刻胶涂布方法

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Also Published As

Publication number Publication date
JP2008046408A (ja) 2008-02-28
DE102006058795A1 (de) 2008-02-28
JP4724073B2 (ja) 2011-07-13
KR20080016406A (ko) 2008-02-21
TW200811918A (en) 2008-03-01
CN101226335A (zh) 2008-07-23
TWI358748B (en) 2012-02-21
US20120098103A1 (en) 2012-04-26
US8945816B2 (en) 2015-02-03
KR100845486B1 (ko) 2008-07-10
CN101226335B (zh) 2012-03-21
US8119325B2 (en) 2012-02-21
US20080044769A1 (en) 2008-02-21

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