DE10196382T1 - Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird - Google Patents

Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird

Info

Publication number
DE10196382T1
DE10196382T1 DE10196382T DE10196382T DE10196382T1 DE 10196382 T1 DE10196382 T1 DE 10196382T1 DE 10196382 T DE10196382 T DE 10196382T DE 10196382 T DE10196382 T DE 10196382T DE 10196382 T1 DE10196382 T1 DE 10196382T1
Authority
DE
Germany
Prior art keywords
semiconductor chip
semiconductor
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10196382T
Other languages
English (en)
Inventor
Yuji Kikuchi
Kiyoharu Kishimoto
Kazunari Nakagawa
Yoshiharu Hino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Hitachi Maxell Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Publication of DE10196382T1 publication Critical patent/DE10196382T1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07756—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being non-galvanic, e.g. capacitive
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07775—Antenna details the antenna being on-chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE10196382T 2000-06-21 2001-06-20 Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird Ceased DE10196382T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000186409 2000-06-21
PCT/JP2001/005282 WO2001099193A1 (en) 2000-06-21 2001-06-20 Semiconductor chip and semiconductor device using the semiconductor chip

Publications (1)

Publication Number Publication Date
DE10196382T1 true DE10196382T1 (de) 2003-12-04

Family

ID=18686575

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196382T Ceased DE10196382T1 (de) 2000-06-21 2001-06-20 Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird

Country Status (6)

Country Link
US (1) US6838773B2 (de)
KR (1) KR100741039B1 (de)
CN (1) CN1275328C (de)
AU (1) AU7457401A (de)
DE (1) DE10196382T1 (de)
WO (1) WO2001099193A1 (de)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7298331B2 (en) * 2000-03-13 2007-11-20 Rcd Technology, Inc. Method for forming radio frequency antenna
US6476775B1 (en) 2000-03-13 2002-11-05 Rcd Technology Corporation Method for forming radio frequency antenna
US7268740B2 (en) * 2000-03-13 2007-09-11 Rcd Technology Inc. Method for forming radio frequency antenna
DE10196382T1 (de) * 2000-06-21 2003-12-04 Hitachi Maxell Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird
JP3616605B2 (ja) * 2002-04-03 2005-02-02 沖電気工業株式会社 半導体装置
US7009576B2 (en) * 2002-06-11 2006-03-07 Michelin Recherche Et Technique S.A. Radio frequency antenna for a tire and method for same
US7456752B2 (en) 2003-05-06 2008-11-25 Rcd Technology, Inc. Radio frequency identification sensor for fluid level
US7629667B2 (en) * 2003-08-28 2009-12-08 Hitachi, Ltd. Semiconductor device including an on-chip coil antenna formed on a device layer which is formed on an oxide film layer
JP2005123591A (ja) * 2003-09-25 2005-05-12 Rohm Co Ltd 半導体装置及びこれを実装した電子機器
US7487373B2 (en) * 2004-01-30 2009-02-03 Semiconductor Energy Laboratory Co., Ltd. Wireless semiconductor device having low power consumption
US7842948B2 (en) * 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
US8030745B2 (en) * 2004-03-04 2011-10-04 Semiconductor Energy Laboratory Co., Ltd. ID chip and IC card
KR101113010B1 (ko) 2004-03-12 2012-03-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 디바이스
CN1947132B (zh) 2004-04-09 2010-10-13 株式会社半导体能源研究所 产品管理系统及方法
WO2006028195A1 (en) * 2004-09-09 2006-03-16 Semiconductor Energy Laboratory Co., Ltd. Wireless chip
US7781758B2 (en) * 2004-10-22 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7380190B2 (en) * 2004-12-15 2008-05-27 Impinj, Inc. RFID tag with bist circuits
US7307528B2 (en) * 2004-12-15 2007-12-11 Impinj, Inc. RFID tag design with circuitry for wafer level testing
WO2006068286A1 (en) * 2004-12-24 2006-06-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI252575B (en) * 2005-01-17 2006-04-01 Phoenix Prec Technology Corp Flip-chip package structure with direct electrical connection of semiconductor chip
US7400255B2 (en) * 2005-02-28 2008-07-15 Impinj, Inc. Wireless functional testing of RFID tag
US7528724B2 (en) * 2005-02-28 2009-05-05 Impinj, Inc. On die RFID tag antenna
JP2006243724A (ja) 2005-03-04 2006-09-14 Samsung Electronics Co Ltd 駆動チップ、表示装置及びその製造方法
US20060205113A1 (en) * 2005-03-14 2006-09-14 Rcd Technology Corp. Radio frequency identification (RFID) tag lamination process
US7456506B2 (en) * 2005-03-14 2008-11-25 Rcd Technology Inc. Radio frequency identification (RFID) tag lamination process using liner
KR100642643B1 (ko) 2005-03-18 2006-11-10 삼성전자주식회사 내부회로의 전원/접지선들과 직접 접속되는 재배치된전원/접지선들을 갖는 반도체 칩들 및 그 제조방법들
WO2006104792A1 (en) * 2005-03-28 2006-10-05 Avery Dennison Corporation Method for making rfid device antennas
US7607586B2 (en) * 2005-03-28 2009-10-27 R828 Llc Semiconductor structure with RF element
JP2006286966A (ja) * 2005-03-31 2006-10-19 Fujitsu Ltd 半導体装置の生産管理方法及び半導体基板
JP2006303344A (ja) * 2005-04-25 2006-11-02 Matsushita Electric Ind Co Ltd パッケージ基板上にｌｓｉチップをフリップして配置した半導体装置、及びその基板配線設計方法
TWI330863B (en) * 2005-05-18 2010-09-21 Megica Corp Semiconductor chip with coil element over passivation layer
US7651932B2 (en) 2005-05-31 2010-01-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing antenna and method for manufacturing semiconductor device
JP4547625B2 (ja) * 2005-07-04 2010-09-22 ソニー株式会社 通信ボード
JP2007067012A (ja) * 2005-08-29 2007-03-15 Matsushita Electric Ind Co Ltd 半導体装置
WO2007043602A1 (en) * 2005-10-14 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and communication system using the semiconductor device
US7388542B2 (en) * 2005-11-10 2008-06-17 Rcd Technology, Inc. Method for an element using two resist layers
US7377447B2 (en) 2005-12-05 2008-05-27 Rcd Technology, Inc. Tuned radio frequency identification (RFID) circuit used as a security device for wristbands and package security
US20080129455A1 (en) * 2006-05-24 2008-06-05 Rcd Technology Inc. Method for forming rfid tags
EP2050130B1 (de) * 2006-07-10 2015-03-04 Nxp B.V. Transponder und verfahren zur herstellung eines transponders
TWI380500B (en) 2007-02-06 2012-12-21 Mutual Pak Technology Co Ltd Integrated circuit device having antenna conductors and the mothod for the same
CN101246849B (zh) * 2007-02-13 2010-05-19 相丰科技股份有限公司 具天线导体的集成电路装置及其制造方法
JP2009212481A (ja) * 2007-04-27 2009-09-17 Sharp Corp 半導体装置及び半導体装置の製造方法
DE102008046761B4 (de) 2007-09-14 2021-08-05 Infineon Technologies Ag Halbleiterbauelement mit leitfähiger Verbindungsanordnung und Verfahren zur Bildung eines Halbleiterbauelements
US7986023B2 (en) * 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
JP2009278030A (ja) * 2008-05-19 2009-11-26 Panasonic Corp 半導体装置及びその製造方法
JP5140565B2 (ja) * 2008-11-28 2013-02-06 三洋電機株式会社 素子搭載用基板、半導体モジュール、および携帯機器
US9011706B2 (en) * 2008-12-16 2015-04-21 City University Of Hong Kong Method of making foraminous microstructures
WO2010113751A1 (ja) * 2009-03-31 2010-10-07 戸田工業株式会社 複合ｒｆタグ、該複合ｒｆタグを設置した工具
US8366009B2 (en) 2010-08-12 2013-02-05 Féinics Amatech Teoranta Coupling in and to RFID smart cards
DE102010039156A1 (de) * 2010-08-10 2012-02-16 Robert Bosch Gmbh Verfahren zum Herstellen einer elektrischen Schaltung und elektrische Schaltung
US8789762B2 (en) 2010-08-12 2014-07-29 Feinics Amatech Teoranta RFID antenna modules and methods of making
US8991712B2 (en) 2010-08-12 2015-03-31 Féinics Amatech Teoranta Coupling in and to RFID smart cards
JP2012049434A (ja) 2010-08-30 2012-03-08 Sony Corp 電子部品、給電装置、受電装置、およびワイヤレス給電システム
JP5087118B2 (ja) * 2010-09-28 2012-11-28 株式会社東芝 通信機器
US9781783B2 (en) 2011-04-15 2017-10-03 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, display device, light-emitting system, and display system
EP2742464A1 (de) * 2011-08-08 2014-06-18 Féinics AmaTech Teoranta Verbesserte kopplung bei und an rfid-chipkarten
JP2014527230A (ja) * 2011-08-08 2014-10-09 フェニックス アマテック テオランタ Ｒｆｉｄスマートカードに関する結合の向上
US10403511B2 (en) * 2013-01-14 2019-09-03 Intel Corporation Backside redistribution layer patch antenna
TWI515843B (zh) * 2013-12-16 2016-01-01 南茂科技股份有限公司 晶片封裝結構
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
CN107705976B (zh) * 2017-08-30 2020-08-25 潍坊歌尔微电子有限公司 一种线圈的制造方法、线圈、电子设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10162112A (ja) 1996-12-02 1998-06-19 Mitsui High Tec Inc Ｉｃカード
JP4255141B2 (ja) * 1998-02-02 2009-04-15 株式会社ルネサステクノロジ 半導体装置
US6525410B1 (en) * 1998-07-24 2003-02-25 Texas Instruments Incorporated Integrated circuit wireless tagging
JP2000137779A (ja) * 1998-10-30 2000-05-16 Hitachi Maxell Ltd 非接触情報媒体とその製造方法
DE10196382T1 (de) * 2000-06-21 2003-12-04 Hitachi Maxell Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird

Also Published As

Publication number Publication date
US6838773B2 (en) 2005-01-04
KR20030041870A (ko) 2003-05-27
WO2001099193A1 (en) 2001-12-27
AU7457401A (en) 2002-01-02
CN1436370A (zh) 2003-08-13
US20030116790A1 (en) 2003-06-26
KR100741039B1 (ko) 2007-07-20
CN1275328C (zh) 2006-09-13

Similar Documents

Publication Publication Date Title
DE10196382T1 (de) Halbleiterchip und Halbleitervorrichtung, für die der Halbleiterchip verwendet wird
DE50112868D1 (de) Halbleiter-chip
DE60200455D1 (de) Thermisch aushärtbare Harzverbindung und Halbleitervorrichtung, die dieselbe verwendet
DE60004614D1 (de) Integrierte Halbleitervorrichtung
NO20023642D0 (no) Nitrid halvlederlaserinnretning
DE60232480D1 (de) Hochspannungs-Halbleiterbauelement
DE60202425D1 (de) Hochfrequenz-Halbleitervorrichtung
DE60229776D1 (de) Polstervorrichtung
FR2817658B1 (fr) Dispositif semi-conducteur
DE69900274D1 (de) Mehrchip-Halbleiter-Leistungsbauelement vom Druckkontakttyp
DE10196595T1 (de) Vorrichtung und Halbleiter-Prüfvorrichtung
DE60227475D1 (de) Halbleiterbauelement
DE69942813D1 (de) Halbleitervorrichtung
DE69937739D1 (de) Halbleitervorrichtung
DE60140691D1 (de) Halbleiterdiodenbauelement
DE60142141D1 (de) Halbleiterbauelement
DE60211244D1 (de) Halbleiterbauelement
DE69915903D1 (de) Gehäuse für Halbleiterbauelemente und Halbleitermodul, das das Gehäuse verwendet
DE50114925D1 (de) Strahlungsemittierender halbleiterchip
DE19980453T1 (de) Halbleiterbauelement-Testgerät
DE60005959D1 (de) Halbleiteranordnung
DE60133429D1 (de) Verdrahtungssubstrat, seine Herstellung und Halbleiterbauteil
DE10191585B8 (de) Halbleitervorrichtung
DE10291889D2 (de) Halbleiterchip für die Optoelektronik
DE60141670D1 (de) Halbleiterspeicherbauelement, dessen Herstellungsverfahren und dessen Betriebsweise

Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: KYUSHU HITACHI MAXELL LTD., FUKUOKA, JP

R016 Response to examination communication
R016 Response to examination communication
R002 Refusal decision in examination/registration proceedings
R003 Refusal decision now final

Effective date: 20131212