DE10084864T1 - Verfahren und Struktur zum Fertigen von gehäusten Halbleiterbauelementen mit verbesserter Ausbeute - Google Patents

Verfahren und Struktur zum Fertigen von gehäusten Halbleiterbauelementen mit verbesserter Ausbeute

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Publication number
DE10084864T1
DE10084864T1 DE10084864T DE10084864T DE10084864T1 DE 10084864 T1 DE10084864 T1 DE 10084864T1 DE 10084864 T DE10084864 T DE 10084864T DE 10084864 T DE10084864 T DE 10084864T DE 10084864 T1 DE10084864 T1 DE 10084864T1
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Germany
Prior art keywords
semiconductor devices
packaged semiconductor
improved yield
manufacturing packaged
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10084864T
Other languages
English (en)
Inventor
Tongbi Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE10084864T1 publication Critical patent/DE10084864T1/de
Ceased legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
DE10084864T 1999-07-30 2000-07-28 Verfahren und Struktur zum Fertigen von gehäusten Halbleiterbauelementen mit verbesserter Ausbeute Ceased DE10084864T1 (de)

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US09/365,356 US6774480B1 (en) 1999-07-30 1999-07-30 Method and structure for manufacturing improved yield semiconductor packaged devices
PCT/US2000/020583 WO2001009939A1 (en) 1999-07-30 2000-07-28 Method and structure for manufacturing improved yield semiconductor packaged devices

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JP (1) JP2003506868A (de)
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WO (1) WO2001009939A1 (de)

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US6774480B1 (en) 2004-08-10
KR20020030087A (ko) 2002-04-22
US20050285279A1 (en) 2005-12-29
US6902956B2 (en) 2005-06-07
US20020013014A1 (en) 2002-01-31
KR100614431B1 (ko) 2006-08-23
EP1212791A4 (de) 2008-05-28
WO2001009939A1 (en) 2001-02-08
US6586277B2 (en) 2003-07-01
AU6387900A (en) 2001-02-19
JP2003506868A (ja) 2003-02-18
US7199463B2 (en) 2007-04-03
EP1212791A1 (de) 2002-06-12
US20020058358A1 (en) 2002-05-16

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