DE60011702D1 - Verfahren und Struktur zum Verbinden von Schichten in einer Halbleitervorrichtung - Google Patents

Verfahren und Struktur zum Verbinden von Schichten in einer Halbleitervorrichtung

Info

Publication number
DE60011702D1
DE60011702D1 DE60011702T DE60011702T DE60011702D1 DE 60011702 D1 DE60011702 D1 DE 60011702D1 DE 60011702 T DE60011702 T DE 60011702T DE 60011702 T DE60011702 T DE 60011702T DE 60011702 D1 DE60011702 D1 DE 60011702D1
Authority
DE
Germany
Prior art keywords
semiconductor device
connecting layers
layers
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60011702T
Other languages
English (en)
Other versions
DE60011702T2 (de
Inventor
Min Cao
Jeremy A Theil
Gary W Ray
Dietrich W Vook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Application granted granted Critical
Publication of DE60011702D1 publication Critical patent/DE60011702D1/de
Publication of DE60011702T2 publication Critical patent/DE60011702T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60011702T 1999-04-26 2000-04-25 Verfahren und Struktur zum Verbinden von Schichten in einer Halbleitervorrichtung Expired - Fee Related DE60011702T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/299,687 US6387736B1 (en) 1999-04-26 1999-04-26 Method and structure for bonding layers in a semiconductor device
US299687 1999-04-26

Publications (2)

Publication Number Publication Date
DE60011702D1 true DE60011702D1 (de) 2004-07-29
DE60011702T2 DE60011702T2 (de) 2005-06-30

Family

ID=23155820

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60011702T Expired - Fee Related DE60011702T2 (de) 1999-04-26 2000-04-25 Verfahren und Struktur zum Verbinden von Schichten in einer Halbleitervorrichtung

Country Status (4)

Country Link
US (2) US6387736B1 (de)
EP (1) EP1049150B1 (de)
JP (1) JP2000315690A (de)
DE (1) DE60011702T2 (de)

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US6956268B2 (en) * 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
US20070128827A1 (en) * 2001-09-12 2007-06-07 Faris Sadeg M Method and system for increasing yield of vertically integrated devices
US7163826B2 (en) * 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US7033910B2 (en) * 2001-09-12 2006-04-25 Reveo, Inc. Method of fabricating multi layer MEMS and microfluidic devices
US6875671B2 (en) * 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
WO2004071948A2 (en) * 2003-02-10 2004-08-26 Reveo, Inc. Micro-nozzle, nano-nozzle, manufacturing methods therefor, applications therefor
US7768500B2 (en) * 2003-06-16 2010-08-03 Humanscale Corporation Ergonomic pointing device
KR20080108372A (ko) * 2003-12-24 2008-12-12 쿄세라 코포레이션 세라믹 히터 및 그 제조 방법
US7557799B2 (en) 2004-06-17 2009-07-07 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. System for determining pointer position, movement, and angle
DE102005017655B4 (de) * 2005-04-15 2008-12-11 Polyic Gmbh & Co. Kg Mehrschichtiger Verbundkörper mit elektronischer Funktion
DE102005031448A1 (de) 2005-07-04 2007-01-11 Polyic Gmbh & Co. Kg Aktivierbare optische Schicht
DE102005035590A1 (de) * 2005-07-29 2007-02-01 Polyic Gmbh & Co. Kg Elektronisches Bauelement
DE102005035589A1 (de) 2005-07-29 2007-02-01 Polyic Gmbh & Co. Kg Verfahren zur Herstellung eines elektronischen Bauelements
DE102005042166A1 (de) * 2005-09-06 2007-03-15 Polyic Gmbh & Co.Kg Organisches Bauelement und ein solches umfassende elektrische Schaltung
DE102005044306A1 (de) * 2005-09-16 2007-03-22 Polyic Gmbh & Co. Kg Elektronische Schaltung und Verfahren zur Herstellung einer solchen
US8846149B2 (en) * 2006-02-21 2014-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Delamination resistant semiconductor film and method for forming the same
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
US8647981B1 (en) * 2012-08-31 2014-02-11 Micron Technology, Inc. Methods of forming patterns, and methods of forming integrated circuitry
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
US9082885B2 (en) * 2013-05-30 2015-07-14 Samsung Electronics Co., Ltd. Semiconductor chip bonding apparatus and method of forming semiconductor device using the same
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
JP6770432B2 (ja) 2014-01-27 2020-10-14 コーニング インコーポレイテッド 薄いシートの担体との制御された結合のための物品および方法
KR20160145062A (ko) 2014-04-09 2016-12-19 코닝 인코포레이티드 디바이스 변경된 기판 물품 및 제조 방법
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
JP2018524201A (ja) 2015-05-19 2018-08-30 コーニング インコーポレイテッド シートをキャリアと結合するための物品および方法
JP7106276B2 (ja) 2015-06-26 2022-07-26 コーニング インコーポレイテッド シート及び担体を有する物品及び方法
TW201825623A (zh) 2016-08-30 2018-07-16 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI810161B (zh) 2016-08-31 2023-08-01 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
CN111615567B (zh) 2017-12-15 2023-04-14 康宁股份有限公司 用于处理基板的方法和用于制备包括粘合片材的制品的方法

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US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface
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US5084399A (en) * 1984-10-01 1992-01-28 Fuji Xerox Co., Ltd. Semi conductor device and process for fabrication of same
JP2501118B2 (ja) * 1988-06-17 1996-05-29 忠弘 大見 半導体装置の製造方法
US5488012A (en) * 1993-10-18 1996-01-30 The Regents Of The University Of California Silicon on insulator with active buried regions
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
US5661081A (en) 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
US5739046A (en) 1994-09-30 1998-04-14 United Microelectronics Corporation Method of making a reliable barrier layer
US5707894A (en) 1995-10-27 1998-01-13 United Microelectronics Corporation Bonding pad structure and method thereof
US5783487A (en) 1996-02-20 1998-07-21 Motorola, Inc. Method of coupling titanium to a semiconductor substrate and semiconductor device thereof
EP0793406B1 (de) * 1996-02-29 2005-12-28 Tokyo Ohka Kogyo Co., Ltd. Verfahren zur Herstellung von mehrschichtigen Leiterplatten
US5858873A (en) 1997-03-12 1999-01-12 Lucent Technologies Inc. Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof

Also Published As

Publication number Publication date
JP2000315690A (ja) 2000-11-14
EP1049150B1 (de) 2004-06-23
DE60011702T2 (de) 2005-06-30
EP1049150A1 (de) 2000-11-02
US6387736B1 (en) 2002-05-14
US20010006846A1 (en) 2001-07-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT

8339 Ceased/non-payment of the annual fee