DE10036891A1 - Verfahren zum Herstellen einer Schottky-Diode und einer verwandten Struktur - Google Patents
Verfahren zum Herstellen einer Schottky-Diode und einer verwandten StrukturInfo
- Publication number
- DE10036891A1 DE10036891A1 DE10036891A DE10036891A DE10036891A1 DE 10036891 A1 DE10036891 A1 DE 10036891A1 DE 10036891 A DE10036891 A DE 10036891A DE 10036891 A DE10036891 A DE 10036891A DE 10036891 A1 DE10036891 A1 DE 10036891A1
- Authority
- DE
- Germany
- Prior art keywords
- dopant
- type
- ldd
- layer
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/051—Manufacture or treatment of Schottky diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
- H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
- H10D84/617—Combinations of vertical BJTs and only diodes
Landscapes
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/364,232 US6261932B1 (en) | 1999-07-29 | 1999-07-29 | Method of fabricating Schottky diode and related structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE10036891A1 true DE10036891A1 (de) | 2001-03-22 |
Family
ID=23433620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10036891A Withdrawn DE10036891A1 (de) | 1999-07-29 | 2000-07-28 | Verfahren zum Herstellen einer Schottky-Diode und einer verwandten Struktur |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6261932B1 (https=) |
| JP (1) | JP2001102462A (https=) |
| DE (1) | DE10036891A1 (https=) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20250081684A1 (en) * | 2023-09-01 | 2025-03-06 | AUO Corporation | Display panel and method of fabricating the same |
| US20250126856A1 (en) * | 2023-10-13 | 2025-04-17 | Avago Technologies International Sales Pte. Limited | Semiconductor device with increased operating voltage characteristics |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7274082B2 (en) * | 2000-01-19 | 2007-09-25 | Adrena, Inc. | Chemical sensor using chemically induced electron-hole production at a schottky barrier |
| US6903433B1 (en) * | 2000-01-19 | 2005-06-07 | Adrena, Inc. | Chemical sensor using chemically induced electron-hole production at a schottky barrier |
| US6956274B2 (en) * | 2002-01-11 | 2005-10-18 | Analog Devices, Inc. | TiW platinum interconnect and method of making the same |
| US6927460B1 (en) | 2002-02-15 | 2005-08-09 | Fairchild Semiconductor Corporation | Method and structure for BiCMOS isolated NMOS transistor |
| US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
| US7902029B2 (en) * | 2002-08-12 | 2011-03-08 | Acorn Technologies, Inc. | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor |
| US7176483B2 (en) * | 2002-08-12 | 2007-02-13 | Acorn Technologies, Inc. | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US7084423B2 (en) | 2002-08-12 | 2006-08-01 | Acorn Technologies, Inc. | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| JP4637553B2 (ja) * | 2004-11-22 | 2011-02-23 | パナソニック株式会社 | ショットキーバリアダイオード及びそれを用いた集積回路 |
| US7064407B1 (en) * | 2005-02-04 | 2006-06-20 | Micrel, Inc. | JFET controlled schottky barrier diode |
| US7388271B2 (en) * | 2005-07-01 | 2008-06-17 | Texas Instruments Incorporated | Schottky diode with minimal vertical current flow |
| US7737532B2 (en) * | 2005-09-06 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Schottky source-drain CMOS for high mobility and low barrier |
| KR101338160B1 (ko) * | 2007-07-06 | 2013-12-06 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성 방법 |
| US8338906B2 (en) * | 2008-01-30 | 2012-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Schottky device |
| US20100258899A1 (en) * | 2009-04-08 | 2010-10-14 | Chih-Tsung Huang | Schottky diode device with an extended guard ring and fabrication method thereof |
| US20130241007A1 (en) * | 2012-03-15 | 2013-09-19 | International Business Machines Corporation | Use of band edge gate metals as source drain contacts |
| US9620611B1 (en) | 2016-06-17 | 2017-04-11 | Acorn Technology, Inc. | MIS contact structure with metal oxide conductor |
| WO2018094205A1 (en) | 2016-11-18 | 2018-05-24 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
| CN109638084B (zh) * | 2018-12-11 | 2021-12-03 | 成都芯源系统有限公司 | 一种横向肖特基二极管及其制作方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2460040A1 (fr) | 1979-06-22 | 1981-01-16 | Thomson Csf | Procede pour realiser une diode schottky a tenue en tension amelioree |
| JP3061406B2 (ja) * | 1990-09-28 | 2000-07-10 | 株式会社東芝 | 半導体装置 |
| US5150177A (en) | 1991-12-06 | 1992-09-22 | National Semiconductor Corporation | Schottky diode structure with localized diode well |
| EP0562309B1 (en) * | 1992-03-25 | 2002-06-12 | Texas Instruments Incorporated | Planar process using common alignment marks for well implants |
| US5665993A (en) * | 1994-09-29 | 1997-09-09 | Texas Instruments Incorporated | Integrated circuit including a FET device and Schottky diode |
| JP3093620B2 (ja) * | 1995-10-19 | 2000-10-03 | 日本電気株式会社 | 半導体装置の製造方法 |
| FR2756104B1 (fr) * | 1996-11-19 | 1999-01-29 | Sgs Thomson Microelectronics | Fabrication de circuits integres bipolaires/cmos |
| FR2758004B1 (fr) * | 1996-12-27 | 1999-03-05 | Sgs Thomson Microelectronics | Transistor bipolaire a isolement dielectrique |
| US5973372A (en) * | 1997-12-06 | 1999-10-26 | Omid-Zohoor; Farrokh | Silicided shallow junction transistor formation and structure with high and low breakdown voltages |
-
1999
- 1999-07-29 US US09/364,232 patent/US6261932B1/en not_active Expired - Fee Related
-
2000
- 2000-07-28 DE DE10036891A patent/DE10036891A1/de not_active Withdrawn
- 2000-07-31 JP JP2000231509A patent/JP2001102462A/ja not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20250081684A1 (en) * | 2023-09-01 | 2025-03-06 | AUO Corporation | Display panel and method of fabricating the same |
| US20250126856A1 (en) * | 2023-10-13 | 2025-04-17 | Avago Technologies International Sales Pte. Limited | Semiconductor device with increased operating voltage characteristics |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001102462A (ja) | 2001-04-13 |
| US6261932B1 (en) | 2001-07-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| 8139 | Disposal/non-payment of the annual fee |