CN86101209A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN86101209A
CN86101209A CN86101209.7A CN86101209A CN86101209A CN 86101209 A CN86101209 A CN 86101209A CN 86101209 A CN86101209 A CN 86101209A CN 86101209 A CN86101209 A CN 86101209A
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emitter
table top
polysilicon
base
substrate
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彼得·丹尼斯·斯科维尔
彼特·弗里德·布洛姆利
罗格·莱斯利·贝克
加里·约翰·托姆金斯
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

一种完全自对准的多晶硅发射极双极晶体管。P+基极接触(12)的自对准是通过利用发射极台面(7)的氧化侧壁(8)(侧壁隔层)作为P+基极接触注入掩模的一部分而获得的，集电极接触(13)的对准是利用多晶硅对准台面(14)的氧化侧壁而获得的，该对准台面限定在同发射极台面(7)一样的多晶硅中，但淀积在氧化物(2)上，而不是淀积在注入的基区(5)中。

Description

本发明涉及半导体器件，特别涉及具有多晶硅发射极的双极晶体管及其制造方法。
使用多晶硅发射极能改善双极晶体管的特性。到目前为止，已公开了若干种自对准这种器件的方法，例如IEEE    JSSC    SC17    1983第266页上唐.D.（Tang    D.）的方法和IEEE    EIDM    Techn.Drg.1983第16页上Sakai.T.的方法。这些方法都依赖于使用多晶硅基极接触，因而需要两层多晶硅。
根据本发明的一个构思，提供了一种制造双极晶体管的方法，它包括的步骤有：在一半导体衬底中的基区的未氧化表面上限定一多晶硅发射极台面，氧化台面的侧壁以及基区外露的未氧化表面，至少用台面的一个侧壁作为注入掩模，把基极接触区注入与基区相接的衬底，这样基极接触区就与发射极自动对准。
根据本发明的另一构思，提供了一种双极晶体管，它包括一个与基区连接的多晶硅发射极台面，和一基极接触，发射极具有一在晶体管的制造过程中起基极接触自对准作用的氧化侧壁。
下面将参照附图说明本发明的实施例。
在附图中：
图1到图6大略地示出了根据本发明的一个实施例制造自对准基极接触的连续加工各阶段的剖面图。
图7示出了全部自对准多晶硅发射极双极晶体管的断面图。
首先参照图1到图6说明制造自对准基极接触所需的连续加工阶段。将n型单晶硅的衬底1氧化以提供一层二氧化硅表面2，加上一层光刻胶3，利用一适当的光刻掩模（未示出），在光刻胶3上开一个窗口4，该窗口4限定了基极区域（图1）。利用离子注入硼的技术，形成基极5。注入硼之后，利用基极掩模（光刻胶3）将窗口4露出的氧化层腐蚀掉，以便限定要形成发射极的区域。去掉光刻胶3（图2）。如果需要对表面进行处理以产生层间氧化层的话，现在就可以进行。而后，沉积一层多晶硅6（图3）并掺入n+，例如用砷或磷，在确定发射极区域之后，将多晶硅干腐蚀以产生图4的结构，n+的多晶硅台面或发射极7大体处于中心位置。要对于腐蚀进行控制以在单晶硅衬底1上产生好的各向异性和高选择性。我们已用实验给出了10∶1的选择性。对于典型的层厚和过腐蚀，用这种方法，在多晶硅腐蚀过程中被耗去的基极将小于500
Figure 86101209_IMG2
（0.05μm）。而后在此结构上形成氧化物的侧壁隔离层8（图5）。例如，这一隔离层可用我们的共同未决申请（第 号）（系列号 ）（P.D.Scovell-R.L.Baker 14-6）中所述的氧化法或用一致的沉积氧化物的活性离子腐蚀（RIE）。我们的共同未决申请中所述的方法包括在多晶硅台面（发射极）上覆盖一层氮化硅，在低温下氧化台面的侧壁，温度最好低于900℃，以充分利用多晶硅和单晶硅氧化速率不同的优点。经过这一处理，就形成了一n型区域9。而后，在此结构上形成一层光刻胶10（图6），利用一适当的掩模使之成形，以提供一窗口11，即限定一P+接触掩模。注入例如硼来形成基极接触12，由于使用多晶硅和侧壁隔离层8作为P+接触掩模的一部分，使基极接触12与多晶硅发射区7自对准。要按图6的结构完成一双极晶体管，需要一衬底体的集电极接触并进行适当的金属化，以提供基极、集电极接触以及多晶硅发射极与外部的电气连接。
图7给出了一完整的双极晶体管的断面图。此晶体管有集电极接触13，利用多晶硅条（对准台面）14将接触13与发射极边缘对准，多晶硅条14用与发射极台面7一样的掩模方法继而腐蚀确定。条14的侧壁17象发射极7的侧壁一样也要进行氧化。加上光刻胶层15并利用一掩模（未示出）使之成形，以便提供窗口16注入砷，来形成集电极接触13。掩模只需是一“稀薄的”掩模，因为多晶硅条14最外面的氧化边限定了集电极接触的边，且只需光刻胶来保护不要注入集电极接触材料的区域。多晶硅条的边限定了集电极接触和发射极边之间的距离。这样，此器件就完全自对准了。
如此，可完成基极接触的自对准，其方法是利用单层多晶硅和侧壁，这种自对准比利用两层多晶硅的方法（就象上述已知方法中所需的）要简单。

Claims (12)

1、一种制造双极型晶体管的方法，包括下列步骤：在半导体衬底中基区的未氧化表面上限定一多晶硅发射极台面；氧化台面的侧壁和基区暴露的未氧化表面；将基极接触区注入与基区接触的衬底；至少利用台面的一个氧化侧壁作为注入掩模的一部分，这样，基极接触区就与发射极自对准。
2、如权利要求1所要求的一种方法，其中，基区是经一掩模层上的窗口，穿过衬底上的氧化层注入衬底的，而后去掉窗口所暴露的氧化层。
3、如权利要求2所要求的方法，其中，在去掉窗口所暴露的氧化层之后，根据淀积在衬底上的多晶硅层限定台面。
4、如权利要求3所要求的方法，其中，台面的限定包括给多晶硅层加掩模和干腐蚀。
5、如权利要求3或4所要求的方法，进一步包括下列步骤：根据所述多晶硅层，至少限定一个多晶硅接触对准台面，此对准台面置于氧化层上且其侧壁在所述氧化步骤中被氧化，利用台面的至少一个氧化侧壁作为注入掩模的一部分，在衬底中注入一集电极接触区，这样，就由台面限定了发射极和集电极接触之间的间隙。
6、一种参照图1至图6所述的双极晶体管的制造方法（参照或不参照图7）。
7、一种根据前述任一权利要求的方法所制造的双极晶体管。
8、一种双极晶体管，包括一与基区相连的多晶硅发射极台面，和一基极接触，在该晶体管的制造期间，带有氧化侧壁的发射极起基极接触自对准的作用。
9、如权利要求8所要求的双极晶体管，其中，发射极基本上置于基区中心，该晶体管包括置于发射极相对两侧的两个基极接触，它们通过相应的发射极侧壁与发射极自对准。
10、如权利要求8或9所要求的双极晶体管，其中，基区被置于衬底的表面，该晶体管包括与衬底相连的集电极接触。
11、如权利要求10所要求的双极晶体管，包括与发射极台面隔开的多晶硅对准台面，并限定发射极与集电极接触间的距离。
12、一种基本上参照图1至图6所述的双极晶体管（参照或不参照图7）。
CN86101209A 1985-03-23 1986-02-26 半导体器件 Expired CN1009887B (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037061A (zh) * 2018-07-26 2018-12-18 深圳市南硕明泰科技有限公司 一种晶体管及其制作方法

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
US5005066A (en) * 1987-06-02 1991-04-02 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US4803175A (en) * 1987-09-14 1989-02-07 Motorola Inc. Method of fabricating a bipolar semiconductor device with silicide contacts
US5001081A (en) * 1988-01-19 1991-03-19 National Semiconductor Corp. Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5124817A (en) * 1988-01-19 1992-06-23 National Semiconductor Corporation Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US5179031A (en) * 1988-01-19 1993-01-12 National Semiconductor Corporation Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
US4857476A (en) * 1988-01-26 1989-08-15 Hewlett-Packard Company Bipolar transistor process using sidewall spacer for aligning base insert
GB8810973D0 (en) * 1988-05-10 1988-06-15 Stc Plc Improvements in integrated circuits
KR910005401B1 (ko) * 1988-09-07 1991-07-29 경상현 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법
JPH02170538A (ja) * 1988-12-23 1990-07-02 Toshiba Corp 半導体装置の製造方法
US4927775A (en) * 1989-03-06 1990-05-22 Motorola Inc. Method of fabricating a high performance bipolar and MOS device
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US5008207A (en) * 1989-09-11 1991-04-16 International Business Machines Corporation Method of fabricating a narrow base transistor
US5132765A (en) * 1989-09-11 1992-07-21 Blouse Jeffrey L Narrow base transistor and method of fabricating same
US5268314A (en) * 1990-01-16 1993-12-07 Philips Electronics North America Corp. Method of forming a self-aligned bipolar transistor
US5124271A (en) * 1990-06-20 1992-06-23 Texas Instruments Incorporated Process for fabricating a BiCMOS integrated circuit
US5013671A (en) * 1990-06-20 1991-05-07 Texas Instruments Incorporated Process for reduced emitter-base capacitance in bipolar transistor
US5082796A (en) * 1990-07-24 1992-01-21 National Semiconductor Corporation Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers
US6011283A (en) * 1992-10-19 2000-01-04 Hyundai Electronics America Pillar emitter for BiCMOS devices
US5348896A (en) * 1992-11-27 1994-09-20 Winbond Electronic Corp. Method for fabricating a BiCMOS device
US5320972A (en) * 1993-01-07 1994-06-14 Northern Telecom Limited Method of forming a bipolar transistor
US5476800A (en) * 1994-01-31 1995-12-19 Burton; Gregory N. Method for formation of a buried layer for a semiconductor device
US5476803A (en) * 1994-10-17 1995-12-19 Liu; Kwo-Jen Method for fabricating a self-spaced contact for semiconductor devices
CA2166450C (en) * 1995-01-20 2008-03-25 Ronald Salovey Chemically crosslinked ultrahigh molecular weight polyethylene for artificial human joints
JP2000514481A (ja) * 1996-07-09 2000-10-31 ザ オーソピーディック ホスピタル 放射線及び熱処理を用いた低摩耗ポリエチレンの架橋
SE519628C2 (sv) * 1997-03-04 2003-03-18 Ericsson Telefon Ab L M Tillverkningsförfarande för halvledarkomponent med deponering av selektivt utformat material,vilket är ogenomträngligt för dopjoner
US5849613A (en) * 1997-10-23 1998-12-15 Chartered Semiconductor Manufacturing Ltd. Method and mask structure for self-aligning ion implanting to form various device structures
US5904536A (en) * 1998-05-01 1999-05-18 National Semiconductor Corporation Self aligned poly emitter bipolar technology using damascene technique
US6225181B1 (en) 1999-04-19 2001-05-01 National Semiconductor Corp. Trench isolated bipolar transistor structure integrated with CMOS technology
US6262472B1 (en) 1999-05-17 2001-07-17 National Semiconductor Corporation Bipolar transistor compatible with CMOS utilizing tilted ion implanted base
US6043130A (en) * 1999-05-17 2000-03-28 National Semiconductor Corporation Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base
US6313000B1 (en) 1999-11-18 2001-11-06 National Semiconductor Corporation Process for formation of vertically isolated bipolar transistor device
AT4149U1 (de) * 1999-12-03 2001-02-26 Austria Mikrosysteme Int Verfahren zum herstellen von strukturen in chips
US6352901B1 (en) * 2000-03-24 2002-03-05 Industrial Technology Research Institute Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions
DE202006017371U1 (de) * 2006-11-13 2008-03-20 Big Dutchman Pig Equipment Gmbh Förderkette
JP4498407B2 (ja) 2006-12-22 2010-07-07 キヤノン株式会社 プロセスカートリッジ、電子写真画像形成装置、及び、電子写真感光体ドラムユニット
RU2562852C2 (ru) * 2009-08-11 2015-09-10 Конинклейке Филипс Электроникс, Н.В. Немагнитная высоковольтная система зарядки для использования в устройствах для стимуляции сердца

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL149638B (nl) * 1966-04-14 1976-05-17 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting bevattende ten minste een veldeffecttransistor, en halfgeleiderinrichting, vervaardigd volgens deze werkwijze.
JPS539469A (en) * 1976-07-15 1978-01-27 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device having electrode of stepped structure and its production
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory
JPS55123157A (en) * 1979-03-16 1980-09-22 Oki Electric Ind Co Ltd High-stability ion-injected resistor
JPS5690561A (en) * 1979-12-22 1981-07-22 Fujitsu Ltd Manufacture of semiconductor device
JPS56115560A (en) * 1980-02-18 1981-09-10 Toshiba Corp Manufacture of semiconductor device
DE3160917D1 (en) * 1980-03-22 1983-10-27 Tokyo Shibaura Electric Co Semiconductor device and method for fabricating the same
JPS56148863A (en) * 1980-04-21 1981-11-18 Nec Corp Manufacture of semiconductor device
US4691219A (en) * 1980-07-08 1987-09-01 International Business Machines Corporation Self-aligned polysilicon base contact structure
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
JPS5936432B2 (ja) * 1980-08-25 1984-09-04 株式会社東芝 半導体装置の製造方法
DE3174638D1 (en) * 1980-10-29 1986-06-19 Fairchild Camera Instr Co A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
GB2090053B (en) * 1980-12-19 1984-09-19 Philips Electronic Associated Mesfet
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
JPS5852817A (ja) * 1981-09-25 1983-03-29 Hitachi Ltd 半導体装置及びその製造方法
JPS58132964A (ja) * 1982-02-01 1983-08-08 Toshiba Corp 半導体装置の製造方法
DE3272436D1 (en) * 1982-05-06 1986-09-11 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor
EP0103653B1 (de) * 1982-09-20 1986-12-10 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
JPS5989457A (ja) * 1982-11-15 1984-05-23 Hitachi Ltd 半導体装置の製造方法
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
JPS59108361A (ja) * 1982-12-14 1984-06-22 Olympus Optical Co Ltd 半導体装置およびその製造方法
EP0122004A3 (en) * 1983-03-08 1986-12-17 Trw Inc. Improved bipolar transistor construction
US4529996A (en) * 1983-04-14 1985-07-16 Allied Coporation Indium phosphide-boron phosphide heterojunction bipolar transistor
DE3369030D1 (en) * 1983-04-18 1987-02-12 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit comprising at least one insulated gate field-effect transistor
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037061A (zh) * 2018-07-26 2018-12-18 深圳市南硕明泰科技有限公司 一种晶体管及其制作方法

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GB2172744B (en) 1989-07-19
EP0202727A3 (en) 1988-03-23
EP0199061A3 (en) 1988-03-30
GB2172744A (en) 1986-09-24
KR860007751A (ko) 1986-10-17
EP0202727B1 (en) 1992-01-08
DE3683316D1 (de) 1992-02-20
CN1009887B (zh) 1990-10-03
KR940006691B1 (ko) 1994-07-25
IN166243B (zh) 1990-03-31
IE57334B1 (en) 1992-07-29
US4745080A (en) 1988-05-17
GB8507602D0 (en) 1985-05-01
JPS61259570A (ja) 1986-11-17
EP0199061A2 (en) 1986-10-29
CN86101884A (zh) 1986-11-12
JPH0812863B2 (ja) 1996-02-07
US5055419A (en) 1991-10-08
PH24294A (en) 1990-05-29
EP0202727A2 (en) 1986-11-26
US4916517A (en) 1990-04-10
IE860380L (en) 1986-09-23
JPS61229362A (ja) 1986-10-13
KR860007752A (ko) 1986-10-17

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