KR860007752A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR860007752A
KR860007752A KR1019860002151A KR860002151A KR860007752A KR 860007752 A KR860007752 A KR 860007752A KR 1019860002151 A KR1019860002151 A KR 1019860002151A KR 860002151 A KR860002151 A KR 860002151A KR 860007752 A KR860007752 A KR 860007752A
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KR
South Korea
Prior art keywords
mesa
emitter
substrate
contact
base
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KR1019860002151A
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English (en)
Inventor
데니스 스코벨 피터
프레드 블롬레이 피터
레슬리 베이커 로저
존 톰 킨스 게어리
Original Assignee
더블유. 제이. 바움
아이티티 인더스트리스 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 더블유. 제이. 바움, 아이티티 인더스트리스 인코포레이티드 filed Critical 더블유. 제이. 바움
Publication of KR860007752A publication Critical patent/KR860007752A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도에서 3도는 본 발명의 한 실시예에 따른 자기 정렬된 베이스 접점의 제조에 있어서 연속처리 단계를 개략적으로 도시한 횡단면도.
* 도면의 주요 부분에 대한 설명
(1) 기판, (2) 실리콘 디옥사이드, (3) 광저항, (4) 윈도우, (5) 베이스, (6) 폴리실리콘, (7) 에미터, (8) 측벽스페이서, (9) n형 영역, (10) 광저항 층, (11) 윈도우, (12) 베이스 접점, (13) 콜렉터 접점, (14) 폴리실리콘 스트라이, (15) 광저항 층, (16) 윈도우 (17) 측벽.

Claims (12)

  1. 반도체 기판에 놓인 베이스영역의 산화되지 않은 표면상에 다결성 실리콘 에미터 메사를 형성하는 단계와, 메사의 측벽 및 베이스 영역의 노출된 산화되지 않은 표면을 산화시키는 단계와, 베이스 접촉 영역이 에미터와 정렬되도록 이식 마스크의 일부로서 적어도 하나의 메사의 산화된 측벽을 사용하여 베이스 영역과 접촉되게 베이스 접촉 영역을 기판에 이식하는 단계를 포함하는 것을 특징으로 하는 양극성 트랜지스터 제조방법.
  2. 제1항에 있어서, 베이스 영역이 그 위에 놓인 산화층과 마스크층 내의 윈도우를 통해 기판에 이식되며 이어서 윈도우에 의해 노출된 산화층이 제거되는 것을 특징으로 하는 방법.
  3. 제2항에 있어서, 윈도우에 의해 노출된 산화층의 제거에 이어 메사가 기판상에 위치한 다결정 실리콘 층으로부터 형성되는 것을 특징으로 하는 방법.
  4. 제3항에 있어서, 메사 형성이 다결정 실리콘을 적절히 마스킹하는 것과 건식식각하는 것을 포함하는 것을 특징으로 하는 방법.
  5. 제3항 또는 제4항에 있어서, 상기 다결정 실리콘의 상기 층으로부터 적어도 하나의 다결정 실리콘 접점의 정렬 메사를 형성하는 단계를 아울러 포함하는데, 그 정렬 메사는 산화층 상에 놓이고 그 정렬 메사의 측벽은 상기 산화단계 동안 산화되며, 또 에미터와 콜렉터 접점 사이의 간격이 정렬 메사에 의해 한정되도록 이식 마스크의 일부로서 적어도 하나의 산화된 정렬 메사의 측벽을 사용하여 콜렉터 접점 영역을 기판으로 이식하는 단게를 포함하는 것을 특징으로 하는 방법.
  6. 실질적으로 첨부도면의 제1도 내지 6도를 참조하고 또 제7도는 참조하거나 참조하지 않고 설명한 바와 같은 양극성 트랜지스터의 제조방법.
  7. 전술한 항중 어느 한항에 따른 방법에 의해 제조된 양극성 트랜지스터.
  8. 베이스 영역과 접촉된 다결정 실리콘 에미터 메사와 베이스 접점을 포함하는 것으로서, 그 에미터가 트랜지스터의 제조시 베이스 접점의 자기 정렬에 쓰이는 산화된 측벽을 갖는 것을 특징으로 하는 양극성 트랜지스터.
  9. 제8항에 있어서, 에미터가 실질적으로 베이스 영역의 표면에 대하여 중앙에 놓이고 두 개의 베이스 접촉 영역이 에미터의 반대측상에 놓여 에미터의 각 산화된 측벽에 자기 정렬되는 것을 특징으로 하는 양극성 트랜지스터.
  10. 제8항 또는 9항에 있어서, 베이스영역이 기판의 표면 영역에 놓이고 기판에 대한 콜렉터 접점을 갖는 것을 특징으로 하는 양극성 트랜지스터.
  11. 제10항에 있어서, 에미터 메사로부터 이격되어 에미터와 콜렉터 접점 사이의 거리를 한정하는 다결정 실리콘 정렬 메사를 포함하는 것을 특징으로 하는 양극성 트랜지스터.
  12. 실질적으로 첨부도면의 제1도 내지 6도를 참조하고 또 제7도는 참조하거나 참조하지 않고 설명한 바와 같은 양극성 트랜지스터.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860002151A 1985-03-23 1986-03-22 반도체 장치 KR860007752A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8507602 1985-03-23
GB8507602A GB2172744B (en) 1985-03-23 1985-03-23 Semiconductor devices

Publications (1)

Publication Number Publication Date
KR860007752A true KR860007752A (ko) 1986-10-17

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Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019860001082A KR940006691B1 (ko) 1985-03-23 1986-02-17 개선된 쌍극형 트렌지스터 제조방법
KR1019860002151A KR860007752A (ko) 1985-03-23 1986-03-22 반도체 장치

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Country Status (10)

Country Link
US (3) US4745080A (ko)
EP (2) EP0202727B1 (ko)
JP (2) JPH0812863B2 (ko)
KR (2) KR940006691B1 (ko)
CN (2) CN1009887B (ko)
DE (1) DE3683316D1 (ko)
GB (1) GB2172744B (ko)
IE (1) IE57334B1 (ko)
IN (1) IN166243B (ko)
PH (1) PH24294A (ko)

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Also Published As

Publication number Publication date
KR860007751A (ko) 1986-10-17
EP0199061A2 (en) 1986-10-29
JPS61259570A (ja) 1986-11-17
US4745080A (en) 1988-05-17
US5055419A (en) 1991-10-08
JPH0812863B2 (ja) 1996-02-07
GB2172744A (en) 1986-09-24
EP0202727A3 (en) 1988-03-23
EP0202727A2 (en) 1986-11-26
CN1009887B (zh) 1990-10-03
PH24294A (en) 1990-05-29
IE860380L (en) 1986-09-23
EP0199061A3 (en) 1988-03-30
JPS61229362A (ja) 1986-10-13
IN166243B (ko) 1990-03-31
IE57334B1 (en) 1992-07-29
KR940006691B1 (ko) 1994-07-25
EP0202727B1 (en) 1992-01-08
GB2172744B (en) 1989-07-19
US4916517A (en) 1990-04-10
GB8507602D0 (en) 1985-05-01
DE3683316D1 (de) 1992-02-20
CN86101209A (zh) 1986-09-17
CN86101884A (zh) 1986-11-12

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