KR890007434A - 반도체 장치 제조방법 - Google Patents
반도체 장치 제조방법 Download PDFInfo
- Publication number
- KR890007434A KR890007434A KR1019880013487A KR880013487A KR890007434A KR 890007434 A KR890007434 A KR 890007434A KR 1019880013487 A KR1019880013487 A KR 1019880013487A KR 880013487 A KR880013487 A KR 880013487A KR 890007434 A KR890007434 A KR 890007434A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- semiconductor
- ion implantation
- regions
- exposed
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000000034 method Methods 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 4
- 238000005468 ion implantation Methods 0.000 claims 3
- 239000000463 material Substances 0.000 claims 2
- 238000012986 modification Methods 0.000 claims 2
- 230000004048 modification Effects 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000002244 precipitate Substances 0.000 claims 1
- 238000001556 precipitation Methods 0.000 claims 1
- 239000000047 product Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 방법 및 장치의 제조 단계의 도시도.
* 도면의 주요부분에 대한 부호의 설명
1 : 실리콘 기판 3 : 에피텍셜층
5 : 매립층 21 : 폴리실리콘 영역
Claims (13)
- 반도체의 표면의 일부를 노출한 구멍을 형성하도록 반도체 기판상에 제1층(9,11)을 패턴하는 단계, 노출된 상기 표면의 일부를 가진 상기 구멍내에 측벽 스페이서(13)를 형성하는 단계, 측벽 스페이서에 의해 피복되지 않는 상기 표면의 일부상에 재질(15)을 생성하는 단계, 상기 스페이서 하부의 상기 반도체의 일부를 노출시키도록 상기 측벽 스페이서를 제거하는 단계 및, 상기 반도체의 상기 노출된 부분을 변형하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제1항에 있어서, 상기 노출된 부분은 실리콘으로 구성되는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제2항에 있어서, 상기 제1층은 유전체로 구성되는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제3항에 있어서, 상기 생성은 선택적인 화학적 증기 침전으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제4항에 있어서, 상기 생성물은 실리콘으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제5항에 있어서, 상기 실리콘 산화 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제3항에 있어서, 상기 형성 단계는 실리콘 질화물을 침전하고 에칭하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제7항에 있어서, 상기 변형은 확산 또는 이온 이식으로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제8항에 있어서, 상기 변형은 이온 이식을 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제9항에 있어서, 상기 이온 이식은 대향 도전형의 두 영역을 형성하고, 상기 두 영역은 에미터 및 베이스 영역을 형성하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제6항에 있어서, 하부 재질의 일부를 노출하도록 상기 산화된 실리콘을 제거하고, 상기 노출부를 변형하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제10항에 있어서, 상기 기판은 콜렉터 영역을 형성하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제12항에 있어서, 상기 에미터 베이스 및 콜렉터 영역에 대해 전기 접촉부를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US111002 | 1987-10-20 | ||
US07/111,002 US4818713A (en) | 1987-10-20 | 1987-10-20 | Techniques useful in fabricating semiconductor devices having submicron features |
US111,002 | 1987-10-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890007434A true KR890007434A (ko) | 1989-06-19 |
KR910009033B1 KR910009033B1 (ko) | 1991-10-28 |
Family
ID=22336098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880013487A KR910009033B1 (ko) | 1987-10-20 | 1988-10-15 | 반도체 장치 제조 방법 |
Country Status (7)
Country | Link |
---|---|
US (1) | US4818713A (ko) |
EP (1) | EP0313250B1 (ko) |
JP (1) | JPH01124261A (ko) |
KR (1) | KR910009033B1 (ko) |
CA (1) | CA1299770C (ko) |
DE (1) | DE3886672T2 (ko) |
ES (1) | ES2047558T3 (ko) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051805A (en) * | 1987-07-15 | 1991-09-24 | Rockwell International Corporation | Sub-micron bipolar devices with sub-micron contacts |
US5059544A (en) * | 1988-07-14 | 1991-10-22 | International Business Machines Corp. | Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy |
JPH0744186B2 (ja) * | 1989-03-13 | 1995-05-15 | 株式会社東芝 | 半導体装置の製造方法 |
US5227317A (en) * | 1989-04-21 | 1993-07-13 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit bipolar transistor device |
JPH02280340A (ja) * | 1989-04-21 | 1990-11-16 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
EP0396802B1 (de) * | 1989-05-11 | 1997-10-22 | Siemens Aktiengesellschaft | Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit einem lateralen Bipolartransistor |
IT1231300B (it) * | 1989-07-24 | 1991-11-28 | Sgs Thomson Microelectronics | Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore |
US4902639A (en) * | 1989-08-03 | 1990-02-20 | Motorola, Inc. | Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts |
US4975385A (en) * | 1990-04-06 | 1990-12-04 | Applied Materials, Inc. | Method of constructing lightly doped drain (LDD) integrated circuit structure |
US5311054A (en) * | 1991-03-25 | 1994-05-10 | Harris Corporation | Graded collector for inductive loads |
DE59209271D1 (de) * | 1991-09-23 | 1998-05-14 | Siemens Ag | Verfahren zur Herstellung eines seitlich begrenzten, einkristallinen Gebietes in einem Bipolartransistor |
KR100233832B1 (ko) * | 1996-12-14 | 1999-12-01 | 정선종 | 반도체 소자의 트랜지스터 및 그 제조방법 |
DE102004034572B4 (de) * | 2004-07-17 | 2008-02-28 | Infineon Technologies Ag | Verfahren zum Herstellen einer Struktur auf der Oberfläche eines Substrats |
US8083953B2 (en) | 2007-03-06 | 2011-12-27 | Micron Technology, Inc. | Registered structure formation via the application of directed thermal energy to diblock copolymer films |
US8557128B2 (en) | 2007-03-22 | 2013-10-15 | Micron Technology, Inc. | Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers |
US8097175B2 (en) | 2008-10-28 | 2012-01-17 | Micron Technology, Inc. | Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure |
US8372295B2 (en) | 2007-04-20 | 2013-02-12 | Micron Technology, Inc. | Extensions of self-assembled structures to increased dimensions via a “bootstrap” self-templating method |
US8404124B2 (en) | 2007-06-12 | 2013-03-26 | Micron Technology, Inc. | Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces |
US8080615B2 (en) | 2007-06-19 | 2011-12-20 | Micron Technology, Inc. | Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide |
US8999492B2 (en) | 2008-02-05 | 2015-04-07 | Micron Technology, Inc. | Method to produce nanometer-sized features with directed assembly of block copolymers |
US8426313B2 (en) | 2008-03-21 | 2013-04-23 | Micron Technology, Inc. | Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference |
US8425982B2 (en) | 2008-03-21 | 2013-04-23 | Micron Technology, Inc. | Methods of improving long range order in self-assembly of block copolymer films with ionic liquids |
US8114301B2 (en) | 2008-05-02 | 2012-02-14 | Micron Technology, Inc. | Graphoepitaxial self-assembly of arrays of downward facing half-cylinders |
US8900963B2 (en) | 2011-11-02 | 2014-12-02 | Micron Technology, Inc. | Methods of forming semiconductor device structures, and related structures |
US9087699B2 (en) | 2012-10-05 | 2015-07-21 | Micron Technology, Inc. | Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure |
US9229328B2 (en) | 2013-05-02 | 2016-01-05 | Micron Technology, Inc. | Methods of forming semiconductor device structures, and related semiconductor device structures |
US9177795B2 (en) | 2013-09-27 | 2015-11-03 | Micron Technology, Inc. | Methods of forming nanostructures including metal oxides |
KR102643949B1 (ko) * | 2016-09-26 | 2024-03-05 | 가부시끼가이샤 레조낙 | 수지 조성물, 반도체용 배선층 적층체 및 반도체 장치 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538823B2 (ko) * | 1971-12-22 | 1980-10-07 | ||
US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
US4236294A (en) * | 1979-03-16 | 1980-12-02 | International Business Machines Corporation | High performance bipolar device and method for making same |
US4272308A (en) * | 1979-10-10 | 1981-06-09 | Varshney Ramesh C | Method of forming recessed isolation oxide layers |
US4309812A (en) * | 1980-03-03 | 1982-01-12 | International Business Machines Corporation | Process for fabricating improved bipolar transistor utilizing selective etching |
US4338138A (en) * | 1980-03-03 | 1982-07-06 | International Business Machines Corporation | Process for fabricating a bipolar transistor |
US4378627A (en) * | 1980-07-08 | 1983-04-05 | International Business Machines Corporation | Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes |
US4640721A (en) * | 1984-06-06 | 1987-02-03 | Hitachi, Ltd. | Method of forming bipolar transistors with graft base regions |
EP0170250B1 (en) * | 1984-07-31 | 1990-10-24 | Kabushiki Kaisha Toshiba | Bipolar transistor and method for producing the bipolar transistor |
JPS6146063A (ja) * | 1984-08-10 | 1986-03-06 | Hitachi Ltd | 半導体装置の製造方法 |
US4698316A (en) * | 1985-01-23 | 1987-10-06 | Rca Corporation | Method of depositing uniformly thick selective epitaxial silicon |
US4592792A (en) * | 1985-01-23 | 1986-06-03 | Rca Corporation | Method for forming uniformly thick selective epitaxial silicon |
US4641416A (en) * | 1985-03-04 | 1987-02-10 | Advanced Micro Devices, Inc. | Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter |
US4678537A (en) * | 1985-05-23 | 1987-07-07 | Sony Corporation | Method of manufacturing semiconductor devices |
US4728624A (en) * | 1985-10-31 | 1988-03-01 | International Business Machines Corporation | Selective epitaxial growth structure and isolation |
US4758530A (en) * | 1986-12-08 | 1988-07-19 | Delco Electronics Corporation | Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers |
US4749441A (en) * | 1986-12-11 | 1988-06-07 | General Motors Corporation | Semiconductor mushroom structure fabrication |
US4760036A (en) * | 1987-06-15 | 1988-07-26 | Delco Electronics Corporation | Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation |
US4758531A (en) * | 1987-10-23 | 1988-07-19 | International Business Machines Corporation | Method of making defect free silicon islands using SEG |
-
1987
- 1987-10-20 US US07/111,002 patent/US4818713A/en not_active Expired - Lifetime
-
1988
- 1988-09-27 JP JP63239908A patent/JPH01124261A/ja active Pending
- 1988-10-11 ES ES88309484T patent/ES2047558T3/es not_active Expired - Lifetime
- 1988-10-11 EP EP88309484A patent/EP0313250B1/en not_active Expired - Lifetime
- 1988-10-11 DE DE88309484T patent/DE3886672T2/de not_active Expired - Fee Related
- 1988-10-15 KR KR1019880013487A patent/KR910009033B1/ko not_active IP Right Cessation
- 1988-10-19 CA CA000580655A patent/CA1299770C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0313250A2 (en) | 1989-04-26 |
ES2047558T3 (es) | 1994-03-01 |
DE3886672D1 (de) | 1994-02-10 |
EP0313250A3 (en) | 1989-11-02 |
JPH01124261A (ja) | 1989-05-17 |
DE3886672T2 (de) | 1994-04-28 |
EP0313250B1 (en) | 1993-12-29 |
CA1299770C (en) | 1992-04-28 |
KR910009033B1 (ko) | 1991-10-28 |
US4818713A (en) | 1989-04-04 |
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