CN207338365U - 集成电路 - Google Patents

集成电路 Download PDF

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CN207338365U
CN207338365U CN201720453260.3U CN201720453260U CN207338365U CN 207338365 U CN207338365 U CN 207338365U CN 201720453260 U CN201720453260 U CN 201720453260U CN 207338365 U CN207338365 U CN 207338365U
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A·马扎基
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STMicroelectronics Rousset SAS
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Abstract

一种集成电路包括第一导电类型的半导体衬底以及通过绝缘区域与衬底绝缘的第一导电类型的半导体阱，绝缘区域具有：第一绝缘沟槽，从衬底的第一面延伸到衬底中并且围绕阱；第二导电类型的半导体层，掩埋在阱下方的衬底中；中间绝缘区，被配置为确保第一绝缘沟槽与掩埋半导体层之间的电绝缘连续性，并且包括第二沟槽，第二沟槽具有围绕阱的外围部分，外围部分具有从衬底的第一面延伸同时与第一绝缘沟槽接触的第一部分，第一部分通过位于第一绝缘沟槽与掩埋半导体层之间的第二部分延伸，第二沟槽具有中央部分，中央部分被配置为导电并且被封闭在绝缘护套中，集成电路包括被配置为在中央部分上导电的第一触点以及被配置为在阱上导电的第二触点。

Description

集成电路
技术领域
本实用新型的实施例涉及集成电路，具体地是那些利用三阱型结构的集成电路，因此使得有可能将第一导电类型(例如，P型导电性) 的阱与同样是第一导电类型的另一半导体区(例如，衬底的其余部分) 绝缘，并且具体地是那些在供电电压与地之间具有去耦电容器的集成电路，通过术语“填料盖(Filler Cap)”被本领域技术人员所公知。
背景技术
图1示意性地展示了具有三阱型结构的集成电路IC，使得有可能将此处为P型导电性的阱1与同样是P型导电性的半导体衬底SB的其余部分绝缘。
更确切地，阱1通过具有第一绝缘沟槽2(例如，通过首字母缩略STI(浅沟槽隔离)被本领域技术人员已知的类型)的绝缘区域而与衬底SB绝缘，该第一绝缘沟槽从衬底的第一面FS延伸到衬底中并且围绕阱1。
绝缘区域还具有掩埋在阱1下方的衬底中的N型导电性半导体层 3。
最后，绝缘区包括中间绝缘区以确保第一绝缘沟槽2与掩埋半导体层3之间的电绝缘连续性。
此处，此中间绝缘区具有横向围绕阱1并且在第一绝缘沟槽2与掩埋半导体层3之间延伸的阱4。这个阱4通过注入N型导电性掺杂剂而产生。
这种基于注入阱4的绝缘区域需要在绝缘沟槽2的边缘与阱4的边缘之间维持一定距离，从而防止N掺杂剂通过扩散现象进入P阱的任何溢出风险，其效果将减少P阱的有效尺寸。
然而，这个维度约束呈现出引起阱的表面区域增大的表面成本。
此外还可以使用这些阱以便在此形成连接在供电电压与地之间的去耦电容器。这些去耦电容器包含例如通过绝缘材料(如，氧化硅) 与P阱绝缘的一条或多条多晶硅。然而，发现这种去耦电容器具有不可忽略的漏电流以及在某些情况下可以相对较低的电容值。
实用新型内容
一个实施例提出减少对通过三阱型结构绝缘的半导体阱的表面占用率，同时提出在这个阱中产生具有更高电容值和减少的漏电流的去耦电容器。
一方面提供了一种集成电路，该集成电路包括：第一导电类型(例如，P型导电性)的半导体衬底；以及第一导电类型(例如，P型导电性)的至少一个半导体阱，该至少一个半导体阱通过具有第一绝缘沟槽的绝缘区与该衬底绝缘，该第一绝缘沟槽从衬底的第一面延伸至该衬底中并且围绕该至少一个半导体阱；与第一导电类型相反的第二导电类型(例如，N型导电性)的半导体层，该半导体层掩埋在该阱下方的衬底中；以及中间绝缘区，该中间绝缘区被配置以便确保该第一绝缘沟槽与该掩埋半导体层之间的电绝缘连续性。
该中间绝缘区包括：第二沟槽，该第二沟槽具有围绕该至少一个半导体阱的至少一个外围部分，该外围部分具有从该衬底的该第一面延伸同时与该第一绝缘沟槽接触的第一部分，该第一部分通过位于该第一绝缘沟槽与该掩埋半导体层之间的第二部分延伸。
该第二沟槽具有中央部分，该中央部分被配置以便导电(例如，多晶硅的)并且被封闭在(例如，二氧化硅的)绝缘护套中，并且该集成电路包括：至少一个第一触点，该至少一个第一触点被配置以便在该中央部分上是导电的；以及至少一个第二触点，该至少一个第二触点被配置以便在该至少一个半导体阱上是导电的。
因此，通过其外围部分，第二沟槽有助于半导体阱与衬底的其余部分绝缘。此外，封闭在绝缘护套中的其导电部分使得有可能形成具有半导体阱的去耦电容器。
通过这种第二沟槽实现的半导体阱绝缘使得有可能结合注入阱克服以上提到的表面占有率问题。此外，使用用于去耦电容器的这个沟槽也旨在使得有可能增大这个去耦电容器的电容值，同时限制漏电流。
为了进一步增加去耦电容器的电容值，可以规定第二沟槽具有连接至该外围部分并且延伸到该至少一个半导体阱内部的至少一个附加支路，或者甚至连接至该外围部分并且延伸到该至少一个半导体阱内部的多个并行附加支路。
可能有若干替代性实施例。
因此，第二沟槽的该至少一个外围部分的第一部分可以完全位于第一绝缘沟槽中。换句话说，第二沟槽可以穿过第一绝缘沟槽(例如， STI型的)。
作为变体，第二沟槽的该至少一个外围部分的第一部分可以完全位于阱与第一绝缘沟槽之间。第二沟槽的外围部分的这个第一部分然后有利地邻近第一绝缘沟槽。
第二沟槽的外围部分的第二部分可以与掩埋半导体层接触。
作为变体，这个第二部分的底部可以位于距掩埋半导体层一定距离处，在这种情况下，中间绝缘区具有第二导电类型(例如，N型导电性)的注入区，该注入区位于该第二部分的底部与掩埋半导体层之间。
由于该第二沟槽的深度可以基本上等于该掩埋栅极的深度，因此这个实施例有利地与在集成电路内制造存储器装置相兼容，该存储器装置具有含有非易失性存储器单元的存储器平面和具有掩埋栅极的选择晶体管。
第一导电类型可以是P型，并且第二导电类型可以是N型。
根据本实用新型的实施例的集成电路能够减少对通过三阱型结构绝缘的半导体阱的表面占用率，同时在这个阱中产生具有更高电容值和减少的漏电流的去耦电容器。
附图说明
本实用新型的其他特优点和特征将基于学习完全非限制性实施例的详细描述和附图而变得明显，在附图中：
-图1如已经描述的展示了根据现有技术的三阱型半导体阱的电绝缘示例，以及
-图2至图7示意性地展示了本实用新型的各个实施例。
具体实施方式
在图2和图3(其是图2的平面视图)中，参考IC1指示包含具有第一导电类型(在此为P型导电性)的半导体阱1的集成电路。
如现在将看到的，这个半导体阱1通过具有一定数量的元件的绝缘区域与同样是P型导电性的衬底SB电绝缘。
更确切地，绝缘区域具有例如浅沟槽型(STI：浅沟槽隔离)的第一绝缘沟槽2，围绕半导体阱1并且从第一面或衬底的上面FS延伸到衬底SB中。
绝缘区域还具有掩埋在半导体阱1下方的衬底SB中的第二导电类型(在此为N型导电性)的半导体层，参考号为3。
绝缘区还具有中间绝缘区，以确保第一绝缘沟槽2与掩埋半导体层3之间的电绝缘连续性。
在这个实施例中，中间绝缘区包括第二沟槽4，该第二沟槽具有围绕半导体阱1的外围部分40。
这个外围部分具有从衬底的第一面FS延伸的同时与第一绝缘区域2接触的第一部分410。
邻近第一绝缘沟槽2的这个第一部分410通过第二部分420延伸，该第二部分位于第一绝缘沟槽2与掩埋半导体层3之间。
在这个实施例中，外围部分40的第二部分420的底部位于距掩埋半导体层3一定距离处。
因此，为了确保电绝缘连续性，中间绝缘区也具有N型导电性的注入区5，该注入区位于第二沟槽4的第二部分420的底部与掩埋半导体层3之间。
因此半导体阱1与衬底SB的其余部分完全电绝缘。
此外，第二沟槽4具有封闭在绝缘护套440中的导电中央部分 430。通过非限制性示例的方式，导电中央部分430可以包含多晶硅并且绝缘护套可以包含二氧化硅。
通过非限制性示例的方式，第二沟槽4的中央部分的横截面区域可以约为0.1μm2，而绝缘护套440的厚度可以约为一百埃。
进一步为了其绝缘功能，第二沟槽4形成具有半导体阱1的去耦电容器。这个去耦电容器的第一电极通过第二沟槽4的中央部分430 形成，而去耦电容器的第二电极通过半导体阱1形成。去耦电容器的电介质通过绝缘护套440形成。
同样，还规定集成电路IC具有第二沟槽4的中央部分430上的第一导电触点CT1以及半导体阱1上的第二导电触点CT2。
然后，例如，供电电压Vdd可以施加至第二触点CT2，并且地压可以施加至第一触点CT1，这使得有可能在供电电压与地之间具有去耦电容器。
这个第二沟槽4的外围部分使得有可能具有相应的电容值，该相应的电容值通常是如现有技术的去耦电容器的电容值一半大小的电容值。
此外，具有沟槽的这个结构还使得有可能限制去耦电容器的漏电流。
如刚刚已经看到的，第二沟槽4的底部位于距掩埋半导体层3一定距离处。
这与用于产生存储器装置的方法兼容，该存储器装置的存储器平面PM具有如图4中示意性展示的非易失性存储器单元CEL以及具有掩埋栅极的选择晶体管TSL。
更确切地，每个存储器单元CEL具有在P型半导体阱之中和之上产生的浮置栅极晶体管TGF，该P型半导体阱通过N型半导体层(出于简明目的在此未表示出)与下面的P型衬底隔离开。
常规地，每个浮置栅极晶体管具有例如由多晶硅制成的浮置栅极 GF和控制栅极CG。
每个选择晶体管TSL使得有可能选择一排单元并且是MOS晶体管，其栅极GTSL是掩埋在P型阱中并且通过栅极氧化物OX(通常为二氧化硅)与这个阱电绝缘的栅极。
掩埋栅极GTSL被两个相邻的选择晶体管TSL所共用，它们的两个栅极氧化物OX分别位于这个掩埋栅极的两个侧面上。
此外，如图4中所展示的，使得有可能产生掩埋选择栅极GTSL 的沟槽的深度PR然后有利地与图2中所展示的第二沟槽4的深度PR 相同或基本上相同。
为了更进一步增大去耦电容器的电容值，有可能提供如图5中所展示的实施例，其中，第二沟槽4具有连接至第二沟槽4的外围部分 40并且延伸到半导体阱1内部的至少一个附加支路，在此为多个并行附加支路41。
其他替代性实施例是可能的，这些实施例都展示在图6和图7中。
因此，如图6中所展示的，有可能提供第二沟槽400，该第二沟槽的第二部分的底部不再位于距掩埋半导体层3一定距离处而是与其相接触。
类似地，如图7中所展示的，一旦完成生产，就不提供邻近第一绝缘沟槽2的第二沟槽40，有可能提供穿过第一绝缘沟槽2的第二沟槽4000。换句话说，这个第二沟槽4000的第一部分然后完全位于第一绝缘沟槽2内。
在图7中所展示的示例中，第二沟槽4000与掩埋半导体层3接触。当然，将完全可以想象这个第二沟槽4000的底部位于距这个掩埋半导体层3一定距离处，如图2中所展示的，对其而言，N型导电性的注入区5然后将是必要的。

Claims (9)

1.一种集成电路，其特征在于，所述集成电路包括第一导电类型的半导体衬底以及所述第一导电类型的至少一个半导体阱，所述至少一个半导体阱通过绝缘区域与所述衬底绝缘，所述绝缘区域具有：
-第一绝缘沟槽，所述第一绝缘沟槽从所述衬底的第一面延伸到所述衬底中并且围绕所述至少一个半导体阱，
-第二导电类型的半导体层，所述第二导电类型与所述第一导电类型相反，所述半导体层掩埋在所述阱下方的所述衬底中，以及
-中间绝缘区，所述中间绝缘区被配置以便确保所述第一绝缘沟槽与所述掩埋半导体层之间的电绝缘连续性，
所述中间绝缘区包括第二沟槽，所述第二沟槽具有围绕所述至少一个半导体阱的至少一个外围部分，所述外围部分具有从所述衬底的所述第一面延伸同时与所述第一绝缘沟槽接触的第一部分，所述第一部分通过位于所述第一绝缘沟槽与所述掩埋半导体层之间的第二部分延伸，所述第二沟槽具有中央部分，所述中央部分被配置以便导电并且被封闭在绝缘护套中，所述集成电路包括：至少一个第一触点，所述至少一个第一触点被配置以便在所述中央部分上是导电的；以及至少一个第二触点，所述至少一个第二触点被配置以便在所述至少一个半导体阱上是导电的。
2.根据权利要求1所述的集成电路，其特征在于，所述至少一个外围部分的所述第一部分完全位于所述第一绝缘沟槽中。
3.根据权利要求1所述的集成电路，其特征在于，所述至少一个外围部分的所述第一部分完全位于所述阱与所述第一绝缘沟槽之间。
4.根据权利要求1至3中任一项所述的集成电路，其特征在于，所述第二沟槽具有至少一个附加沟槽，所述至少一个附加沟槽连接至所述外围部分并且延伸到所述至少一个半导体阱内部。
5.根据权利要求4所述的集成电路，其特征在于，所述第二沟槽具有多个并行附加支路，所述多个并行附加支路连接至所述外围部分并且延伸到所述至少一个半导体阱内部。
6.根据权利要求1至3和5中任一项所述的集成电路，其特征在于，所述至少一个外围部分的所述第二部分与所述掩埋半导体层接触。
7.根据权利要求1至3和5中任一项所述的集成电路，其特征在于，所述至少一个外围部分的所述第二部分的底部位于距所述掩埋半导体层一定距离处，并且所述中间绝缘区具有所述第二导电类型的注入区，所述注入区位于所述第二部分的底部与所述掩埋半导体层之间。
8.根据权利要求7所述的集成电路，其特征在于，所述集成电路包括存储器装置，所述存储器装置具有含有非易失性存储器单元的存储器平面和具有掩埋栅极的选择晶体管，所述第二沟槽的深度基本上等于所述掩埋栅极的深度。
9.根据权利要求1至3、5和8中任一项所述的集成电路，其特征在于，所述第一导电类型是P型并且所述第二导电类型是N型。
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