CN103503140A - 绝缘体上硅芯片上的独立电压控制的硅区域 - Google Patents

绝缘体上硅芯片上的独立电压控制的硅区域 Download PDF

Info

Publication number
CN103503140A
CN103503140A CN201280019453.8A CN201280019453A CN103503140A CN 103503140 A CN103503140 A CN 103503140A CN 201280019453 A CN201280019453 A CN 201280019453A CN 103503140 A CN103503140 A CN 103503140A
Authority
CN
China
Prior art keywords
silicon area
independent voltage
semiconductor chip
injection region
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280019453.8A
Other languages
English (en)
Other versions
CN103503140B (zh
Inventor
K.R.埃里克森
P.C.保内
D.P.保尔森
J.E.希茨
G.J.乌尔曼
K.L.威廉斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN103503140A publication Critical patent/CN103503140A/zh
Application granted granted Critical
Publication of CN103503140B publication Critical patent/CN103503140B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Abstract

一种半导体芯片（100）具有独立电压控制的硅区域（110），该独立电压控制的硅区域是用于控制eDRAM沟槽电容器（140）的电容值和叠置在独立电压控制的硅区域（110）上的场效晶体管（130）的阈值电压的电路元件。独立电压控制的硅区域（110）的底部或地板是深注入区（105），该深注入区的掺杂与独立电压控制的硅区域（110）的掺杂相反。独立电压控制的硅区域（110）的顶部或天花板是诸如注入在基板中的埋设的氧化物（103）。独立电压控制的硅区域的侧部是深沟槽隔离（106）。通过接触结构（107）施加独立电压控制的硅区域（110）的电压，该接触结构（107）形成得通过埋设的氧化物（103）。

Description

绝缘体上硅芯片上的独立电压控制的硅区域
技术领域
本发明总体上涉及半导体芯片，具体来讲涉及SOI（绝缘体上硅）半导体芯片上的独立电压控制的硅区域。
发明内容
SOI芯片具有通常为P-掺杂硅的基板，尽管也已经知晓相反掺杂（即N-）的基板。埋设的氧化物（BOX）层可注入以隔离在BOX层之上的电路区域与下面的基板部分。下面的基板部分通常连接到电压源（例如，接地）。在BOX之上，电路区域可包含STI（浅沟槽隔离）区域、用于FET（场效应晶体管）的源极/漏极注入区域、在用于FET的FET栅极结构下的主体区域、接触、和互连FET的配线。
在本发明的实施例中，独立电压控制的硅区域形成为电路元件。用深注入区域形成独立电压控制的硅区域的底部，在基板掺杂P-时，该深注入区域为硼注入，以形成N区域。用深沟槽隔离形成独立电压控制的硅区域的侧部，因此在所有侧部（例如，如果独立电压控制的硅区域是正方形或矩形，则为四侧）上绝缘独立电压控制的硅区域。埋设的氧化物区域（BOX）形成独立电压控制的硅区域的顶表面，因此完成独立电压控制的硅区域的电隔离。通过BOX并且通过任何的STI或者BOX之上的硅形成电接触，该电接触适于将独立电压控制的硅区域连接至电压或者芯片上的逻辑信号。
附图说明
图1示出了半导体芯片的一部分的侧视图，示出了逻辑区域和eDRAM区域，该eDRAM区域包括独立电压控制的硅区域。
图2A-2E示出了在产生独立电压控制的硅区域中的关键工艺步骤。
图3示出了具有两个独立电压控制区域的半导体芯片的截面图，其每一个独立电压控制区域包含eDRAM单元。
具体实施方式
在本发明实施例的下文详细描述中参考附图，这些附图形成详细描述的一部分，并且其中通过实施本发明的具体实施例的图示说明进行示出。应理解，在不脱离本发明范围的情况下可利用其它的实施例，且可进行结构的变化。
本发明的实施例提供了产生独立电压控制的硅区域，所述独立电压控制的硅区域是电路元件，通常用于提供硅芯片上的嵌入动态随机存取存储器（embedded dynamic random access memory，eDRAM）的泄漏/性能特征的选择性控制，并且提供其它电路的阈值控制。
图1的绝缘体上硅（SOI）半导体芯片100示出为具有逻辑区域150和eDRAM区域151。
逻辑区域150包括一部分P-硅101，其通常接地。埋设的氧化物（BOX）103提供了逻辑FET（场效晶体管）120下的电绝缘体。逻辑FET120包括源极/漏极注入区域121、P-主体区域125、栅极电介质126、源极/漏极接触122、栅极侧壁隔板123和栅极124，栅极可电连接到逻辑信号或电压源。具有P-主体和N+源极/漏极区域的逻辑FET120是NFET（N-沟道场效晶体管）。通常，还采用已知的技术在逻辑区域150中形成PFET（P-沟道场效晶体管），以形成N-主体区域和P+源极/漏极区域。逻辑区域150中的NFET和PFET构造为制作逻辑栅极（NAND、NOR、XOR、锁存器和寄存器等）。
eDRAM区域151包括旁栅NFET130，以在耦接到栅极134的字线的控制下将连接到源极/漏极注入区域131的位线连接到深沟槽电容器140。旁栅NFET130包括栅极134、栅极电介质136、源极/漏极注入区域131和132、主体区域135、栅极电介质136、侧壁隔板133以及外延生长137和138。深沟槽电容器140包括深沟槽中的导体141。导体可为钨、掺杂的多晶硅或者设置在深沟槽中的其它合适的导电材料。电介质材料142使导体141与P-硅101和P-硅109隔离。电介质材料142例如可为HfO2或SiO2或者其它适当的电介质材料。外延生长137耦接电介质材料142的上部之上的相邻源极/漏极区域132以形成导体141和相邻源极/漏极区域132之间的电接触。
eDRAM区域151还包括深N注入区105，其形成独立电压控制的硅区域110的“地板”或底部，在图1中由点线表示。N注入区105可为足够高能量的深硼注入，以在半导体芯片100小于深沟槽隔离106但是深到足以包括位于BOX103下的深沟槽电容器140的大部分或全部的深度上形成N注入区105，如图1所示。例如，深沟槽电容器140的50%以上应面对P-Si109。应注意，深沟槽电容器140不需要延伸到N注入区105。4MeV（百万电子伏特）硼注入在约20um具有峰值剂量；2MeV硼注入在约10um具有峰值剂量。
独立电压控制的硅区域110的“天花板”或者顶部是BOX103的一部分。独立电压控制的硅区域110的侧部由深沟槽隔离106形成，这在图2E的俯视图中清楚可见。N注入区105必须足够宽，以保证P-Si109不与P-Si101电接触。
蚀刻通过STI（浅沟槽隔离）102且通过BOX103，并且填充诸如钨或者掺杂的多晶硅之类的导体，以形成电连接到P-Si109的电连接，形成接触结构107。接触结构107可具有接触108以连接到电压（电压源或逻辑信号）。除了接触结构107外，如上所述，P-Si109完全与P-Si101和在BOX103之上的电路（例如，旁栅NFET130）隔离。接触结构107将施加在接触108上的电压传输到P-Si109，因此在独立电压控制的硅区域110上提供电压。
在eDRAM区域151中示出了单个的NFET旁栅130和相关的深沟槽电容器140，然而，应理解，大量的，大概一百万或更多的NFET旁栅130和相关的电容器140通常设置在eDRAM区域151中。类似地，为了简单起见，在逻辑区域150中示出了单一逻辑FET120。然而，在现代的半导体芯片100中，可构造一百万或更多的FET120。
还应理解，尽管示出NFET旁栅130为对深沟槽电容器140进行充电或放电的开关，并且在读取时导致深沟槽电容器140上的充电以影响位线电压，但是在BOX103之上具有已知处理的PFET也可用作旁栅。
现在参见图2A-2E，示出了产生独立电压控制的硅区域110的一组关键工艺步骤。在图2A中，半导体芯片100通过掩模302接受高能硼注入301，从而在由注入能量和半导体结构决定的深度上形成N注入区105。如上所述，4MeV硼注入将在半导体芯片100的顶表面下约20um处形成N注入区105。
图2B示出了施加到半导体芯片100上的传统氧注入区303，以便在由氧注入区303的能量决定的深度处形成BOX103。
图2C示出了深沟槽隔离106的形成，深沟槽隔离106至少延伸到N注入区105且优选略微在其下。深沟槽隔离可采用传统的工艺形成，例如用于形成eDRAM电容器的工艺，但被拉长以形成独立电压控制的硅区域110的侧部。可替换地，深沟槽隔离106可利用深沟槽电容器结构，如处于审查中且已转让给本受让人的申请US2011/0018094所教导。在构造深沟槽隔离106、BOX103和N注入区105后，P-Si109完全电隔离。P-Si109仅是P-Si101的电隔离部分，而不受到单独的注入。
图2D和2E分别示出了半导体芯片100的一部分的截面图（通过AA）和俯视图，半导体芯片100的该部分通常位于构造独立电压控制的硅区域110的区域中。浅沟槽隔离（STI）102形成在硅111中（即P-Si101在BOX103之上的部分），如具有向上和向左阴影线的细阴影线所示。接触结构107通过氧化蚀刻通过STI102和BOX103而形成。接触108可形成在接触结构107的顶部。图2E示出了半导体芯片100的该部分的俯视图。以传统的方式，在蚀刻、加衬和填充深沟槽电容器140后形成源极/漏极注入区域131、132、栅极电介质136、隔板133、外延生长137和138，用传统的方法在硅111中形成NFET旁栅130（图1）。
图3示出了两个独立电压控制的硅区域110，参见110A（左边的例子）和110B（右边的例子），为了简便示出的目的，110A和110B共享公用深沟槽隔离106在它们之间的部分。关键参考项目具有“A”后缀（例如，130A，用于左手的NFET旁栅130）和“B”后缀，“A”后缀用于与独立电压控制的硅区域110A相关的参考项目，“B”后缀用于与独立电压控制的硅区域110B相关的参考项目。
在图3中，连接到具有接触108A的接触结构107A的VA可具有0.0伏特的电压，因此使P-Si109A为0.0伏特。连接到具有接触108B的接触结构107B的VB可具有+5.0伏特的电压，因此使P-Si109B为5.0伏特。在深沟槽电容器140（140A、140B）周围的电荷耗尽区域144（144A、144B）的宽度取决于导体141（141A、141B）上的电压和施加到P-Si109（109A、109B）的电压之间的电位差。首先，电容器C（CA、CB）的电容器板的间隔对应于电荷耗尽区域的宽度。应理解，深沟槽电容器140示意性地示为电容器C。深沟槽电容器140A示意性地示为电容器CA；深沟槽电容器140B示意性地示为电容器CB。如果电荷耗尽区域144（图3中的144A、144B）较宽，则电容器板变大，并且电容变小。采用假定的VA、VB电压，独立电压控制的硅区域110A在深沟槽电容器140A周围的电荷耗尽区域144A宽于独立电压控制的硅区域110B在深沟槽电容器140B周围的电荷耗尽区域144B的宽度。因此，示出CA相比CB电容器板间隔更大。CA比CB具有更小的电容值。
施加在P-Si109A、109B上的电压（VA、VB）的另一个效果是电场302（302A、302B）通过BOX103且影响上面FET的阈值电压，例如NFET旁栅130A、130B。如所示，采用VA、VB的假设值，电场302A小于电场302B。
根据P-Si109A中eDRAM单元的控制特性，NFET旁栅130A的阈值电压将高于NFET旁栅130B的阈值电压，因此相对于NFET旁栅130B显著地降低NFET旁栅130A的泄漏。如前所述，CA的电容值小于CB，但是通过NFET旁栅130A来自CA的泄漏相对于通过NFET旁栅130B来自CB的泄漏的显著减小将导致深沟槽电容器140A（即CA）中的数据保持力强于深沟槽电容器140B（即CB）中的数据保持力，即使CB是较大电容。因此，通过控制施加到独立电压控制的硅区域110中相关P-Si109上的电压，可以控制eDRAMs更大或更小的泄漏。在eDRAM的低功率模式中非常期望这种泄漏控制能力。
然而，对于诸如读取速度之类的性能，独立电压控制的硅区域110B中的eDRAM相对于独立电压控制的硅区域110A中的eDRAM更优秀（更快）。具有较低阈值电压的NFET旁栅130B将具有更强的传输能力。再者，CB的较大电容值比与独立电压控制的硅区域110A相关的较低电容值和低导电结构更快下拉位线且更快通过NFET旁栅130B。因此，可通过控制独立电压控制的硅区域110中的相关P-Si109，可控制eDRAMs运行得更快（或更慢）。
将电场302和电容器C应用于具有逻辑区域150以及eDRAM区域151的图1，清楚可见，因为逻辑FET120构造在接地的P-Si101之上，而不是构造在P-Si109之上，施加到P-Si109的电压不影响逻辑FET120中的阈值电压。当然正确的是P-Si101可不接地而是连接到电压源，从而影响任何位于偏置的P-Si101上的FET的阈值电压，不过，这样做会以相反的方式影响PFET和NFET（例如，NFET的强度增加时，PFET的强度会下降），因此不希望这样做。本发明的实施例在半导体芯片上提供一个或多个独立电压控制的硅区域。由于eDRAM区域151通常只包含NFET（即NFET旁栅130），eDRAM应用中的PFET/NFET的相对强度没有问题。
工业实用性
本发明在高性能半导体场效晶体管（FET）器件的设计和制造上具有工业应用性，这些高效能半导体场效应晶体管结合在可应用于各种电子和电气设备上的集成电路芯片中。

Claims (7)

1.一种半导体芯片（100），包括：
独立电压控制的硅区域（110），还包括：
深注入区（105），该深注入区（105）的掺杂与该半导体芯片（100）的基板掺杂相反，该深注入区（105）形成该独立电压控制的硅区域（110）的底部；
埋设的氧化物（103），形成该独立电压控制的硅区域（110）的顶部；
深沟槽隔离（106），形成该独立电压控制的硅区域（110）的侧部；以及
接触结构（107），由穿过该埋设的氧化物（103）形成的导电材料制成，以对该独立电压控制的硅区域（110）提供电接触。
2.如权利要求1所述的半导体芯片（100），其中，该半导体芯片的基板掺杂为P-掺杂，掺杂与该半导体芯片的基板掺杂相反的该深注入区（105）是2MeV至4MeV能量的硼深注入区。
3.如权利要求1所述的半导体芯片（100），其中该接触结构（107）将该独立电压控制的硅区域（110）耦接至电压源。
4.如权利要求1所述的半导体芯片（100），其中该接触结构（107）将该独立电压控制的硅区域耦接至逻辑信号。
5.一种在半导体芯片（100）中产生独立电压控制的硅区域（110）的方法，包括：
形成深注入区（105），使该深注入区的掺杂与该半导体芯片（100）的基板的掺杂相反；
在该半导体芯片（100）中形成埋设的氧化物（BOX）（103），该深注入区（105）全部在该BOX（103）下；
在该基板中形成深沟槽隔离（106），该深沟槽隔离（106）的深度至少与该深注入区（105）同样深，并且该深沟槽隔离与该深注入区（105）和该BOX（103）相交；
该深注入区（105）形成该独立电压控制的硅区域（110）的底部；
该BOX（103）形成该独立电压控制的硅区域（110）的顶部；
该深沟槽隔离（106）形成该独立电压控制的硅区域（110）的壁部，从而使该独立电压控制的硅区域（100）与该基板的其余部分完全隔离；以及
形成接触结构（107），以将该独立电压控制的硅区域（110）电连接至接触（108）。
6.如权利要求5所述的方法，还包括将该接触（108）连接至电压源。
7.如权利要求5所述的方法，还包括将该接触（108）连接至逻辑信号。
CN201280019453.8A 2011-04-21 2012-03-14 绝缘体上硅芯片上的独立电压控制的硅区域 Expired - Fee Related CN103503140B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/091,275 US8816470B2 (en) 2011-04-21 2011-04-21 Independently voltage controlled volume of silicon on a silicon on insulator chip
US13/091,275 2011-04-21
PCT/US2012/028987 WO2012145097A2 (en) 2011-04-21 2012-03-14 Independently voltage controlled volume of silicon on a silicon on insulator chip

Publications (2)

Publication Number Publication Date
CN103503140A true CN103503140A (zh) 2014-01-08
CN103503140B CN103503140B (zh) 2016-05-18

Family

ID=47020650

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280019453.8A Expired - Fee Related CN103503140B (zh) 2011-04-21 2012-03-14 绝缘体上硅芯片上的独立电压控制的硅区域

Country Status (5)

Country Link
US (1) US8816470B2 (zh)
CN (1) CN103503140B (zh)
DE (1) DE112012001195B4 (zh)
GB (1) GB2502480B (zh)
WO (1) WO2012145097A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489609A (zh) * 2014-10-03 2016-04-13 瑞萨电子株式会社 半导体器件

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9716036B2 (en) 2015-06-08 2017-07-25 Globalfoundries Inc. Electronic device including moat power metallization in trench
TWI681502B (zh) * 2015-09-21 2020-01-01 美商格羅方德半導體公司 接觸ｓｏｉ基板
FR3057393A1 (fr) 2016-10-11 2018-04-13 Stmicroelectronics (Rousset) Sas Circuit integre avec condensateur de decouplage dans une structure de type triple caisson
US9929148B1 (en) * 2017-02-22 2018-03-27 Globalfoundries Inc. Semiconductor device including buried capacitive structures and a method of forming the same
FR3070535A1 (fr) 2017-08-28 2019-03-01 Stmicroelectronics (Crolles 2) Sas Circuit integre avec element capacitif a structure verticale, et son procede de fabrication
FR3070534A1 (fr) 2017-08-28 2019-03-01 Stmicroelectronics (Rousset) Sas Procede de fabrication d'elements capacitifs dans des tranchees
FR3076660B1 (fr) 2018-01-09 2020-02-07 Stmicroelectronics (Rousset) Sas Dispositif integre de cellule capacitive de remplissage et procede de fabrication correspondant
US11621222B2 (en) 2018-01-09 2023-04-04 Stmicroelectronics (Rousset) Sas Integrated filler capacitor cell device and corresponding manufacturing method
US11004785B2 (en) 2019-08-21 2021-05-11 Stmicroelectronics (Rousset) Sas Co-integrated vertically structured capacitive element and fabrication process
US11183452B1 (en) 2020-08-12 2021-11-23 Infineon Technologies Austria Ag Transfering informations across a high voltage gap using capacitive coupling with DTI integrated in silicon technology

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010026990A1 (en) * 2000-01-05 2001-10-04 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
US20030094654A1 (en) * 2001-11-21 2003-05-22 International Business Machines Corporation Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
US20040248363A1 (en) * 2003-06-09 2004-12-09 International Business Machines Corporation Soi trench capacitor cell incorporating a low-leakage floating body array transistor

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6330648B1 (en) 1996-05-28 2001-12-11 Mark L. Wambach Computer memory with anti-virus and anti-overwrite protection apparatus
US6260172B1 (en) 1997-09-05 2001-07-10 Nippon Steel Corporation Semiconductor device with logic rewriting and security protection function
US6087690A (en) 1998-10-13 2000-07-11 Worldwide Semiconductor Manufacturing Corporation Single polysilicon DRAM cell with current gain
JP3437132B2 (ja) 1999-09-14 2003-08-18 シャープ株式会社 半導体装置
JP3526446B2 (ja) 2000-06-09 2004-05-17 株式会社東芝 フューズプログラム回路
US6429477B1 (en) 2000-10-31 2002-08-06 International Business Machines Corporation Shared body and diffusion contact structure and method for fabricating same
US6498057B1 (en) * 2002-03-07 2002-12-24 International Business Machines Corporation Method for implementing SOI transistor source connections using buried dual rail distribution
JP2003296680A (ja) 2002-03-29 2003-10-17 Hitachi Ltd データ処理装置
US7129142B2 (en) * 2002-06-11 2006-10-31 Advanced Micro Devices, Inc. Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same
US7825488B2 (en) * 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
JP4497874B2 (ja) 2002-12-13 2010-07-07 株式会社ルネサステクノロジ 半導体集積回路及びｉｃカード
US6821857B1 (en) 2003-06-10 2004-11-23 International Business Machines Corporation High on-current device for high performance embedded DRAM (eDRAM) and method of forming the same
JP3781740B2 (ja) 2003-07-07 2006-05-31 沖電気工業株式会社 半導体集積回路、半導体装置および半導体装置の製造方法
JP4221274B2 (ja) 2003-10-31 2009-02-12 株式会社東芝 半導体集積回路および電源電圧・基板バイアス制御回路
JP4106033B2 (ja) 2004-02-04 2008-06-25 株式会社ルネサステクノロジ 半導体集積回路装置
US7129745B2 (en) 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
US20060175659A1 (en) 2005-02-07 2006-08-10 International Business Machines Corporation A cmos structure for body ties in ultra-thin soi (utsoi) substrates
US7394708B1 (en) 2005-03-18 2008-07-01 Xilinx, Inc. Adjustable global tap voltage to improve memory cell yield
US9058300B2 (en) 2005-03-30 2015-06-16 Unity Semiconductor Corporation Integrated circuits and methods to control access to multiple layers of memory
US7129138B1 (en) 2005-04-14 2006-10-31 International Business Machines Corporation Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
US7605429B2 (en) 2005-04-15 2009-10-20 International Business Machines Corporation Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
US7352029B2 (en) 2005-04-27 2008-04-01 International Business Machines Corporation Electronically scannable multiplexing device
JP2007103863A (ja) 2005-10-07 2007-04-19 Nec Electronics Corp 半導体デバイス
US7655973B2 (en) 2005-10-31 2010-02-02 Micron Technology, Inc. Recessed channel negative differential resistance-based memory cell
US7479418B2 (en) 2006-01-11 2009-01-20 International Business Machines Corporation Methods of applying substrate bias to SOI CMOS circuits
WO2008084017A1 (fr) 2007-01-05 2008-07-17 Proton World International N.V. Limitation d'acces a une ressource d'un circuit electronique
US7675317B2 (en) 2007-09-14 2010-03-09 Altera Corporation Integrated circuits with adjustable body bias and power supply circuitry
US7985633B2 (en) 2007-10-30 2011-07-26 International Business Machines Corporation Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
US7939863B2 (en) 2008-08-07 2011-05-10 Texas Instruments Incorporated Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
US8594333B2 (en) 2008-09-05 2013-11-26 Vixs Systems, Inc Secure key access with one-time programmable memory and applications thereof
US7764531B2 (en) 2008-09-18 2010-07-27 International Business Machines Corporation Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor
US8021941B2 (en) 2009-07-21 2011-09-20 International Business Machines Corporation Bias-controlled deep trench substrate noise isolation integrated circuit device structures
US8525245B2 (en) * 2011-04-21 2013-09-03 International Business Machines Corporation eDRAM having dynamic retention and performance tradeoff

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010026990A1 (en) * 2000-01-05 2001-10-04 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
US20030094654A1 (en) * 2001-11-21 2003-05-22 International Business Machines Corporation Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
US20040248363A1 (en) * 2003-06-09 2004-12-09 International Business Machines Corporation Soi trench capacitor cell incorporating a low-leakage floating body array transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEAMEN: "《Semiconductor Physics and Devices》", 31 December 2003 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489609A (zh) * 2014-10-03 2016-04-13 瑞萨电子株式会社 半导体器件

Also Published As

Publication number Publication date
US8816470B2 (en) 2014-08-26
DE112012001195B4 (de) 2021-01-28
DE112012001195T5 (de) 2013-12-12
GB201315408D0 (en) 2013-10-16
GB2502480B (en) 2014-04-30
WO2012145097A2 (en) 2012-10-26
US20120267752A1 (en) 2012-10-25
WO2012145097A3 (en) 2012-12-27
GB2502480A (en) 2013-11-27
CN103503140B (zh) 2016-05-18

Similar Documents

Publication Publication Date Title
CN103503140B (zh) 绝缘体上硅芯片上的独立电压控制的硅区域
US8525245B2 (en) eDRAM having dynamic retention and performance tradeoff
US5801080A (en) Method of manufacturing semiconductor substrate having total and partial dielectric isolation
KR100325559B1 (ko) 고전압트랜지스터
CN100505319C (zh) 栅控二极管及其形成方法
KR100250346B1 (ko) 필드시일드분리구조의 반도체장치 및 그 제조방법
CN102804376B (zh) 充电保护装置
KR20100015485A (ko) Ｓｏｉ 트랜지스터들을 위한 무선 주파수 분리
US9337302B2 (en) On-SOI integrated circuit comprising a subjacent protection transistor
US9165908B2 (en) On-SOI integrated circuit comprising a triac for protection against electrostatic discharges
US10256340B2 (en) High-voltage semiconductor device and method for manufacturing the same
CN103022131A (zh) 半导体装置
KR100839706B1 (ko) 마이크로일렉트로닉 디바이스와 그 제조 방법
WO2005031876A1 (en) Lateral thin-film soi device having a field plate with isolated metallic regions
US10651184B2 (en) Integrated circuit with decoupling capacitor in a structure of the triple well type
US9379028B2 (en) SOI CMOS structure having programmable floating backplate
KR20170055031A (ko) 터널링 전계효과 트랜지스터를 이용한 1t 디램 셀 소자와 그 제조방법 및 이를 이용한 메모리 어레이
US8018003B2 (en) Leakage power reduction in CMOS circuits
US9653459B2 (en) MOSFET having source region formed in a double wells region
CN103515385A (zh) 半导体装置
KR20070069195A (ko) 금속-산화물-반도체 디바이스 및 그 제조 방법
US20100052026A1 (en) Deep trench capacitor for soi cmos devices for soft error immunity
US20100052053A1 (en) Soi body contact using e-dram technology
KR102054059B1 (ko) Soi 기판 상에 형성된 반도체 소자
CN214898445U (zh) 集成电路

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171116

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171116

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160518

Termination date: 20190314

CF01 Termination of patent right due to non-payment of annual fee