CN1983612A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1983612A
CN1983612A CNA2006101667094A CN200610166709A CN1983612A CN 1983612 A CN1983612 A CN 1983612A CN A2006101667094 A CNA2006101667094 A CN A2006101667094A CN 200610166709 A CN200610166709 A CN 200610166709A CN 1983612 A CN1983612 A CN 1983612A
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semiconductor substrate
receiving element
light receiving
semiconductor device
back side
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CN1983612B (zh
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野间崇
冈田和央
石部真三
北川胜彦
森田佑一
大塚茂树
山田纮士
大久保登
篠木裕之
沖川满
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置,在半导体基板(2)的表面上形成有光接收元件(1)(例如CCD、红外线传感器、CMOS传感器、照度传感器等光接收元件)。半导体基板(2)的背面配置多个球状的导电端子(11)。各个导电端子(11)经由配线层(9)而与半导体基板(2)的表面的焊盘电极(4)电气连接。在此,配线层(9)和导电端子(11)在所述半导体基板(2)的背面上、在垂直方向上看时除与光接收元件(1)的形成区域重叠的区域以外的区域上,在与所述光接收元件(1)的形成区域重叠的区域上不配置配线层(9)、导电端子(11)。从而能够解决输出图像上映入形成在半导体基板的背面上的配线图案这样的问题。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置,特别是涉及具有光接收元件的芯片尺寸封装型的半导体装置。
技术背景
近年,作为新的封装技术CSP(Chip Size Package:芯片尺寸封装)倍受瞩目。CSP是指与半导体芯片的外形尺寸具有大致相同尺寸的外形尺寸的小型封装。以往,作为CSP的一种众所周知BGA(Ball Grid Array:球栅阵列)型的半导体装置。该BGA型半导体装置在封装的一主面上排列多个由焊锡等金属部件构成球形导电端子,与搭载在封装的其他面上的半导体芯片电气连接。
并且,该BGA型半导体装置装入电子设备中时,通过将各导电端子安装在印刷基板上的配线图案上,从而电气连接半导体芯片和印刷基板上搭载的外部电路。
这样的BGA型电子装置与具有向侧部突出的引脚的SOP(SmallOutline Package:小型封装)或QFP(Quad Flat Package:四方平面封装)等其他的CSP型半导体装置相比,能够设计多个导电端子,而且具有能够实现小型化的优点,所以被广泛应用。
图6(a)是表示具有光接收元件的以往的BGA型半导体装置的概略结构的剖面图。硅(Si)等构成的半导体基板100的表面上设有CCD(ChargeCoupled Device:电荷耦合器件)型图像传感器、CMOS型图像传感器等光接收元件101,另外,经由第一绝缘膜103形成焊盘电极102。另外,在半导体基板100的表面上经由环氧树脂等构成的树脂层105连接着例如玻璃、石英等透光性基板104。另外,在半导体基板100的侧面和背面形成由硅氧化膜或硅氮化膜等构成的第二绝缘膜106。
另外,在第二绝缘膜106上形成从半导体基板100的表面沿侧面到背面的与焊盘电极102电气连接的配线层107。另外,覆盖第二绝缘膜106和配线层107形成抗焊剂等构成的保护层108。在配线层107上的保护层108的规定区域上形成开口部,并形成通过该开口部与配线层107电气连接的球状导电端子109。
上述技术记载于例如以下的专利文献中。
专利文献1:特表2002-512436号公报
但是,在上述的以往的BGA型的半导体装置中,使用红外线的情况下,如图6(a)的箭头所示,通过透过性基板104的红外线还会通过半导体基板100,达到半导体基板100的背面形成的配线层107上。并且,该红外线由配线层107反射而朝向上方(光接收元件101侧),光接收元件101接收到该反射光,结果导致图6(b)所示那样地,导电端子109和配线层107的图案111映入输出图像110上的问题。
发明内容
本发明是鉴于上述问题而研发的,其主要特征如下:即,本发明的半导体装置具有:半导体基板,其表面形成有光接收元件;透光性基板,其在所述光接收元件的上方与所述半导体基板粘合;配线层,其形成在半导体基板的背面;保护层,其覆盖配线层,其中,所述配线层形成在半导体基板的背面上、除与光接收元件的形成区域重叠的区域以外的区域上。
另外,本发明的半导体装置的所述保护层中混合有红外线吸收材料。
本发明的半导体装置的制造方法的主要特征如下,即本发明的半导体装置的制造方法,具有如下工序:准备在表面形成有光接收元件以及焊盘电极的半导体基板;在所述半导体基板的表面上粘合透光性基板;在所述半导体基板的背面上、除与所述光接收元件的形成区域重叠的区域以外的区域上形成与所述焊盘电极电气连接的配线层;形成覆盖配线层的保护层。
另外,本发明的半导体装置的制造方法的形成所述保护层的工序中,在所述保护层中混合红外线吸收材料。
根据本发明,不需要进行复杂的制造工序,就能够防止形成在半导体基板的背面上的导电端子和配线层的图案映入输出图像中。
附图说明
图1(a)、(b)是说明本发明的第一实施方式的半导体装置及其制造方法的平面图和断面图。
图2(a)~(c)是说明本发明的第一实施方式的半导体装置及其制造方法的剖面图。
图3(a)~(c)是说明本发明的第一实施方式的半导体装置及其制造方法的剖面图。
图4(a)、(b)是说明本发明的第二实施方式的半导体装置及其制造方法的平面图和剖面图。
图5(a)、(b)是说明本发明的半导体装置及其制造方法的平面图和剖面图。
图6(a)、(b)是说明以往的半导体装置的剖面图和输出图像图。
附图标记的说明
1光接收元件;2半导体基板;3第一绝缘膜;4焊盘电极;5树脂层;6透光性基板;7开口部;8、8a第二绝缘膜;9配线层;10保护层;11导电端子;20反射层;21贯通电极;22配线层;23势垒层;50虚电极;100半导体基板;101光接收元件;102焊盘电极;103第一绝缘膜;104玻璃基板;105树脂层;106第二绝缘膜;107配线层;108保护层;109导电端子;110输出图像;111图案;150半导体装置;200半导体装置;DL划线。
具体实施方式
下面参照附图说明本发明的第一实施方式。图1(a)是本发明的第一实施方式的半导体装置150从背面看的概略平面图。图1(b)是图1(a)的X-X线剖面图。另外,图1(a)中,从方便上考虑将保护层10和焊盘电极4等构成上的一部分省略而进行表示。
该半导体装置150的半导体基板2的表面上形成有能检测大约700nm~2500nm波长的红外线的光接收元件1(例如CCD传感器、CMOS传感器、照度传感器等元件)。另外,半导体基板2的背面上配置多个球状的导电端子11,各个导电端子11经由配线层9而与形成在半导体基板2的表面上的焊盘电极4电气连接。
本实施方式中,在半导体基板2的背面、从垂直方向(图1(a)中相对于纸面垂直的方向)看时除与光接收元件1的形成区域重叠的区域外的区域上形成配线层9和导电端子11,在与光接收元件1的形成区域重叠的区域不配置配线层9和导电端子11。
另外,这样的结构下,还要考虑到:从透光性基板6经由半导体基板2向该半导体基板2的背面的方向上入射的红外线、从半导体基板2的背面侧入射的红外线由抗焊剂等保护层10、半导体装置150的底部(与其他部件的接触面)等而引起乱反射,光接收元件1受到该反射光,结果会产生输出图像模糊等坏影响。
因此,从进一步提高可靠性的观点出发,优选地,在覆盖半导体基板2的背面的保护层10上添加例如黑色颜料等红外线吸收剂。根据该结构,达到保护层10的红外线全部被吸收,或者即使没有被全部吸收也仅反射极少的红外线,所以乱反射的影响极小。另外,同样从防止乱反射的影响的观点出发,可以与保护层10分体地,在与光接收元件1的形成区域重叠的区域设置具有同样的红外线吸收效果的红外线吸收层。另外,在保护层10上添加的红外线吸收剂或红外线吸收剂层优选具有吸收大约700nm~2500nm波长的红外线的性质。
另外,采用这样在与光接收元件1的形成区域重叠的区域不配置配线层9和导电端子11的结构,则由光接收元件1的形成区域的大小和配置等,使多个导电端子11集中在背面的规定区域,结果,半导体装置150向印刷基板等模块上安装时其平衡变差,不能最适地进行安装,因此,根据需要通过在半导体基板2的背面设置虚电极50,从而能够改善安装时的力得以均等分布。
接着,说明本发明的第一实施方式的半导体装置150的制造方法。图2~图3分别是图1(a)的X-X线剖面图,安装制造工序顺序表示。
首先,如图2(a)所示,准备在表面形成光接收元件1的硅(Si)等构成的半导体基板2。然后,在半导体基板2的表面形成例如2μm的膜厚的第一绝缘膜3(例如通过热氧化法或CVD法等形成的硅氧化膜)。
其次,通过溅射法或镀敷法、其他成膜方法形成铝(Al)、铜(Cu)等金属层,之后未图示的光致抗蚀剂层作为掩模对该金属层进行蚀刻,在第一绝缘膜3上形成例如1μm膜厚的焊盘电极4。焊盘电极4是与光接收元件1或其周边元件电气连接的外部连接用电极。然后,在上述半导体基板2的表面形成覆盖焊盘电极4的一部分的未图示的钝化膜(例如由CVD法形成的硅氮化膜)。
接着,对半导体基板2的背面进行后部研磨(back grind),将半导体基板2的厚度薄化到例如100μm左右。另外,最终制品的用途、规格、准备的半导体基板2的当初厚度都有可能使得没有必要进行该研削加工。
接着,如图2(b)所示,从半导体基板2的背面侧有选择地对与焊盘电极4对应的半导体基板2的位置进行蚀刻,使包括焊盘电极4的一部分的第一绝缘膜3露出。以下,以该露出部分为开口部7。另外,本实施方式中,该开口部7是从半导体基板2的背面侧向背面侧其口径越来越窄的缩径形状。另外,未图示,但是也可以以半导体基板2的侧面与透光性基板6的主面垂直的方式将开口部7蚀刻成条形。
接着,如图2(c)所示,在包括开口部7内的半导体基板2的侧面和背面上形成第二绝缘膜8。该第二绝缘膜是例如由等离子体CVD法等形成的硅氧化膜或硅氮化膜。
接着,如图3(a)所示,以未图示的光致抗蚀剂为掩模,对第一绝缘膜3和第二绝缘膜8进行选择性蚀刻。通过该蚀刻,除去从焊盘电极4的一部分上到划线DL的区域上形成的第一绝缘膜3和第二绝缘膜8,在开口部7的底部露出焊盘电极4的一部分。
接着,如图3(b)所示,通过溅射法或镀敷法、其他成膜方法来形成作为配线层9的铝(Al)或铜(Cu)等金属层。之后,以未图示的光致抗蚀剂层为掩模进行蚀刻,在焊盘电极4的一部分上以及第二绝缘膜8上形成例如1μm膜厚的配线层9。
接着,如图3(c)所示,含有配线层9的半导体基板2的背面上形成由抗焊剂这样的保护材料构成的保护层10。然后,如图3(c)所示,使保护层10的规定区域开口,在从该开口露出的上述配线层9上形成镍或金等构成的电极连接层(未图示),在其上形成由焊锡(ハンだ)、铝或金等构成的球状的导电端子11。另外,上述保护层10是负型保护材料的情况下,被光照射了的区域作为保护层10保留,未被光照射的区域的保护层10被除去,形成上述开口。
这样,可形成从半导体基板2的表面的焊盘电极4沿半导体基板2的侧壁到形成于半导体基板2的背面的导电端子11的配线。
另外,如已经叙述的那样,根据需要也可以与导电端子11以同一工序形成虚电极50。具体地,使成为虚电极50的保护层10的规定区域开口,在该开口上形成由焊锡(ハンだ)、铝或金或镍等构成的球状的虚电极50。
然后,沿作为多个半导体装置的边界即划线DL进行划线分割,而切断分离成各个半导体装置150。
通过以上的工序,完成具有光接收元件1的芯片尺寸封装型的半导体装置。
根据本发明的第一实施方式,由于在半导体基板2的背面中与光接收元件1的形成区域重叠的区域上未形成配线层9和导电端子11,所以作为以往的问题即配线层9和导电端子11的图案映入输出图像的情况能够得以可靠防止。另外,通过配线层9和导电端子11的配置的变更能够得到相应的效果,从而与以往的制造方法相比不会增加制造工序数目。另外,通过在保护层上混合红外线吸收材料,或另外设置红外线吸收剂层,能够防止乱反射的影响。
接着,参照附图说明本发明的第二实施方式。图4(a)是本发明的第二实施方式的半导体装置200从背面看的平面图。图4(b)是图4(a)的Y-Y线剖面图。另外,与第一实施方式相同的部件赋以相同的附图标记,不再赘述。另外,图4(a)中,保护层10等结构的一部分为方便而省略这一点、半导体基板2的背面中与光接收元件1的形成区域重叠的区域不形成配线层9和导电端子11这一点与第一实施方式相同。
第二实施方式的半导体装置200中,如图4(a)、(b)所示,半导体基板2的背面上至少与光接收元件1的形成区域重叠的区域上以一样的面状形成例如铝、金、银、铜等金属材料构成的反射层20。反射层20是具有经由半导体基板2从透光性基板6向半导体基板2的背面方向入射的红外线或从半导体基板2的背面侧入射的红外线不再进一步向前通过而反射的功能的层。只要具有该功能即可,其材料、膜厚不做特别限定。反射层20的膜厚例如是0.1~2μm。
另外,该反射层20使用与配线层9同样的材料,由同一工序形成。具体地例如,通过图3(b)所示那样的溅射法或镀敷法、其他成膜方法等形成铝、铜等金属层。之后,将该金属层在配线层9上构图时,与反射层20的构图同时进行。
根据第二实施方式的半导体装置200,从透光性基板6到反射层20的红外线由反射层20反射到光接收元件1侧。因此,作为以往的问题即配线层9、导电端子11映入输出图像中的情况得以防止,除此之外,有输入到光接收元件1的红外线的光强度上升,输出图像的对比度也上升的优点。另外,如已经叙述的那样,反射层20与配线层9由同一工序形成,所以与第一实施方式相比,不会增加制造工序。
另外,以上的实施方式中,说明了从半导体基板2的表面形成的焊盘电极4沿半导体基板2侧面延伸到背面的配线层9这样的半导体装置,但是只要是在半导体基板2的背面形成配线层、导电端子等的结构即适用于本发明。
因此例如图5所示,形成从与半导体基板2的焊盘电极4对应的位置的表面到背面贯通的通孔,并在该通孔内形成贯通电极,在半导体基板2的背面形成与贯通电极21电气连接的配线层22这样的贯通电极型的半导体装置也可采用本发明。另外,图5(b)是图5(a)的Z-Z线剖面图。与已述的半导体装置相同的结构使用同一附图标记,省略说明。另外,图5的23是例如钛(Ti)层、氧化钛(TiO2)层、钛氮化合物(TiN)层、或钽氮化合物(TaN)层等金属构成的势垒金属层。
该贯通电极型的半导体装置例如通过以下制造工序制造。首先,准备经由光接收元件1和第一绝缘膜3形成焊盘电极4的半导体基板2。其次,在对应焊盘电极4的位置形成贯通半导体基板2的通孔。其次,形成覆盖该通孔的侧壁和半导体基板2的背面的第二绝缘膜8a。其次,除去通孔底部的第二绝缘膜8a,之后在通孔内形成上述势垒金属层23。其次,在通孔内例如通过电解镀敷法等形成铜等金属构成的贯通电极21。其次,在半导体基板2的背面中除与光接收元件1的形成区域重叠的区域以外的区域上构图出与贯通电极21电气连接的配线层22。之后,形成球状的导电端子11、保护层10。另外,上述一系列的工序是贯通电极型半导体装置的制造工序的一例,其制造工序不作限定。另外,未图示,但是,在图5所示的贯通电极型的半导体装置中,与上述第二实施方式的半导体装置同样地,也可以至少在与光接收元件1的形成区域重叠的区域形成反射层。
另外,在以上的实施方式中,说明了具有球状的导电端子的BGA型半导体装置,但是本发明适用于LGA(Land Grid Array:区栅阵列)型半导体装置也可以。

Claims (11)

1.一种半导体装置,其特征在于,具有:
半导体基板,其表面形成有光接收元件;
透光性基板,其在所述光接收元件的上方与所述半导体基板粘合;
配线层,其形成在所述半导体基板的背面上;
保护层,其覆盖所述配线层,
其中,所述配线层形成在所述半导体基板的背面上、除与所述光接收元件的形成区域重叠的区域以外的区域上。
2.如权利要求1所述的半导体装置,其特征在于,所述保护层中混合有红外线吸收材料。
3.如权利要求1所述的半导体装置,其特征在于,所述半导体基板的背面上、与所述光接收元件的形成区域重叠的区域上形成反射层,该反射层使从所述透光性基板经由所述半导体基板向半导体基板背面方向入射的红外线向所述光接收元件侧反射。
4.如权利要求3所述的半导体装置,其特征在于,所述反射层和所述配线层由同一材料形成。
5.如权利要求4所述的半导体装置,其特征在于,所述材料含有金属。
6.如权利要求1~5任一项所述的半导体装置,其特征在于,形成与所述光接收元件电气连接的焊盘电极,所述配线层与所述焊盘电极电气连接,并且从所述半导体基板的侧面向背面延伸。
7.如权利要求1~5任一项所述的半导体装置,其特征在于,所述半导体基板的表面形成焊盘电极,所述半导体基板具有从该半导体基板的背面向所述焊盘电极贯通的通孔,所述配线层通过所述通孔与所述焊盘电极电气连接。
8.一种半导体装置的制造方法,其特征在于,具有如下工序:
准备在表面形成有光接收元件以及焊盘电极的半导体基板;
在所述半导体基板的表面上粘合透光性基板;
在所述半导体基板的背面上、除与所述光接收元件的形成区域重叠的区域以外的区域上形成与所述焊盘电极电气连接的配线层;
形成覆盖所述配线层的保护层。
9.如权利要求8所述的半导体装置的制造方法,其特征在于,在形成所述保护层的工序中,在所述保护层中混合红外线吸收材料。
10.如权利要求8所述的半导体装置的制造方法,其特征在于,在所述半导体基板的背面上与所述光接收元件的形成区域重叠的区域上形成反射层,该反射层使从所述透光性基板经由所述半导体基板向半导体基板背面方向入射的红外线向所述光接收元件侧反射。
11.如权利要求10所述的半导体装置的制造方法,其特征在于,所述配线层和所述反射层由同一材料且同一工序形成。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5010244B2 (ja) * 2005-12-15 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置
US7919353B2 (en) * 2006-09-11 2011-04-05 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US7679167B2 (en) * 2007-01-08 2010-03-16 Visera Technologies Company, Limited Electronic assembly for image sensor device and fabrication method thereof
JP5301108B2 (ja) * 2007-04-20 2013-09-25 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2009032929A (ja) * 2007-07-27 2009-02-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2009099591A (ja) * 2007-10-12 2009-05-07 Toshiba Corp 固体撮像素子及びその製造方法
JP5498684B2 (ja) 2008-11-07 2014-05-21 ラピスセミコンダクタ株式会社 半導体モジュール及びその製造方法
JP5427394B2 (ja) 2008-11-21 2014-02-26 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
CN101419952B (zh) * 2008-12-03 2010-09-15 晶方半导体科技(苏州)有限公司 晶圆级芯片封装方法及封装结构
JP5150566B2 (ja) * 2009-06-22 2013-02-20 株式会社東芝 半導体装置およびカメラモジュール
JP5757614B2 (ja) * 2010-03-05 2015-07-29 国立大学法人九州工業大学 撮像素子
JP2013084722A (ja) * 2011-10-07 2013-05-09 Toshiba Corp 固体撮像装置および固体撮像装置の製造方法
JP6215612B2 (ja) * 2013-08-07 2017-10-18 ソニーセミコンダクタソリューションズ株式会社 発光素子、発光素子ウェーハ及び電子機器
JP6279857B2 (ja) * 2013-08-29 2018-02-14 京セラ株式会社 電子装置、多数個取り枠体および多数個取り電子装置
JP6658782B2 (ja) * 2013-12-19 2020-03-04 ソニー株式会社 半導体装置の製造方法
JP2016001633A (ja) * 2014-06-11 2016-01-07 ソニー株式会社 固体撮像素子、および電子装置
TWI585870B (zh) * 2015-05-20 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
JP7266961B2 (ja) 2015-12-31 2023-05-01 晶元光電股▲ふん▼有限公司 発光装置
JP2018133392A (ja) * 2017-02-14 2018-08-23 キヤノン株式会社 光電変換装置

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521698A (ja) 1991-07-11 1993-01-29 Mitsubishi Electric Corp 半導体装置
US5656819A (en) * 1994-11-16 1997-08-12 Sandia Corporation Pulsed ion beam source
JP2674545B2 (ja) 1995-01-20 1997-11-12 日本電気株式会社 赤外線検出器及びその駆動方法
US5804827A (en) 1995-10-27 1998-09-08 Nikon Corporation Infrared ray detection device and solid-state imaging apparatus
JPH09321333A (ja) 1996-05-24 1997-12-12 Nikon Corp 赤外線検出素子
US5929440A (en) 1996-10-25 1999-07-27 Hypres, Inc. Electromagnetic radiation detector
US5981314A (en) 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US5973337A (en) 1997-08-25 1999-10-26 Motorola, Inc. Ball grid device with optically transmissive coating
JPH11167154A (ja) 1997-12-03 1999-06-22 Olympus Optical Co Ltd フレキシブルプリント基板
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
JP2000349238A (ja) 1999-06-04 2000-12-15 Seiko Epson Corp 半導体装置
US6326689B1 (en) 1999-07-26 2001-12-04 Stmicroelectronics, Inc. Backside contact for touchchip
US6465786B1 (en) 1999-09-01 2002-10-15 Micron Technology, Inc. Deep infrared photodiode for a CMOS imager
JP2001085652A (ja) 1999-09-09 2001-03-30 Sony Corp 赤外線用ccd撮像素子パッケージ
JP3632558B2 (ja) 1999-09-17 2005-03-23 日立化成工業株式会社 封止用エポキシ樹脂組成物及び電子部品装置
US6455774B1 (en) 1999-12-08 2002-09-24 Amkor Technology, Inc. Molded image sensor package
JP2002094082A (ja) * 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
JP3409848B2 (ja) * 2000-08-29 2003-05-26 日本電気株式会社 熱型赤外線検出器
JP5031172B2 (ja) 2000-09-11 2012-09-19 浜松ホトニクス株式会社 シンチレータパネル、放射線イメージセンサおよびそれらの製造方法
KR20020048716A (ko) * 2000-12-18 2002-06-24 박종섭 기판 뒷면에 반사층을 구비하는 이미지 센서 및 그 제조방법
JP3910817B2 (ja) 2000-12-19 2007-04-25 ユーディナデバイス株式会社 半導体受光装置
JP4037197B2 (ja) * 2002-07-17 2008-01-23 富士フイルム株式会社 半導体撮像装置実装構造体の製造方法
US20040108588A1 (en) 2002-09-24 2004-06-10 Cookson Electronics, Inc. Package for microchips
US7033664B2 (en) 2002-10-22 2006-04-25 Tessera Technologies Hungary Kft Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
JP5030360B2 (ja) * 2002-12-25 2012-09-19 オリンパス株式会社 固体撮像装置の製造方法
JP2004260135A (ja) * 2003-02-06 2004-09-16 Sanyo Electric Co Ltd 半導体集積装置及びその製造方法
JP2004319530A (ja) 2003-02-28 2004-11-11 Sanyo Electric Co Ltd 光半導体装置およびその製造方法
TWI229890B (en) * 2003-04-24 2005-03-21 Sanyo Electric Co Semiconductor device and method of manufacturing same
JP2007528120A (ja) 2003-07-03 2007-10-04 テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ 集積回路装置をパッケージングする方法及び装置
JP4401181B2 (ja) 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
US7329861B2 (en) 2003-10-14 2008-02-12 Micron Technology, Inc. Integrally packaged imaging module
US7332408B2 (en) 2004-06-28 2008-02-19 Micron Technology, Inc. Isolation trenches for memory devices
JP2006093367A (ja) 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
JP5010244B2 (ja) 2005-12-15 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP5301108B2 (ja) 2007-04-20 2013-09-25 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2009032929A (ja) 2007-07-27 2009-02-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105531822A (zh) * 2013-11-06 2016-04-27 索尼公司 半导体装置、固态成像元件和电子设备
CN110610951A (zh) * 2014-01-27 2019-12-24 索尼公司 具有改善的切割性能的图像传感器、其制造装置及制造方法
CN110610951B (zh) * 2014-01-27 2022-11-18 索尼公司 具有改善的切割性能的图像传感器、其制造装置及制造方法
US11594563B2 (en) 2014-01-27 2023-02-28 Sony Corporation Image sensor having improved dicing properties

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