CN1959973A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1959973A
CN1959973A CNA2006101285371A CN200610128537A CN1959973A CN 1959973 A CN1959973 A CN 1959973A CN A2006101285371 A CNA2006101285371 A CN A2006101285371A CN 200610128537 A CN200610128537 A CN 200610128537A CN 1959973 A CN1959973 A CN 1959973A
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inserted sheet
semiconductor element
directions
electrode
semiconductor device
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CN100565861C (zh
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船越正司
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明揭示一种半导体器件及其制造方法，半导体器件包含半导体元件(1)、具有往4个方向配置的电极(2)和处在有电极(2)的面的背面的外部电极(4)并装载半导体元件(1)的内插片(5)、将半导体元件(1)固定在内插片(5)上的粘接材料(6)、电连接半导体元件(1)具有的电极和内插片(5)具有的电极(2)的金属丝(7)、密封包含半导体元件(1)和金属丝(7)的区域的绝缘材料(8)、以及装载在内插片(5)具有的外部电极(4)上的金属球(9)，在内插片(5)上由往4个方向配置的电极(2)包围的区域内的边隅对角处设置图案(10)。

Description

半导体器件及其制造方法
技术领域
本发明涉及将端子排列做成面积阵的球栅阵封装的半导体器件及其制造方法。
背景技术
近年，对电子设备、尤其对便携设备而言，多功能化、高功能化、节省空间和降低成本的要求不断提高，但与该动向对应的状态下，主流为缩小芯片规模、并按小间距进行配置的多引脚半导体器件。
这里，作为封装，急需开发封装具有上述特征的半导体元件以满足器件要求的封装件。针对这点，作为封装件开发，通过在原来的QFP(方形扁平封装)的多引脚化中缩短端子间距，也有利于节省空间。
然而，为了满足进一步节空间的要求，如图7所示，开发将端子TS1的排列做成面积阵的球栅阵封装(下文简称为BGA)(例如参考日本国实用新型公开公报实开平1-332号公报)，并且BGA的需求不断增大。
尤其要求这种BGA实现节省空间的小型化。作为实现这点用的一种方法，有减小内插片具有的连接金属丝的电极的间距。
然而，使电极减小间距时，丝焊装置识别电极的精度降低，有可能产生接合错位。因此，通过如图8所示，在内插片IP1上往4个方向排列的电极的隅部对角处，配置与电极形状不同的识别图案NP1，使设备精度提高，防止接合错位。
然而，上述已有技术存在如下课题。
今后，BGA重要的是要求进一步降低成本来设计图7所示那样的1块衬底17上保持的半导体器件数量多的内插片。为了增多1块衬底17保持的半导体器件数量，必须使内插片有效节省未制作半导体器件的无用空间。
为此，不得不减小配置在未制作半导体器件的无用空间的识别图案的尺寸。又，BGA外形本身也开展小型化，内插片上往4个方向排列的电极边隅空间变小，识别图案尺寸也变小。
由于识别图案这样变小，丝焊装置中的识别困难，产生接合错位。这是内插片具有的电极不能减小间距的原因，成为实现半导体器件小型化的课题。
再者，接合工序中，将识别图案NP1用作定位识别标记，因而识别标记变小，使识别精度降低时，将半导体元件装载在衬底上的精度也降低。这是不能缩短半导体元件侧面至内插片具有的电极的距离原因，成为实现半导体器件小型化的课题。
本发明解决上述已有问题，其目的在于提供一种能实现半导体器件小型化，同时还能对衬底设计增加1块衬底保持半导体器件的数量、并且又能实现半导体器件低成本又能使内插片装载半导体元件的精度提高以进一步可靠地防止丝焊错位的半导体器件及其制造方法。
发明内容
为了解决上述课题，本发明的半导体器件，包含：具有多个电极的半导体元件；具有往4个方向配置在衬底表面的电极和配置在所述衬底的背面的外部电极并将所述半导体元件装载在表面侧的内插片；将所述半导体元件固定在所述内插片上的粘接材料，电连接所述半导体元件具有的多个电极和内插片具有的往所述4个方向配置的电极的金属丝；密封包含所述半导体元件和所述金属丝的区域的绝缘材料；以及装载在所述内插片具有的所述外部电极上的金属球，其中，在所述内插片上由所述往4个方向配置的电极包围的区域内的边隅对角处设置至少一对形状与往所述4个方向配置的电极不同的图案。
由此，能按丝焊装置和管芯键合装置的识别能力可充分识别的图案尺寸决定尺寸，而不依赖于未用作半导体器件的区域。而且，由于将图案配置在装载后的半导体元件附近，在半导体元件装载位置有些偏移时，可通过确认图案与半导体元件侧面的距离，立即修正半导体元件的装载位置。
因而，能维持并提高半导体元件安装精度，结果能实现进一步小型化的半导体器件。由于在半导体器件使用的衬底区配置识别图案，可在1块衬底上使半导体器件数量尽量多，与识别图案配置区域无关，从而能谋求降低成本。
此外，本发明的半导体器件，是在上述半导体器件中，设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案形成L状。
由此，作为识别装置，容易识别电极的形状。通过在X方向、Y方向设置线条，半导体元件产生装载位置偏移时能快捷发现，并且容易测量半导体元件侧面至图案的距离，从而可高精度进行装载位置偏差校正。
此外，本发明的半导体器件，是在上述半导体器件中，设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案具有接地功能，并且用所述金属细丝与所述半导体元件电连接。
由此，可以不必在内插片上另行配置具有接地功能的布线。
其结果，以往在由往4个方向配置的电极包围的区域配置将从电极引出的布线连接到各层用的插头，但未配置具有接地功能的布线，因而本发明对插头配置而言，设计自由度提高。
此外，本发明的半导体器件，是在上述半导体器件中，设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案用所述金属丝与所述半导体元件具有的带信号功能的电极电连接。
由此，半导体元件至图案的距离短于半导体元件至配置在内插片的电极的距离，因而能缩短连接半导体元件具有的电极与图案的金属丝的长度。对信号功能中频率高且需要高速信号的信号或希望减小噪声的信号而言，使其连接图案尤其有效。
此外，本发明的半导体器件，是在设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案具有连接到使从所述内插片上往4个方向配置的电极引出的布线与各层的布线结合的插头的受插焊接区的功能。
由此，设置在内插片上由往4个方向配置的电极包围的区域内的边隅对角处的图案形成连接到使各层布线结合用的插头的受插焊接区，从而除作为识别图案的功能外，还能兼有作为来自内插片具有的电极的布线的引入处的功能。因而，仅有受插功能的图案减少，可增加4个方向配置的电极所包围的区域内的布线设计自由度。
此外，本发明的半导体器件制造方法，包含以下工序：将具有多个电极的半导体元件装载到具有往4个方向配置在衬底表面的电极和配置在所述衬底的背面的外部电极的内插片的所述表面侧的工序；用金属丝电连接所述半导体元件具有的多个电极和内插片具有的往所述4个方向配置的电极的工序；利用绝缘材料密封包含所述半导体元件和所述金属丝的区域的工序；将所述金属球装载在所述内插片具有的所述外部电极上的工序；以及在将所述半导体元件装在内插片的所述表面侧的状态下对每一半导体元件制成单片半导体器件的工序，其中，在将所述半导体元件装载到所述内插片的工序中，把设置在所述内插片上由所述往4个方向配置的电极包围的区域内的边隅对角处的所述图案，用作识别所述内插片上的位置用的标记进行定位。
由此，将图案设计成用作衬底识别标记从而识别装置容易识别的尺寸，因而识别精度提高，使半导体元件对内插片的装载位置稳定，而且能防止识别差错造成的设备停止，可谋求提高生产率。
综上所述，采用本发明，则能使半导体元件装载到内插片的精度提高，而且也能防止丝焊错位，又能抑制内插片上未制作半导体器件的无用空间。
因此，能实现半导体器件小型化，同时作为衬底设计还能从1块衬底增加保持半导体器件的数量，可又实现半导体器件降低成本，又使内插片装载半导体元件的精度提高，而且能可靠地防止丝焊错位。
附图说明
图1A是示出本发明实施方式1的半导体器件的结构的平面图；
图1B是示出本发明实施方式1的半导体器件的结构的剖视图；
图2是本发明实施方式2的半导体器件的结构图；
图3是本发明实施方式3的半导体器件的结构图；
图4是本发明实施方式4的半导体器件的结构图；
图5是本发明实施方式5的半导体器件的结构图；
图6A是示出本发明实施方式的半导体器件制造方法的工序1的剖视图；
图6B是示出本发明实施方式的半导体器件制造方法的工序2的剖视图；
图6C是示出本发明实施方式的半导体器件制造方法的工序3的剖视图；
图6D是示出本发明实施方式的半导体器件制造方法的工序4的剖视图；
图6E是示出本发明实施方式的半导体器件制造方法的工序5的剖视图；
图7是已有半导体器件设计时的衬底上的图案配置图；
图8是该已有例的半导体器件的结构图。
具体实施方式
下面，参考附图具体说明示出本发明实施方式的半导体器件及其制造方法。
实施方式1
说明本发明实施方式1的半导体器件。
图1A、图1B是本发明实施方式1的半导体器件的结构图，图1A是半导体器件的平面图，图1B是半导体器件的剖视图。图1A、图1B中，1是半导体元件，2是电极，3是从电极引出的布线(图中仅画出1边，实际上对4边设计引出线)，4是与从电极引出的布线3连接而且与使各层布线结合的插头连接的受插焊接区，5是装载半导体元件1的内插片，6是将半导体元件1固定在内插片1上的粘接材料，7是使半导体元件1具有的电极与内插片5具有的电极2电连接的金属丝，8是密封包含半导体元件1和金属丝7的区域的绝缘材料，9是装载在内插片5的外部端子上的金属球，本实施方式1的半导体器件，其特征为：在内插片5上受往4个方向配置的电极2包围的区域内的边隅部配置特异图案10，作为识别图案。
图7所示的已有一块衬底图案配置中，在一块衬底17上配置多个(图中为4个)半导体器件电极图案，在半导体器件的图案区域外配置识别图案18；此情况下，半导体器件的图案区域外的面积狭小时，不得不使识别图案的尺寸减小，丝焊装置对该识别图案18的识别困难，产生接合错位。
与此相反，本实施方式中，如图1A所示，在内插片5上受往4个方向配置的电极2包围的区域内边隅对角处配置识别图案10，从而作为识别图案10的尺寸，能定为管芯键合装置和丝焊装置的识别能力可充分识别的尺寸，而不依赖于未用作半导体器件的区域。
而且，由于将识别图案10配置在装载后的半导体元件1附近，在半导体元件1的装载位置有些偏移时，可通过确认图案10与半导体元件1的侧面的距离，立即修正半导体元件1的装载位置。
因此，能维持并提高半导体元件1在内插片5上的安装精度，结果能实现进一步小型化的半导体器件。由于在半导体器件的电极2的图案包围的区域内配置识别图案10，可在1块衬底上使半导体器件数量尽量多，与识别图案10的配置区域无关，从而能谋求降低成本。
实施方式2
说明本发明实施方式2的半导体器件。
图2是本实施方式2的半导体器件的结构图。如图2所示，本实施方式2的半导体器件，其特征为：配置在内插片5上的往4个方向配置的电极2包围的区域内边隅部的L形识别图案11。
由此，L形图案11与电极2的形状不同，容易识别。作为L形图案11，如图2所示，往X方向和Y方向设置线条，从而半导体元件1产生装载位置偏移时能快捷发现，并且容易测量半导体元件1的侧面至图案的距离，从而可高精度进行装载位置偏差校正。
实施方式3
说明本发明实施方式3的半导体器件。
图3是本实施方式3的半导体器件的结构图。如图3所示，本实施方式3的半导体器件，其特征为：在内插片5上由往所述4个方向配置的电极2包围的区域内的边隅部配置识别图案12，这样配置的图案12具有接地功能，并且用金属细丝7使设置在半导体元件1的电极与内插片5具有的电极电连接。为了进一步强化接地功能，将识别图案12的线条宽度设计成比衬底的布线宽度粗2～3倍。
由此，由于设置在内插片5上由往所述4个方向配置的电极2包围的区域内的边隅对角处的识别图案12具有接地功能，不必在内插片5上另行配置具有接地功能的布线。
其结果，以往在由往4个方向配置的电极包围的区域配置将从电极引出的布线连接到各层用的插头，但未配置具有接地功能的布线，因而本发明对插头配置而言，设计自由度能提高。
实施方式4
说明本发明实施方式4的半导体器件。
图4是本实施方式4的半导体器件的结构体。如图4所示，本实施方式4的半导体器件，其特征为：设置在内插片5上由往所述4个方向配置的电极2包围的区域内的边隅对角处的识别图案PT4用金属丝7连接半导体元件1具有的带信号功能的电极。又，1个图案PT4上连接半导体元件1具有的带信号功能的多个电极时，如图4所示，设置分离图案13、14，作为图案PT4。
由此，可通过有效利用分离图案13、14，使连接的多个信号电极各自电分离。
实施方式5
说明本发明实施方式5的半导体器件。
图5是本实施方式5的半导体器件的结构图。如图5所示，本实施方式5的半导体器件，其特征为：设置在内插片5上由往所述4个方向配置的电极包围的区域内的边隅对角处的识别图案15具有连接到使内插片5具有的电极2的引出布线16与各层的布线结合的插头的受插焊接区的功能。
由此，仅有受插功能的图案减少，可增加4个方向配置的电极2所包围的区域内的布线设计自由度。
(制造方法)
说明本发明的半导体器件制造方法。
图6A～图6E是示出本实施方式的半导体器件制造方法的工序图。图6A示出一面在内插片5上用粘接材料6固定半导体元件1一面将半导体元件1装载到内插片5的工序1，图6B示出用金属丝7电连接半导体元件1具有的电极和内插片5具有电极2的工序2，图6C示出利用绝缘材料8密封包含半导体元件1和金属丝7的区域的工序3，图6D示出将金属球9装载在内插片5的外部电极上的工序4，图6E示出将半导体器件制成单片的工序5。
本实施方式的半导体器件制造方法，其特征是在上述工序中，在将半导体元件1装载到内插片5的工序1时和用金属丝7连接半导体元件1具有的电极与内插片5具有的电极2的工序2时，把设置在内插片5上由往4个方向配置的电极2包围的区域内的边隅对角处的图案用作衬底识别标记进行定位。
由此，将设置在内插片5上由往4个方向配置的电极2包围的区域内的边隅对角处的图案，设计成用作衬底识别标记从而识别装置容易识别的尺寸，因而识别精度提高，使半导体元件对内插片的装载位置稳定，而且能防止识别差错造成的设备停止，可谋求提高生产率。

Claims (6)

1、一种半导体器件，其特征在于，包含
具有多个电极的半导体元件；
具有往4个方向配置在衬底表面的电极和配置在所述衬底的背面的外部电极，并将所述半导体元件装载在表面侧的内插片；
将所述半导体元件固定在所述内插片上的粘接材料，电连接所述半导体元件具有的多个电极和内插片具有的往所述4个方向配置的电极的金属丝；
密封包含所述半导体元件和所述金属丝的区域的绝缘材料；以及
装载在所述内插片具有的所述外部电极上的金属球，
在所述内插片上由所述往4个方向配置的电极包围的区域内的边隅对角处设置至少一对形状与往所述4个方向配置的电极不同的图案。
2、如权利要求1中所述的半导体器件，其特征在于，
设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案形成L状。
3、如权利要求1中所述的半导体器件，其特征在于，
设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案具有接地功能，并且用所述金属细丝与所述半导体元件电连接。
4、如权利要求1中所述的半导体器件，其特征在于，
设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案用所述金属丝与所述半导体元件具有的带信号功能的电极电连接。
5、如权利要求1中所述的半导体器件，其特征在于，
设置在所述内插片上由往所述4个方向配置的电极包围的区域内的边隅对角处的所述图案，具有连接到使从所述内插片上往4个方向配置的电极引出的布线与各层的布线结合的插头的受插焊接区的功能。
6、一种半导体器件制造方法，其特征在于，包含以下工序：
将具有多个电极的半导体元件装载到具有往4个方向配置在衬底表面的电极和配置在所述衬底的背面的外部电极的内插片的所述表面侧的工序；
用金属丝电连接所述半导体元件具有的多个电极和内插片具有的往所述4个方向配置的电极的工序；
利用绝缘材料密封包含所述半导体元件和所述金属丝的区域的工序；
将所述金属球装载在所述内插片具有的所述外部电极上的工序；以及
在将所述半导体元件装在内插片的所述表面侧的状态下，对每一半导体元件制成单片半导体器件的工序，
在将所述半导体元件装载到所述内插片的工序中，把设置在所述内插片上由所述往4个方向配置的电极包围的区域内的边隅对角处的所述图案，用作识别所述内插片上的位置用的标记进行定位。
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