CN1910752A - 以垫下装置方式之晶圆区域的有效使用 - Google Patents

以垫下装置方式之晶圆区域的有效使用 Download PDF

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Publication number
CN1910752A
CN1910752A CNA2004800404461A CN200480040446A CN1910752A CN 1910752 A CN1910752 A CN 1910752A CN A2004800404461 A CNA2004800404461 A CN A2004800404461A CN 200480040446 A CN200480040446 A CN 200480040446A CN 1910752 A CN1910752 A CN 1910752A
Authority
CN
China
Prior art keywords
metal layer
semiconductor structure
pad
disposed
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800404461A
Other languages
English (en)
Chinese (zh)
Inventor
N·杨
H·小川
Y·吴
K-T·常
Y·孙
D·G·哈密尔顿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Publication of CN1910752A publication Critical patent/CN1910752A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Wire Bonding (AREA)
CNA2004800404461A 2004-01-14 2004-12-17 以垫下装置方式之晶圆区域的有效使用 Pending CN1910752A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/758,148 2004-01-14
US10/758,148 US20050151265A1 (en) 2004-01-14 2004-01-14 Efficient use of wafer area with device under the pad approach

Publications (1)

Publication Number Publication Date
CN1910752A true CN1910752A (zh) 2007-02-07

Family

ID=34740122

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800404461A Pending CN1910752A (zh) 2004-01-14 2004-12-17 以垫下装置方式之晶圆区域的有效使用

Country Status (7)

Country Link
US (1) US20050151265A1 (https=)
EP (1) EP1709685A1 (https=)
JP (1) JP2007518269A (https=)
KR (1) KR20060130105A (https=)
CN (1) CN1910752A (https=)
TW (1) TW200529370A (https=)
WO (1) WO2005071749A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390647A (zh) * 2012-05-10 2013-11-13 无锡华润上华半导体有限公司 一种功率mos器件结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115321B2 (en) * 2009-04-30 2012-02-14 Lsi Corporation Separate probe and bond regions of an integrated circuit
CN110491849B (zh) * 2019-07-18 2024-11-08 珠海零边界集成电路有限公司 芯片、输入输出结构和垫层

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63166273A (ja) * 1986-12-27 1988-07-09 Tdk Corp 縦形半導体装置
JPH06275794A (ja) * 1993-03-18 1994-09-30 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
EP0637840A1 (en) 1993-08-05 1995-02-08 AT&T Corp. Integrated circuit with active devices under bond pads
US7067442B1 (en) * 1995-12-26 2006-06-27 Micron Technology, Inc. Method to avoid threshold voltage shift in thicker dielectric films
JP3157715B2 (ja) * 1996-05-30 2001-04-16 山形日本電気株式会社 半導体集積回路
JPH10335627A (ja) * 1997-05-27 1998-12-18 Sony Corp 固体撮像装置
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
TW445616B (en) 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
JP3505433B2 (ja) 1999-05-21 2004-03-08 三洋電機株式会社 半導体装置
US7199039B2 (en) * 2003-05-19 2007-04-03 Intel Corporation Interconnect routing over semiconductor for editing through the back side of an integrated circuit
JP4492926B2 (ja) * 2003-11-28 2010-06-30 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390647A (zh) * 2012-05-10 2013-11-13 无锡华润上华半导体有限公司 一种功率mos器件结构
WO2013166957A1 (zh) * 2012-05-10 2013-11-14 无锡华润上华半导体有限公司 一种功率mos器件结构

Also Published As

Publication number Publication date
TW200529370A (en) 2005-09-01
US20050151265A1 (en) 2005-07-14
WO2005071749A1 (en) 2005-08-04
EP1709685A1 (en) 2006-10-11
JP2007518269A (ja) 2007-07-05
KR20060130105A (ko) 2006-12-18

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Open date: 20070207