CN1910752A - 以垫下装置方式之晶圆区域的有效使用 - Google Patents

以垫下装置方式之晶圆区域的有效使用 Download PDF

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CN1910752A
CN1910752A CNA2004800404461A CN200480040446A CN1910752A CN 1910752 A CN1910752 A CN 1910752A CN A2004800404461 A CNA2004800404461 A CN A2004800404461A CN 200480040446 A CN200480040446 A CN 200480040446A CN 1910752 A CN1910752 A CN 1910752A
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semiconductor structure
metal level
pad
active device
metal
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N·杨
H·小川
Y·吴
K-T·常
Y·孙
D·G·哈密尔顿
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Spansion LLC
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Abstract

更有效的使用硅面积系藉由加入有源装置(25)于半导体结构(20)的垫区(21)下方而达成。该垫区(21)包含上有第一金属层(23)之衬底(22)。第二金属层(26)则位在该第一金属层(23)的下方。该有源装置(25)是在第二金属层(26)下方的衬底(22)内。介电层(24)系将该第一(23)与第二金属层(26)隔开。在该介电层(24)内之一导通孔(27)系使该第一(23)与第二金属层(26)电性连接。一导通孔(27)系连接至该有源装置(25)。随后的金属层(424，425，426)系经布置成在该第一(23)与第二金属层(26)之间。

Description

以垫下装置方式之晶圆区域的有效使用
技术领域
本发明之具体实施例系有关半导体装置设计之领域。更特别的是，本发明之具体实施例系有关以垫下装置提供晶圆区域更有效的使用。
背景技术
半导体电路设计与制造技术的发展已成就极复杂又密集且运作于低电压的装置，例如闪存、集成电路、与逻辑电路以及其它装置。由于尺度缩放(scaling)系设计复杂又密集的半导体芯片所固有，因此有效使用可用的硅面积(silicon area)而不牺牲效能或劣化物理特性成为一项重要的考量。
有些芯片与晶圆之设计系加上一垫区(pad area)。该垫区通常是在集成电路与外部电路或系统之间可建立的界面处。芯片与外部电路且/或系统之间的界面可包含例如接合(bonding)、针测(probing)、与封装用之界面。为有效建立此等界面，相对于内部电路该垫区通常是宽大的。因此，该垫区明显占用不少芯片的硅面积。
以先进的闪存为例，该垫区占用包含512千位的典型内存扇区一半以上的面积。一典型垫之尺寸约为80微米×80微米，因而覆盖的面积为6,400平方微米。对于有数个垫的芯片，例如范例的闪存芯片有40个垫，则垫区所覆盖的硅面积变为相当显著。例如，范例的闪存芯片上有40个垫，各覆盖6,400平方微米，则总共覆盖50万平方微米以上的硅衬底。
该垫区习知系与芯片内的其它电路隔开。垫与芯片内部电路隔开系有利于针测、接合、与封装，且使该垫区也可用来保护芯片免于静电释放(ESD)的潜在有害效应。与垫隔开后，芯片的电路与装置特性则运作于芯片内的其它地方。图1系图标习知半导体结构10之布局。半导体装置10的垫11与内部电路12的有源装置(active device)是被隔开的。
不过，随着芯片尺寸与工作电压的缩降，垫区所覆盖的硅面积之显著性则变得愈来愈大。该垫通常有数层金属层，最顶端一层用于接合、针测、与封装，下方的数个金属层通常是用来导引垫讯号在芯片的内部电路与例如外部系统之间的进出。最底下的金属层则直接连接于包含芯片之硅衬底。不过，在典型的垫下方之衬底内没有有源装置。
发明内容
由于芯片被设计成愈来愈密集、复杂且由于工作电压减少，以致想要更有效地使用硅。本发明之具体实施例可更有效地使用硅面积。在本发明之一具体实施例中，数个包含快闪或SRAM内存、集成电路、或其类似物的晶粒之半导体结构(例如晶圆片)系加上有源装置于垫区下方。该半导体结构的组件则可执行存储功能、逻辑功能、或其它功能。
兹揭示一种垫区下有有源装置之半导体结构。在一具体实施例中，半导体结构系具有垫区与配置于该垫区下方的有源装置。该有源装置可为例如，晶体管或电路。该有源装置可为该半导体结构数个装置中之一个，该半导体结构也可包含一个至少部份以该垫区为界之非垫区(non-pad)与另一配置于该非垫区内的有源装置。在一具体实施例中，该等数个装置执行类似之功能。
在一具体实施例中，该垫区包含衬底，其系带有配置于其上方之第一金属层且有第二金属层配置于该第一金属层下方。该有源装置(active component)配置在该第二金属层的下方。在一具体实施例中，该半导体结构也有配置于第一与第二金属层之间的介电层与配置于该介电层内的导通孔(via)，该介电层系使该第一与第二金属层电性连接。一导通孔则连接至该有源装置。可将后续的金属层配置在该第一与第二金属层之间。
一具体实施例系提供一种半导体结构用的垫区装置，该半导体结构在金属层下方具有配置于衬底内的有源装置。一具体实施例系提供一种用于制造半导体结构之方法，该半导体结构包含垫区，该垫区下有有源装置。
附图说明
为本专利说明书之一部份的附图系图解本发明之具体实施例，且与实施方式一并用来说明本发明之原理。诸图均不按比例图标。
图1系图标一习知半导体结构之上视图。
图2系根据本发明之一具体实施例图标于垫区下具有有源装置的半导体结构之断面图。
图3系根据本发明之一具体实施例图标于垫区下具有有源装置的半导体结构之上视图。
图4系根据本发明之一具体实施例图标底下有有源装置的垫区之断面图。
图5系根据本发明之一具体实施例图标底下有两个晶体管作为有源装置的垫区之断面图。
图6系根据本发明之一具体实施例图标用于制造半导体结构之方法的流程图。
图7系根据本发明之一具体实施例图标用于制造半导体结构之方法的流程图。
图8系根据本发明之一具体实施例图标用于制造垫区之方法的流程图。
图9系根据本发明之一具体实施例图标用于制造垫区之方法的流程图。
图10系根据本发明之一具体实施例图标用于制造垫区之方法的流程图。
具体实施方式
兹揭示一种垫区下有有源装置之半导体结构。以下本发明的详细说明中系提出许多供彻底了解本发明之特定细节。不过，显然熟谙此艺者可实施本发明而不需该等特定细节或者是等效者。其它的实施例、习知方法、制程、程序、组件、以及电路等不予详述以免模糊本发明之观点。
以下就方法这方面提出本发明具体实施例的部份详细说明。虽然方法的特定步骤与顺序系揭露于描述这些方法操作(例如方法60、80、90、与100)的各图中(例如，图6至图10)，但这些步骤与顺序仅为范例。本发明之具体实施例均适合执行多种其它的步骤或本文流程图所描述诸步骤之变化，且顺序可不同于所图标与描述之顺序。
在此主要系以垫区下具有有源装置的半导体结构说明本发明。此半导体结构系垫下装置方式提供晶圆区域有效使用。在一具体实施例中，半导体结构系具有垫区与配置于该垫区下方的该半导体结构的有源装置。藉由加入装置于该垫区下方，本发明之具体实施例可改善硅面积的使用有效性。根据本发明具体实施例制造半导体结构除能提供经济效益，也可改善晶圆可用的个别晶粒之产量。
示范结构
图2系图标本发明一具体实施例的半导体结构20之断面图。半导体结构20有垫区21，其系与非垫区28毗邻。非垫区28系至少部份以垫区21为界。半导体结构20有配置于该垫区21下方的有源装置25。有源装置25可为例如晶体管。有源装置25可为半导体结构20的数个组件中之一个。例如，可将另一装置29配置于该非垫区28内。在一具体实施例中，装置25与29执行类似的功能。
该垫区21包含衬底22。衬底22具有配置于其上方的第一金属层26。衬底22也有第二金属层23，其配置在该第一金属层26的上方。该有源装置25配置在该第一金属层26的下方。在一具体实施例中，该半导体结构20也有介电层24，其配置在第一金属层23与第二金属层26之间。在一具体实施例中，导通孔27配置在该介电层24内。导通孔27系使该第一金属层23与第二金属层26电性连接。在一具体实施例中，导通孔27系连接至该有源装置。随后的金属层也可被配置在该第一金属层23与第二金属层26之间。
在一具体实施例中，衬底22包含硅。在一具体实施例中，该介电层24系层间介电质(ILD)且可包含材料，例如正硅酸乙酯(TEOS)、类似的介电材料、或其它的介电材料。金属层23与26(以及任一层间的金属层)与导通孔27可包含任何导电材料，包含，但不受限于，铜、铝、金、银、钨、或任何其它导电金属、或其它的导电材料，尤其是例如复晶硅(POLY)与硅化钨。
图3系根据本发明之一具体实施例图标垫区21下具有有源装置(例如，晶体管，电路，或其类似物，等等)的半导体结构20之上视图。半导体装置20的部份非垫区29系以垫区21为界。在一示范具体实施例中，半导体装置20包含闪存。
在此闪存中，该垫之尺寸可约为80微米×80微米且半导体装置20的垂直尺寸约为3,000微米。在一示范性的具体实作中，可由半导体结构20之非垫区29切割100个个别的晶粒(例如，个别的有源装置)且可由该垫区21下方多切3个个别的有源装置。相较于垫区下无有源装置的半导体结构，此具体实作可增加百分之3的有源装置。
图4系根据本发明之一具体实施例图标底下有有源装置25的垫区400之断面图。垫区400配置在硅衬底22的上方，其中系配置有源装置25。
在一具体实施例中，顶部金属层23系形成垫区400之上表面。在另一具体实施例中，顶部金属层23的上方可具有另一材料层，例如涂层，氧化物层，等等。第二金属层424配置在该顶部金属层23下方。层间介电层(ILD)24被配置在顶部金属层23与第二金属层424之间。顶部金属层23与第二金属层424系藉由导通孔27而电性互连，在一具体实施例中，其包含复数个个别的导通孔。
第二金属层424下方系配置一第三金属层425。第四金属层426配置在第三金属层425的下方。层间介电层(ILD)24配置在第三金属层425与第四金属层426之间。第三金属层425与第四金属层426系藉由导通孔27而电性互连，在一具体实施例中，其包含复数个个别的导通孔。一导通孔27可使第三金属层425与第二金属层424电性连接。
底部金属层(M1)26配置在硅衬底22上方且在第四金属层426下方。在一具体实施例中，可配置任何数层的额外金属层于底部金属层26上方以及于第四金属层426下方。可将层间介电层(ILD)24配置于附加的金属层之间、附加金属层中之一层与底部金属层26且/或第四金属层426之间，且/或于该第三金属层425与第二金属层424之间。
导通孔27可使该等附加金属层中之任何一层电性相互连接且/或可使彼等电性连接于任一其它的金属层，例如底部金属层26、或第四金属层426。导通孔27可使底部金属层26电性连接于配置于其上方之任一金属层。导通孔27可使有源装置25电性连接于任一金属层，例如底部金属层26或配置于其上方之任一金属层。
图5系根据本发明之一具体实施例图标底下有两个作为有源装置的晶体管598与599的垫区500之断面图。晶体管598与599均被配置在垫区500底下的硅衬底22内。垫区500系具有配置于衬底22上方的底部(M1)金属层26。
晶体管598包含源极区501与汲极区502，经配置在衬底22的适当掺杂区内。源极区501与汲极区502系各自藉由一个别的导通孔527电性连接于底部金属层26(或连接至另一金属层)。晶体管598也包含可为复晶硅II(POLY-II)或另一闸极材料之闸极503，其配置在源极区501与闸极区502的上方及其间且在底部金属层26的下方。
晶体管599包含源极区504与汲极区505，经配置在衬底22的适当掺杂区内。源极区504与汲极区505系各自藉由一个别的导通孔527电性连接于底部金属层26(或连接至另一金属层)。晶体管599也包含可为POLY-II或另一闸极材料之闸极506，其配置在源极区504与闸极区505的上方及其间且在底部金属层26的下方。
在一具体实施例中，顶部金属层23系形成垫区500之上表面。第二金属层424配置在顶部金属层23的下方。层间介电层(ILD)24配置在顶部金属层23与第二金属层424之间。顶部金属层23与第二金属层424系藉由导通孔27而电性互连，在一具体实施例中，其包含复数个个别的导通孔。
第二金属层424的下方系配置第三金属层425。第四金属层426配置在第三金属层425的下方。层间介电层(ILD)24配置在第三金属层425与第四金属层426之间。第三金属层425与第四金属层426系藉由导通孔27而电性互连，在一具体实施例中，其包含复数个个别的导通孔。导通孔27可使第三金属层425与第二金属层424电性连接。
底部金属层(M1)26配置在硅衬底22上方与第四金属层426下方。在一具体实施例中，于底部金属层26上方与第四金属层426下方可配置任意数量的额外金属层。可将层间介电层(ILD)24配置在附加金属层之间、附加金属层中之一层与底部金属层26且/或第四金属层426之间，且/或该第三金属层425与第二金属层424之间。导通孔27可使该等附加金属层中之任何一层电性相互连接且/或可使彼等电性连接于任一其它的金属层，例如底部金属层26、或第四金属层426。导通孔27可使底部金属层26电性连接于配置于其上方之任一金属层。
示范方法
以下描述的方法系解释用于制造半导体结构与半导体结构用的垫区的方法。该等方法可使用本技艺所习知的技术而予以具体实作，从而在此不予详述以免混淆本发明之具体实施例。例如，方法80(图8)之步骤81包含形成一衬底。形成衬底乃本技艺所习知，且任一可应用的技术均可用来完成步骤81。同样，可适当应用任何一习知技术实施本发明之具体实施例。
此外，为求简明，系以列于一示范性顺序中的个别步骤说明以下所描述的方法。尽管将彼等之特定步骤与顺序揭示于本文的各图中(例如，图6至图10)用来描述该等方法(例如，方法60、70、80、90、与100)之作业，该等步骤及顺序仍只具示范性。本发明之具体实施例均适合多种其它的步骤或本文流程图所描述诸步骤之变体的执行，且顺序可不同于所图标与描述的顺序。
用于制造半导体结构之示范方法
图6系根据本发明之一具体实施例图标一种制造半导体结构用之方法60的流程图。方法60由步骤61开始，其中设置垫区。在步骤62，有源装置(例如，晶体管)配置在该垫区的下方，即完成方法60。
图7系根据本发明之一具体实施例图标用于制造半导体结构之方法70的流程图。方法70系由步骤71开始，其中设置垫区。在步骤72，有源装置配置在该垫区的下方。
步骤73中，系设置非垫区，使得该非垫区至少部份以该垫区为界。步骤74中，系将第二组件(例如，有源装置、电路、等等)配置在该非垫区内，即完成方法70。
用于制造半导体结构用的垫区的示范方法
图8系根据本发明之一具体实施例图标用于制造半导体结构用的垫区的方法80之流程图。方法80系由步骤81开始，其中系形成衬底。在步骤82，有源装置(例如晶体管)配置在该衬底内。
在步骤83，第一金属层配置在该衬底的上方。该第一金属层，于一具体实施例中，其包含配置于该衬底上方的底部(M1)金属层。步骤84中，第二金属层配置在该第一金属层的上方，即完成方法80。
图9系根据本发明之一具体实施例图标用于制造垫区之方法90的流程图。方法90系由步骤91开始，其中形成衬底。步骤92中，有源装置(例如，晶体管)配置在该衬底内。
在步骤93，第一金属层配置在该衬底的上方。该第一金属层，在一具体实施例中，包含配置于该衬底上方的底部(M1)金属层。步骤94中，第二金属层配置在该第一金属层的上方。
在步骤95，介电层，例如层间介电层(ILD)，配置在该第一与第二金属层之间。步骤96中，导通孔配置在该介电层内藉以使该第一与第二金属层电性连接。步骤97中，一导通孔配置在该衬底内且在该第二金属层的下方，藉以使该有源装置电性连接至一金属层，即完成方法90。
图10的流程图系根据本发明之一具体实施例图标制造半导体组件用的垫区的方法100。方法100由步骤101开始，其中系形成衬底。步骤102中，有源装置，例如晶体管，配置在该衬底内。
步骤103中，第一金属层配置在该衬底的上方。在一具体实施例中，该第一金属层包含配置于该衬底上方的底部(M1)金属层。步骤104中，第二金属层配置在该第一金属层的上方。
在步骤105，随后一金属层配置在该第一与第二金属层之间，在一具体实施例中，即完成100。在另一具体实施例中，可配置数层介电层藉以电性隔开数个金属层。在另一具体实施例中，导通孔可经配置在该介电层内藉以使金属层电性相互连接且/或连接至该有源装置。
从而以本发明之具体实施例描述一种以垫下的装置更有效使用晶圆区域的方法。尽管已用特定的具体实施例描述本发明，应了解，本发明不应被解释成是受限于该等具体实施例，反而是根据以下之申请专利范围解释本发明。

Claims (10)

1.一种半导体结构(20)，包含：
垫区(21)；以及
该半导体结构(20)的有源装置(25)，配置在该垫区(21)的下方。
2.如权利要求1所述的半导体结构(20)，其中该有源装置(25)包含晶体管。
3.如权利要求1所述的半导体结构(20)，其中该半导体结构(20)的组件(29)执行逻辑功能。
4.如权利要求1所述的半导体结构(20)，其中该半导体结构(20)的组件(29)执行存储功能。
5.如权利要求1所述的半导体结构(20)，其中该有源装置(25)包含第一装置，该半导体结构(20)进一步包含：
非垫区(28)，该非垫区至少部分地以该垫区(21)为界；以及
第二装置(29)，配置在该非垫区(28)内。
6.如权利要求5所述的半导体结构(20)，其中该第一(25)与该第二装置(29)执行类似的功能。
7.如权利要求1所述的半导体结构(20)，其中该垫区(21)包含：
衬底(22)；
第一金属层(26)，配置在该衬底(22)的上方，其中该有源装置(25)配置在该第一金属层(26)的下方；
第二金属层(23)，配置在该第一金属层(26)的上方。
8.如权利要求7所述的半导体结构(20)，进一步包含：
介电层(24)，配置在该第一金属层(26)与该第二金属层(23)之间；和
导通孔(27)，配置在该介电层(24)内，其中该导通孔(27)使该第一金属层(26)与该第二金属层(23)电性连接。
9.如权利要求7所述的半导体结构(20)，在该第一(26)与该第二金属层(23)之间进一步包含后续金属层(424)。
10.一种用于半导体结构(20)的垫区装置(21)，包含：
衬底(22)；
第一金属层(26)，配置在该衬底(22)的上方；
第二金属层(23)，配置在该第一金属层(26)的上方；以及
有源装置(25)，其中该有源装置(25)配置在该衬底(22)内。
CNA2004800404461A 2004-01-14 2004-12-17 以垫下装置方式之晶圆区域的有效使用 Pending CN1910752A (zh)

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