CN1894781A - 制造氮化氧化硅栅极介质的方法 - Google Patents

制造氮化氧化硅栅极介质的方法 Download PDF

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CN1894781A
CN1894781A CNA2004800243953A CN200480024395A CN1894781A CN 1894781 A CN1894781 A CN 1894781A CN A2004800243953 A CNA2004800243953 A CN A2004800243953A CN 200480024395 A CN200480024395 A CN 200480024395A CN 1894781 A CN1894781 A CN 1894781A
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silicon
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CN1894781B (zh
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J·S·伯纳姆
J·S·纳科斯
J·J·昆利万
B·小罗克
S·M·尚克
B·A·沃德
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

一种制造栅极介质层的方法，包括以下步骤：提供衬底(100)；在衬底的上表面(105)上形成二氧化硅层(110)；在还原气氛中执行等离子体氮化以将二氧化硅层转变为氧氮化硅层(110A)。这样形成的介质层可以用于制造MOSFET(145)。

Description

制造氮化氧化硅栅极介质的方法
技术领域
本发明涉及半导体器件的制造；更具体地说，它涉及制造氮化氧化硅栅极介质的方法。
背景技术
集成电路趋向较高性能、较高速度和较低成本。相应地，要缩小器件的维度和元件的尺寸，并且必须相应地按比例缩放栅极介质。当栅极介质物理厚度减小时，出现了对较高介电常数和较低泄漏栅极介质的需求。在先进金属氧化物半导体场效应晶体管(MOSFET)中，用氧氮化硅(SiOxNy)层作栅极介质。MOSFET晶体管包括在硅衬底中形成的沟道区域，在薄栅极介质层顶上形成并在沟道区域上对准的N或P掺杂多晶硅栅极，以及在沟道区域的任意一侧上的硅衬底中形成的源极/漏极区域。
然而，SiOxNy栅极介质的一个问题是经过晶片厚度和氮浓度的改变。栅极介质的经过晶片厚度和氮浓度的改变直接导致经过晶片阈值电压的改变，特别地，在P-沟道场效应晶体管(PFET)中，引起来自相同晶片的各个分离集成电路芯片的性能的改变。因此，需要一种制造具有相对均匀的经过晶片厚度和氮浓度的SiOxNy层的方法。
发明内容
本发明的第一方面是一种制造栅极介质层的方法，包括以下步骤：提供衬底；在所述衬底的上表面上形成二氧化硅层；在还原气氛中执行等离子体氮化以将所述二氧化硅层转变为氧氮化硅层。
本发明的第二方面是一种制造MOSFET的方法，包括以下步骤：提供具有至少最上硅层的半导体衬底；在所述半导体衬底的上表面上形成二氧化硅层；在还原气氛中执行等离子体氮化以将所述二氧化硅层转变为氧氮化硅层；在所述氧氮化硅层上形成多晶硅栅极，所述多晶硅栅极在所述半导体衬底中的沟道区域上对准；以及在所述半导体衬底中形成源极/漏极区域，所述源极/漏极区域与所述多晶硅栅极对准。
附图说明
在附加权利要求中阐明了本发明的特征。然而，通过参考后面示意性实施例的详细描述并与附图一起阅读将会更好地理解发明本身，其中：
图1至3是部分截面图，示出了根据本发明制造氮化栅极介质层；
图4和5是部分截面图，示出了根据本发明制造MOSFET；
图6是根据本发明用于制造在图1至4中示出的介质层和MOSFET的工艺步骤的流程图；
图7是根据本发明的第一实施例用于执行氮化步骤的远程等离子体系统氮化系统的示意图；
图8是根据本发明氮化氧化硅栅极介质的经过晶片厚度的控制改善的图表；
图9是根据本发明使用和不使用还原气体，氮化二氧化硅厚度的不同的图表；以及
图10是根据本发明的第二实施例用于执行氮化步骤的远程等离子体系统氮化系统的示意图。
具体实施方式
术语氮化二氧化硅指向SiO2层中引入氮以形成氧氮化硅(SiOxNy)。SiOxNy的范围包括所有整数x和y(或其分数)的组合，其中SiOxNy是稳定的。还原气氛限定为包括与氧反应的核素的气态气氛。
图1至3是部分截面图，示出了根据本发明制造氮化物栅极介质层。在图1中，提供具有上表面105的衬底100。衬底100可以是本征、N-型或P-型体硅衬底，未掺杂或本征、N-型或P-型绝缘体上硅(SOI)衬底或蓝宝石衬底或红宝石衬底。
在图2中，在衬底100的上表面105上形成具有厚度D1的基体SiO2层110。在表面105上形成基体SiO2层110之前，通过技术上已公知的多个清洁工艺的任意一个清洁该表面。例如，可以使用稀释氢氟酸(BHF)清洁之后NH4OH清洁再之后HCl清洁来清洁表面105。如果衬底100是块体硅衬底或SOI衬底，可以在第一实例中，通过在含氧气氛的炉中，在约600到800℃温度下热氧化约0.5到30分钟，形成基体SiO2层110。在第二实例中，可以通过在含氧气氛中，在约800到1000℃温度下快速热氧化(RTO)约5到60秒，形成基体SiO2层110。如果衬底100是红宝石或蓝宝石衬底，可以通过在化学气相沉积(CVD)装置中沉积形成基体SiO2层110并且介质层可以是四乙氧基硅烷(TEOS)氧化物。TEOS还可以用于体硅或SOI衬底。TEOS还可以用于体硅或SOI衬底。在一个实例中，D1约8到23厚。对任意衬底，基体SiO2层110可以是自然氧化物，允许通过将清洁硅表面暴露在空气或氧气中形成，或基体SiO2层110可以通过“裸”硅表面的氧化清洁工艺形成。
在图3中，执行远程等离子体氮化(RPN)工艺以将基体SiO2层110(见图2)转变为氮化SiO2(SiOxNy)层110A。下面参考图6，7和9描述远程等离子体氮化工艺。SiOxNy层110A具有厚度D2。在一个实例中，D2约8到24厚。在一个实例中，SiOxNy层110A约2到20％的氮原子。在第二实例中，在SiOxNy层110A中的氮的浓度在1E21和1E22atm/cm3之间。本发明的一个优点是氮化后氧化物的介质厚度与氮化前氧化物的厚度相比增加很小。尽管厚度增加的数量是氮化前氧化物的厚度(D1)的函数，氮化后氧化物的厚度(D2)通常仅增加约0到5％。
图4和5是部分截面图，示出了根据本发明制造MOSFET。图4延续图3。在图4中，在SiOxNy层110A的上表面上形成多晶硅层115。可以使用技术上已公知的如低压化学气相沉积(LPCVD)或快速热化学气相沉积(RTCVD)的许多沉积工艺的一种形成多晶硅层115。多晶硅层115可以是未掺杂或掺杂N-型或P-型。在一个实例中，多晶硅层115是1000到2000厚。
在图5中，蚀刻多晶硅层115(参看图4)；例如，通过反应离子蚀刻(RIE)工艺以形成栅极125。在栅极125的侧壁135上形成隔离物130。源极/漏极140的形成(典型地通过一步或多步离子注入工艺)基本上完成MOSFET 145的形成，SiOxNy层110A作为MOSFET的栅极介质。如果多晶硅层115(参看图4)在沉积期间未掺杂，形成隔离物后，栅极125可以与源极/漏极140的形成一起或通过分离步骤，通过离子注入掺杂N-型或P-型。
图6是根据本发明，在图1至5中示出的用于形成介质层和MOSFET的工艺步骤的流程图。将以硅衬底为例。在步骤150中，通过技术上已公知的多个清洁工艺的任意一个清洁硅衬底的表面。在第一实例中，可以使用稀释氢氟酸(BHF)清洁之后NH4OH清洁再之后HCl清洁，来清洁硅表面105。可选地，在第二实例中，可以使用BHF之后O3清洁再之后干HCl清洁，来清洁硅表面。
在步骤155中，例如，通过在含氧气氛的炉中，在约600到800℃温度下热氧化约0.5到30分钟，通过在含氧气氛中，在约800到1000℃温度下RTO约5到60秒，或通过将清洁硅表面暴露于空气或氧气，来形成基体SiO2层。基体SiO2层约8到23厚。
在步骤160中，执行远程等离子体氮化工艺。在第一实例中，将氮和如氦的惰性气体的混合气体引入远程等离子体氮化装置的等离子体产生端口，并将如氢或氨的还原气体通过第二、非等离子体产生端口引入，同时在处理反应室中旋转将要处理的晶片(参看图7)。典型的工艺条件是氮的流速约1到20slm(标准升/分)，氦(或其它惰性气体)的流速约1到20slm，氢(氨或其它还原气体)的流速约1到20slm，反应室气压约0.2到50Torr，微波功率1000到3000瓦特，晶片温度约25到1000℃，持续约20到500秒。
在第二实例中，将氮、如氦的惰性气体和如氢或氨的还原气体的混合气体引入远程等离子体氮化装置的等离子体产生端口，同时在处理反应室中旋转将要处理的晶片(参看图10)。典型的工艺条件是氮的流速约1到20slm，氦(或其它惰性气体)的流速约1到20slm，氢的流速约1到20slm，反应室气压约0.2到50Torr，微波功率1000到3000瓦特，晶片温度约25到1000℃，持续约20到500秒。
在这两个实例中，氮的剂量约1E14到5E15atm/cm2并且最终SiOxNy层含有约2到20％的氮。
在步骤165中，执行可选的退火步骤。通常不需要退火，因为在热晶片上实施远程等离子体氮化。可以执行标准的快速热退火(RTA)或峰值RTA。使用峰值退火以提高迁移率而不驱使氮进入SiO2/Si界面。峰值退火限定为晶片在最高晶片温度的时间约60秒或更短的退火，而标准RTA限定为晶片在最高晶片温度的时间大于约60秒的退火。
之后的步骤使用氮化SiO2介质作为MOSFET的栅极介质。
在步骤170中，使用技术上已公知的如LPCVD或RTCVD的多种沉积工艺的一种在氮化SiO2上形成多晶硅层。该多晶硅层可以未掺杂或掺杂N-型或P-型。在一个实例中，多晶硅层是1000到2000厚。
在步骤175中，基本上完成了MOSFET。蚀刻多晶硅层；例如，通过RIE工艺形成栅极，在栅极的侧壁上形成隔离物并且在栅极的任意一侧上的衬底中形成源极/漏极(典型地通过一步或多步离子注入工艺)。SiOxNy层是MOSFET的栅极介质。如果多晶硅层在沉积期间未掺杂，形成隔离物后，栅极可以与源极/漏极140的形成一起或通过分离的步骤，通过离子注入掺杂N-型或P-型。
图7是根据本发明的第一实施例，用于执行氮化步骤的远程等离子体系统氮化系统的示意图。在图7中，远程等离子体装置180包括反应室185和在反应室中的可旋转晶片卡盘190(用于夹持晶片195)。用于提供能量以启动并维持等离子体205的微波线圈200包围反应室185的内壁215中的第一入口210A。通过入口210A提供用于产生等离子体205的气体(在本实例中，氦/氮混合气体)。通过第二入口210B提供还原气体(在本实例中，氢)。其它还原气体包括氨，氢和氮的混合气体，氨和氮的混合气体，以及氢、氨和氮的混合气体，氘，氘化氨，氘和氮的混合气体，氘化氨和氮的混合气体，氘、氘化氨和氮的混合气体，以及氘、氨和氮的混合气体。也在反应室185的内壁215中并与真空泵(未示出)相连的排气口220移除废核素并维持处理气压。排气口220和第一入口210A位于室185的直径相对侧，并且第二入口210B位于第一入口和排气口之间。
使用中，具有在晶片230上表面上的基体SiO2层(未示出)的晶片195从转换反应室(未示出)放入反应室185中并且旋转，通过第一入口210A将预定氮化气体混合物(在本实例中，He/N2)以预定流速引入反应室，通过第二入口B将预定还原气体混合物(在本实例中，H2/NH3)以预定流速引入反应室，并且反应室通过与排气口220相连的真空泵维持预定气压。将预定瓦特数的微波功率施加到微波线圈200上，以激励并维持等离子体205。在预定时间后，断开微波功率熄灭等离子体205，切断气流并且反应室185的气压达到转换反应室的气压。等离子体205主要是氮离子、氦离子、氢中性等离子体。
用于实践本发明的合适装置的一个实例是由Applied Materials Corp，Santa Clara，CA制造的AMAT model XE12反应室，具有也是由AppliedMaterials Corp提供的解耦等离子体单元。
图8是根据本发明氮化氧化硅栅极介质的经过晶片厚度的控制改善的图表。图8示出了对于平均厚度相同的两个氮化二氧化硅膜，RPN后氧化硅膜的厚度对与晶片中心的距离的函数。使用椭偏仪执行测量。曲线225是如上述处理的SiOxNy层，但是没有任何还原气体流。曲线225的SiOxNy层的平均厚度是17.9，具有0.97的δ。曲线230是如上述处理的SiOxNy层，但是具有还原气体流。曲线230的SiOxNy层的平均厚度是18.0，具有0.50的δ。因此，引入还原核素导致厚度不均匀的约双倍的增加。
层225和230的第二离子质谱分析(SIMS)分布说明氮浓度均匀性的提高与SiOxNy厚度均匀性的提高轨迹复合很好，如表I所示。注意氮的剂量和浓度之间是一一对应的。
                                     表I
  晶片   工艺   氮剂量晶片中心   氮剂量晶片边缘   △
  晶片A晶片B晶片C   RPN w/o H2RPN w H2RPN w H2   4.8E14atm/cm22.0E14atm/cm24.3E14atm/cm2   7.3E14atm/cm22.5E14atm/cm25.2E14atm/cm2   52％25％21％
在表I中，在没有还原气体存在的反应室中，由远程等离子体氮化处理的晶片中，氮浓度从中心到边缘的改变超过50％。在具有还原气体存在的反应室中，由远程等离子体氮化处理的晶片的两个实例中，在晶片中氮浓度从中心到边缘的改变不超过25％。
因此，SiOxNy厚度的均匀性和氮浓度的均匀性都有约两倍因子的提高。
图9是根据本发明使用和不使用还原气体，氮化二氧化硅厚度的不同的图表。如上所述，在执行RPN处理时不使用还原气体的另一个问题是，如所示的在基体SiO2层和完成的SiOxNy层之间介质厚度有不可接受的增加。如图9所示，向RPN反应室中引入还原气体大大降低了此厚度的增加。图9绘出了自然氧化(曲线235)、RPN后自然氧化膜无还原气体处理(曲线240)和RPN后自然氧化膜有还原气体处理(曲线245)的厚度对与晶片中心的距离的函数。使用椭偏仪执行测量。曲线240是SiOxNy层，由约10厚的自然氧化层经上述处理制备，但是没有任何还原气体流。曲线240的SiOxNy层的平均厚度约25到27.5。曲线245是如上述处理的SiOxNy层，但是具有还原气体流。曲线245的平均厚度约13到13.5。因此，引入还原核素明显减小了介质层厚度在RPN处理期间的增加。厚度的增加限定在约35％。在一些实例中厚度的增加接近于零。
图10是根据本发明的第二实施例用于执行氮化步骤的远程等离子体系统氮化系统的示意图。图10类似于图7，除了没有气体从第二入口210B提供而所有的气体(氮，氦和氢)都通过第一入口210A提供。等离子体205主要是氮离子、氦离子、氢离子等离子体。
因此，本发明满足了对具有相对均匀的经过晶片厚度的SiOxNy层的制造方法的需求。
上面给出的本发明的实施例的描述用于理解本发明。应该明白，本发明不仅仅限于这里描述的特殊的实施例，而是现在对于本领域的技术人员明白的是，在不脱离本发明的范围内可以进行各种修改，重新布置以及替代。因此，旨在随后的权利要求覆盖落入本发明的真正精神和范围内的所有这样的修改和变换。

Claims (30)

1.一种制造栅极介质层的方法，包括以下步骤：
提供衬底；
在所述衬底的上表面上形成二氧化硅层；
在还原气氛中执行等离子体氮化以将所述二氧化硅层转变为氧氮化硅层。
2.根据权利要求1的方法，其中使用远程等离子体氮化工艺执行所述等离子体氮化步骤。
3.根据权利要求1的方法，其中使用通过远程等离子体氮化装置的第一入口引入的氮和惰性气体等离子体和通过所述远程等离子体氮化装置的第二入口引入的中性还原气体执行所述等离子体氮化步骤。
4.根据权利要求3的方法，其中所述惰性气体是氦，并且所述还原气体是氢，氨，氢和氮的混合气体，氨和氮的混合气体，以及氢、氨和氮的混合气体，氘，氘化氨，氘和氮的混合气体，氘化氨和氮的混合气体，氘、氘化氨和氮的混合气体，或氘、氨和氮的混合气体。
5.根据权利要求1的方法，其中使用包括氮，惰性气体和还原气体的等离子体执行所述等离子体氮化步骤。
6.根据权利要求5的方法，其中所述惰性气体是氦，所述还原气体是氢。
7.根据权利要求1的方法，其中所述衬底包括体硅或绝缘体上硅衬底，并且通过选自如下的工艺形成所述二氧化硅层：在空气或氧气中自然氧化生长、热氧化、快速热氧化、化学气相沉积和氧化清洁工艺。
8.根据权利要求1的方法，其中所述二氧化硅层具有约8到23的厚度。
9.根据权利要求1的方法，其中所述氧氮化硅具有约8到24的厚度。
10.根据权利要求1的方法，其中所述氧氮化硅膜包括约2到20百分比的氮。
11.根据权利要求1的方法，其中在所述氧氮化硅层中的氮的浓度在约1E21和1E22atm/cm3之间。
12.根据权利要求1的方法，其中所述执行等离子体氮化的步骤将约1E14到5E14atm/cm2剂量的氮赋予所述二氧化硅层。
13.根据权利要求1的方法，其中所述氧氮化硅层的厚度比所述二氧化硅层的厚度厚约0到35％。
14.根据权利要求1的方法，其中所述氧氮化硅层的厚度从所述衬底的中心到边缘改变不大于约0.5埃δ。
15.根据权利要求1的方法，其中所述氧氮化硅层的氮浓度从所述衬底的中心到边缘改变不大于约25％。
16.一种制造MOSFET的方法，包括以下步骤：
提供具有至少最上硅层的半导体衬底；
在所述半导体衬底的上表面上形成二氧化硅层；
在还原气氛中执行等离子体氮化以将所述二氧化硅层转变为氧氮化硅层；
在所述氧氮化硅层上形成多晶硅栅极，所述多晶硅栅极在所述半导体衬底中的沟道区域上对准；以及
在所述半导体衬底中形成源极/漏极区域，所述源极/漏极区域与所述多晶硅栅极对准。
17.根据权利要求16的方法，其中使用远程等离子体氮化工艺执行所述等离子体氮化步骤。
18.根据权利要求16的方法，其中使用通过远程等离子体氮化装置的第一入口引入的氮和惰性气体等离子体和通过所述远程等离子体氮化装置的第二入口引入的中性还原气体执行所述等离子体氮化步骤。
19.根据权利要求18的方法，其中所述惰性气体是氦，并且所述还原气体是氢，氨，氢和氮的混合气体，氨和氮的混合气体，以及氢、氨和氮的混合气体，氘，氘化氨，氘和氮的混合气体，氘化氨和氮的混合气体，氘、氘化氨和氮的混合气体，或氘、氨和氮的混合气体。
20.根据权利要求16的方法，其中使用包括氮，惰性气体和还原气体的等离子体执行所述等离子体氮化步骤。
21.根据权利要求20的方法，其中所述惰性气体是氦，所述还原气体是氢。
22.根据权利要求16的方法，其中所述衬底包括体硅或绝缘体上硅衬底，并且通过选自如下的工艺形成所述二氧化硅层：在空气或氧气中自然氧化生长、热氧化、快速热氧化、化学气相沉积和氧化清洁工艺。
23.根据权利要求16的方法，其中所述二氧化硅层具有约8到23的厚度。
24.根据权利要求16的方法，其中所述氧氮化硅具有约8到24的厚度。
25.根据权利要求16的方法，其中所述氧氮化硅膜包括约2到20百分比的氮。
26.根据权利要求16的方法，其中在所述氧氮化硅层中的氮的浓度在约1E21和1E22atm/cm3之间。
27.根据权利要求16的方法，其中所述执行等离子体氮化的步骤将约1E14到5E14atm/cm2剂量的氮赋予所述二氧化硅层。
28.根据权利要求16的方法，其中所述氧氮化硅层的厚度比所述二氧化硅层的厚度厚约0到35％。
29.根据权利要求16的方法，其中所述氧氮化硅层的厚度从所述衬底的中心到边缘改变不大于约0.5埃δ。
30.根据权利要求16的方法，其中所述氧氮化硅层的氮浓度从所述衬底的中心到边缘改变不大于约25％。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060275975A1 (en) * 2005-06-01 2006-12-07 Matt Yeh Nitridated gate dielectric layer
US7429538B2 (en) * 2005-06-27 2008-09-30 Applied Materials, Inc. Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
US20070049048A1 (en) * 2005-08-31 2007-03-01 Shahid Rauf Method and apparatus for improving nitrogen profile during plasma nitridation
KR100718835B1 (ko) 2005-09-13 2007-05-16 삼성전자주식회사 반도체 모스 트랜지스터와 그 제조 방법
JP5070702B2 (ja) * 2006-01-19 2012-11-14 富士通セミコンダクター株式会社 半導体装置の製造方法及び製造装置
US7737050B2 (en) * 2006-10-30 2010-06-15 International Business Machines Corporation Method of fabricating a nitrided silicon oxide gate dielectric layer
US20080200039A1 (en) * 2007-02-16 2008-08-21 United Microelectronics Corp. Nitridation process
US20090209854A1 (en) * 2008-02-19 2009-08-20 Parihar Shailendra K Biopsy method
KR101008994B1 (ko) * 2009-05-13 2011-01-17 주식회사 하이닉스반도체 듀얼 폴리 게이트의 산화막 형성 방법
US20110071391A1 (en) * 2009-09-24 2011-03-24 Speeg Trevor W V Biopsy marker delivery device with positioning component
JP5920684B2 (ja) * 2010-02-10 2016-05-18 株式会社東芝 半導体装置
US20110218433A1 (en) * 2010-03-02 2011-09-08 Speeg Trevor W V Biopsy Marker Delivery Device
US8450221B2 (en) * 2010-08-04 2013-05-28 Texas Instruments Incorporated Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls
US9054038B2 (en) 2011-01-25 2015-06-09 Applied Materials, Inc. Floating gates and methods of formation
FR2974446A1 (fr) * 2011-04-19 2012-10-26 St Microelectronics Crolles 2 Procédé de réalisation de l'isolant de grille d'un transistor mos
US10049881B2 (en) 2011-08-10 2018-08-14 Applied Materials, Inc. Method and apparatus for selective nitridation process
JP2013084918A (ja) 2011-09-27 2013-05-09 Hitachi Kokusai Electric Inc 基板処理装置、半導体装置の製造方法及びプログラム
US8741785B2 (en) * 2011-10-27 2014-06-03 Applied Materials, Inc. Remote plasma radical treatment of silicon oxide
WO2013074369A1 (en) * 2011-11-15 2013-05-23 Applied Materials, Inc. Method and apparatus for selective nitridation process
TWI492343B (zh) * 2012-11-02 2015-07-11 矽品精密工業股份有限公司 半導體基板及其製法
US9006064B2 (en) 2013-03-11 2015-04-14 International Business Machines Corporation Multi-plasma nitridation process for a gate dielectric
WO2014196107A1 (ja) * 2013-06-04 2014-12-11 パナソニック株式会社 薄膜トランジスタ素子とその製造方法及び表示装置
JP2016111294A (ja) * 2014-12-10 2016-06-20 住友電気工業株式会社 半導体受光素子を作製する方法
US10509008B2 (en) 2015-04-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Biological device and biosensing method thereof
CN109473439A (zh) * 2018-11-16 2019-03-15 上海华力微电子有限公司 一种sonos存储器件制备的集成工艺
CN113808939B (zh) * 2020-06-15 2023-09-22 长鑫存储技术有限公司 二氧化硅薄膜的形成方法和金属栅极的形成方法

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0006706B2 (en) * 1978-06-14 1993-03-17 Fujitsu Limited Process for producing a semiconductor device having an insulating layer of silicon dioxide covered by a film of silicon oxynitride
US4510172A (en) * 1984-05-29 1985-04-09 International Business Machines Corporation Technique for thin insulator growth
US4762728A (en) * 1985-04-09 1988-08-09 Fairchild Semiconductor Corporation Low temperature plasma nitridation process and applications of nitride films formed thereby
US4715937A (en) * 1986-05-05 1987-12-29 The Board Of Trustees Of The Leland Stanford Junior University Low-temperature direct nitridation of silicon in nitrogen plasma generated by microwave discharge
US5219773A (en) 1990-06-26 1993-06-15 Massachusetts Institute Of Technology Method of making reoxidized nitrided oxide MOSFETs
JP2652108B2 (ja) 1991-09-05 1997-09-10 三菱電機株式会社 電界効果トランジスタおよびその製造方法
US5726087A (en) 1992-04-30 1998-03-10 Motorola, Inc. Method of formation of semiconductor gate dielectric
US5445999A (en) 1992-11-13 1995-08-29 Micron Technology, Inc. Advanced technique to improve the bonding arrangement on silicon surfaces to promote uniform nitridation
US5596218A (en) 1993-10-18 1997-01-21 Digital Equipment Corporation Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation
JP3963961B2 (ja) * 1994-08-31 2007-08-22 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6136654A (en) * 1996-06-07 2000-10-24 Texas Instruments Incorporated Method of forming thin silicon nitride or silicon oxynitride gate dielectrics
US5926730A (en) * 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
JPH10313114A (ja) 1997-05-14 1998-11-24 Nec Corp 半導体装置の製造方法
JP3222404B2 (ja) * 1997-06-20 2001-10-29 科学技術振興事業団 半導体基板表面の絶縁膜の形成方法及びその形成装置
US6200651B1 (en) 1997-06-30 2001-03-13 Lam Research Corporation Method of chemical vapor deposition in a vacuum plasma processor responsive to a pulsed microwave source
US6020243A (en) 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6399445B1 (en) 1997-12-18 2002-06-04 Texas Instruments Incorporated Fabrication technique for controlled incorporation of nitrogen in gate dielectric
US6140024A (en) * 1997-12-31 2000-10-31 Texas Instruments Incorporated Remote plasma nitridation for contact etch stop
TW419732B (en) * 1998-07-15 2001-01-21 Texas Instruments Inc A method for gate-stack formation including a high-k dielectric
JP2000164870A (ja) * 1998-09-24 2000-06-16 Toshiba Corp 半導体装置及びその製造方法
US6114258A (en) 1998-10-19 2000-09-05 Applied Materials, Inc. Method of oxidizing a substrate in the presence of nitride and oxynitride films
US6380056B1 (en) 1998-10-23 2002-04-30 Taiwan Semiconductor Manufacturing Company Lightly nitridation surface for preparing thin-gate oxides
US6228779B1 (en) * 1998-11-06 2001-05-08 Novellus Systems, Inc. Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
US6450116B1 (en) * 1999-04-22 2002-09-17 Applied Materials, Inc. Apparatus for exposing a substrate to plasma radicals
TW410382B (en) * 1999-06-11 2000-11-01 United Microelectronics Corp Method of manufacturing forming metal oxide semiconductor transistor with raised source/drain
JP2001044419A (ja) * 1999-07-14 2001-02-16 Texas Instr Inc <Ti> 高ｋ誘電体を有するゲート積層の形成方法
US7125768B2 (en) * 1999-08-25 2006-10-24 Micron Technology, Inc. Method for reducing single bit data loss in a memory circuit
US6171911B1 (en) 1999-09-13 2001-01-09 Taiwan Semiconductor Manufacturing Company Method for forming dual gate oxides on integrated circuits with advanced logic devices
JP2001168323A (ja) 1999-12-06 2001-06-22 Mitsubishi Electric Corp 半導体装置の製造方法
TW520453B (en) * 1999-12-27 2003-02-11 Seiko Epson Corp A method to fabricate thin insulating films
US6413881B1 (en) * 2000-03-09 2002-07-02 Lsi Logic Corporation Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting product
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
US6649543B1 (en) * 2000-06-22 2003-11-18 Micron Technology, Inc. Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices
US6380104B1 (en) * 2000-08-10 2002-04-30 Taiwan Semiconductor Manufacturing Company Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer
US6800830B2 (en) * 2000-08-18 2004-10-05 Hitachi Kokusai Electric, Inc. Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication
US6933248B2 (en) * 2000-10-19 2005-08-23 Texas Instruments Incorporated Method for transistor gate dielectric layer with uniform nitrogen concentration
US6610615B1 (en) * 2000-11-15 2003-08-26 Intel Corporation Plasma nitridation for reduced leakage gate dielectric layers
JP3916565B2 (ja) * 2001-01-22 2007-05-16 東京エレクトロン株式会社 電子デバイス材料の製造方法
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6893979B2 (en) * 2001-03-15 2005-05-17 International Business Machines Corporation Method for improved plasma nitridation of ultra thin gate dielectrics
US6596570B2 (en) * 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
JP4369091B2 (ja) * 2001-07-18 2009-11-18 東京エレクトロン株式会社 基板処理方法
JP2003060198A (ja) * 2001-08-10 2003-02-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6555485B1 (en) * 2002-01-28 2003-04-29 United Microelectronics Corp. Method for fabricating a gate dielectric layer
JP4035600B2 (ja) 2002-05-22 2008-01-23 国立大学法人 東京大学 イマチニブに対する感受性の判定方法
EP1568075A4 (en) * 2002-11-08 2007-01-03 Aviza Tech Inc NITRURATION OF DIELECTRICS WITH A HIGH K CONSTATANT
DE10255936B4 (de) * 2002-11-29 2005-12-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Isolationsschicht und Verfahren zum Steuern einer Stickstoffkonzentration während der Herstellung der Isolationsschicht
US6962873B1 (en) * 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
US6821868B2 (en) * 2002-12-27 2004-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming nitrogen enriched gate dielectric with low effective oxide thickness
US6906398B2 (en) * 2003-01-02 2005-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor chip with gate dielectrics for high-performance and low-leakage applications
US6821833B1 (en) * 2003-09-09 2004-11-23 International Business Machines Corporation Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法

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