CN1864267A - 具有低饱和电压的双极晶体管 - Google Patents
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Abstract
一种具有小于约500mOhms.mm2的特定面积电阻的双极晶体管,包括定义集电极区域(2)的第一导电型的第一半导体区域。第二导电型的第二半导体区域定义基极区域(3)。第一导电型的第三半导体区域定义发射极区域(4)。金属层提供接触所述基极(3)和发射极区域(4)的触点。金属层具有大于约3μm的厚度。
Description
技术领域
本发明涉及一种具有低饱和电压的双极晶体管。
背景技术
对于双极晶体管来说,集射饱和电压是确定晶体管功率损耗及其效率的关键参数。在双极晶体管作为饱和开关操作的电路中,小基极电流用来导通非常大的集电极到发射极的电流,该电流的大小由电源电压和连接集电极或发射极的负载电阻决定。当双极晶体管饱和工作时,集电极至发射极的电压降减至称之为饱和电压VCE(sat)的最小值。人们希望把该饱和电压减至尽可能低的值,以便使晶体管内的功率损耗最小。
目前有多种减少双极晶体管的饱和电压的已知技术,或者通过确保发射极/基极结在整个结区域尽可能均匀偏置,或者通过减少从集电极触点到发射极触点的寄生串联电阻,来减少饱和电压。
为了导通晶体管,必需把某个最小电压偏置施加到结上。如果该结被不均匀偏置,则晶体管的结的某些区域将不导通,导致硅面积的无效使用。这增加了晶体管导通状态下的集电极与发射极间的晶体管电阻,导致饱和电压上升。
解决该问题的一个已知方案是提供经由发射极区域到基极区域的频繁接触,以减少这两个点之间的沿发射极层下面扩散的基极层的横向电阻。为了使发射极/基极偏置电压不在远离基极触点的发射极区域的中心降低,需要低横向电阻。然而,人们希望实现这种效果,而又不明显影响原来的发射极/基极结面积的百分比,因为这导致或者减少发射极/基极结面积,或者增大晶体管以保持相同的结面积。
人们已经知道减少基极区域的横向电阻的各种方案,比如创建经由发射极区域对基极区域的剥离接触。然而,这明显减小了发射极/基极结的面积,具有上述的缺点。一个更好的方案是提供经由发射极区域的孔接触基极区域的触点阵列。这些孔通常按小于75μm的间隔设置,提供了减少基极区域的横向电阻与保持发射极/基极结的尺寸之间的良好折衷。
晶体管的集电极触点与发射极触点之间的寄生串联电阻的减少可以以多种方式实现。在基片中使用低电阻率半导体(例如,小于5mOhm.cm),可以减少基片的电阻。此外,还可以减少基片和外延层的厚度。当确定外延集电极层的厚度时,要做出一种折衷,因为在晶体管截止状态,该层支持基极/集电极结周围的加宽耗尽层。层越薄,晶体管击穿电压就越低。在导通状态,耗尽区域崩溃,外延层正好代表寄生串联电阻,与其厚度成比例,增加了饱和电压。最佳外延层掺杂分布和厚度必需获得,以便实现击穿电压性能与饱和电压之间的最佳折衷。通过使用粗的和/或多根焊接线,可以减少连接发射极、基极和集电极触点印制线(track)的引线的电阻。
通过改变印制线的布局,可以更均匀地分布电流,和减少印制线上的电压降。减少连接发射极节点的印制线中的电压降是重要的,因为这些直接贡献到接通电阻上,减少了饱和电压。
含有减少饱和电压的某些或所有的上述技术的晶体管是众所周知的。可以根据晶体管的特定区域电阻测量晶体管的饱和电压。晶体管的特定区域电阻是功率半导体业界内众所周知的一个术语,涉及晶体管(在双极晶体管情况下,集电极至发射极电阻)的电阻乘以晶体管的面积之积。它是不同晶体管在电阻和面积方面进行比较的一个质量因数。饱和电压等于集电极至发射极电流乘晶体管的接通电阻。
具有低于500mOhm.mm2的特定面积电阻的低VCE(sat)晶体管现在广泛使用。不过,人们仍然希望发现减少双极晶体管的VCE(sat)的新方法。
发明内容
因此,本发明的目的是提供一种减少双极晶体管的特定面积电阻VCE(sat)的新方案。
根据本发明,这里提供了一种双极晶体管,包括:
定义集电极区域的第一导电型的第一半导体区域;
定义基极区域的第二导电型的第二半导体区域;
定义发射极区域的所述第一导电型的第三半导体区域;和
提供接触所述基极和发射极区域的触点的金属层;
其中,晶体管具有小于500mOhms.mm2的特定面积电阻
其中所述金属层具有大于约3um的厚度。
本发明人已经认识到,为了减少连接发射极触点的金属印制线的电压降,减少沿连接基极触点的金属印制线的电压降同样是重要的,因为这些用来减少施加到发射极/基极结的偏压,潜在地导致结被不均匀偏置。本发明已经显示,根据本发明增加低饱和电压晶体管的金属触点的厚度,可以提供饱和电压的进一步显著减少。也就是,利用本发明能够实现双极晶体管饱和电压的进一步减小,高于并超过了经由上述现有技术的应用实现的那些减小。这可以通过对现有晶体管的设计做最小改变来实现,从而通过对制造过程的最小改变,使该方案应用于现有的双极晶体管设计,因而使成本最小。
本发明提供了双极晶体管的饱和电压的明显减少,该双极晶体管具有小于500mOhms.mm2的特定面积电阻,具有小于3um厚的传统金属层。饱和电压的改善是以晶体管具有小于300mOhms.mm2的特定面积电阻来表明的。对于具有小于3um厚的金属层的小于200mOhms.mm2的特定面积电阻的晶体管,已经测出约为30%的饱和电压的额外减少。
最好是,金属层具有大于3μm的基本均匀的厚度,或者如果不均匀,则金属层具有大于3μm的最小厚度。通常,金属层将小于10μm厚。
在一个优选实施例中,发射极区域定义第一表面,扩展到各位置上的所述表面的基极区域由穿过发射极区域的小孔定义,所述金属层覆盖所述第一表面。这些小孔最好彼此相隔100μm以下。
本发明的其它目的和优点将会通过以下说明而变得清楚。
下面将参考附图,通过举例描述本发明的特定实施例。
所示的双极晶体管包括基片1、外延集电极层2、基极区域3、发射极区域4、氧化层5、基极金属触点6和发射极金属触点7。
晶体管建立于第一导电型的基片1。由第一导电型的集电极区域构成的外延层2被显示在基片1上。第二和相反导电型的基极区域3形成于外延层2,并且在基极区域3内,形成第一导电型的发射极区域4。在所示的本发明的最佳实施例中,除了在未发生发射极掺杂的层中的孔阵列之外,发射极区域4在一个基本连续层中形成于基极区域3的中心部分。其效果是,在基极区域3扩展到发射极区域4的表面的发射极区域4中存在圆孔的规则阵列。这些孔通常在矩形格栅中相隔近似75μm安置。确保对基极区域的规则接触,而又不明显减小发射极区域4/基极区域3结的其它图案也是可能的。
附图显示了双极晶体管的横断面视图,其中横断了该孔阵列的一行。
虚线8指示在远离基极区域3扩展到发射极区域4顶部的这些孔处,发射极区域4的覆盖在基极区域3上连续。在半导体层的顶部上,沉积硅氧化层5的图案,形成桥接发射极区域4与基极区域3之间的边界上边缘的图形。氧化层5之间散布的是基极金属触点6和发射极金属触点7,它们彼此由形成图案的氧化层5分离,并且分别与基极区域6和发射极区域7电接触。从远离发射极区域的基片的侧面得到集电极连接(连线)。
正如迄今所述的那样,双极晶体管完全是传统的,并且可以采用完全传统的方式制造。然而,根据本发明,接触基极和发射极区域的金属层触点比传统的厚,例如大于3μ厚。同样,发射极区域金属层触点可以是增加厚度的触点。
选择定义基极触点6和发射极触点7的金属层的厚度,以便确保发射极区域4/基极区域3结的更均匀偏置,以减小发射极金属触点7上的寄生电压降。减小通向不同基极区域触点的印制线中的电压降确保了施加到发射极/基极结上的偏压更均匀分布,这保证了晶体管上更均匀的电流密度,减小了饱和电阻。
本发明的发明人已经证明,这看起来是简单有利的,当应用于已经设计具有低VCE(sat)的双极晶体管(即,特定面积电阻小于约500mOhms.mm2)时,可以提供达到约30%的VCE(sat)的进一步减小。
本发明的双极晶体管通常将与上述的现有技术结合,以最小化饱和电压。在特定实施例中,接触基极区域的触点阵列被设计成,确保发射极/基极结保持均匀偏置。低电阻率的薄基片被利用,以及选择外延层厚度和掺杂分布以减小导通状态的晶体管的电阻。此外,设计金属印制线的布局,使其有助于减小其长度上的电压降,并且使用厚的和/或多根线构造连接印制线的焊接线。其效果是,双极晶体管的饱和电压被减小到现有技术独自可到达的水平之下。
对于没有为低饱和电压而最佳化的双极晶体管(即,特定区域电阻大于约500mOhms.mm2),即使根据本发明加厚金属触点,也显示出对饱和电压没有明显改善,因为与金属触点厚度相比,上述的其它参数对饱和电压影响更大。对于已经为低饱和电压而最佳化的双极晶体管,,增加金属触点的厚度就进一步减小了饱和电压。这种饱和电压的减小是渐进的并与金属触点和印制线的厚度成比例。对于4μm与6μm之间的金属厚度,已经观测到饱和电压得到明显改善,6μm是优选厚度,它把为低饱和性能而最佳化的双极晶体管的饱和电压降至更多的30%。
应当明白,本发明是结合特定的垂直双极晶体管进行描述的,该双极晶体管是通过现有已知技术为低饱和电压而最佳化的。可以把更厚的金属层应用于任何双极晶体管设计,其中期望减小金属触点的电压降,以便确保发射极/基极结的更均匀偏置。
本发明为电路效率依赖于饱和电压的任何功率开关应用提供了改进的性能。这有效地扩展到晶体管用于饱和而不是用作线性开关的所有应用。
本发明的进一步可能的修改和应用对于适当的熟练技术人员是显而易见的。
Claims (6)
1、一种双极晶体管,包括:
定义集电极区域的第一导电型的第一半导体区域;
定义基极区域的第二导电型的第二半导体区域;
定义发射极区域的所述第一导电型的第三半导体区域;和
提供接触所述基极和发射极区域的触点的金属层;
其中,晶体管具有小于500mOhms.mm2的特定面积电阻;
其中,所述金属层具有大于约3μm的厚度。
2、根据权利要求1所述的双极晶体管,其中金属层具有不小于4μm的厚度。
3、根据上述权利要求任一项所述的双极晶体管,其中金属层具有不小于6μm的厚度。
4、根据上述权利要求任一项所述的双极晶体管,其中发射极区域定义第一表面,基极区域扩展到位于由通过发射极区域的小孔所定义的位置中的所述表面。
5、根据权利要求4所述的双极晶体管,其中邻近的小孔彼此相隔的距离小于100μm。
6、一种基本上如以上权利要求定义的双极晶体管,如附图所示。
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GBGB0318146.8A GB0318146D0 (en) | 2003-08-02 | 2003-08-02 | Bipolar transistor with a low saturation voltage |
GB0318146.8 | 2003-08-02 |
Publications (1)
Publication Number | Publication Date |
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CN1864267A true CN1864267A (zh) | 2006-11-15 |
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ID=27799699
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CNA2004800287699A Pending CN1864267A (zh) | 2003-08-02 | 2004-07-12 | 具有低饱和电压的双极晶体管 |
Country Status (7)
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US (1) | US7923751B2 (zh) |
EP (1) | EP1654766A1 (zh) |
JP (1) | JP2007501511A (zh) |
KR (1) | KR101045335B1 (zh) |
CN (1) | CN1864267A (zh) |
GB (1) | GB0318146D0 (zh) |
WO (1) | WO2005015641A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740383B (zh) * | 2009-12-20 | 2011-07-20 | 锦州七七七微电子有限责任公司 | 集成化pnp差分对管的制作方法 |
CN108281480A (zh) * | 2018-02-09 | 2018-07-13 | 哈尔滨工业大学 | 一种同时产生电离和位移缺陷信号的器件及其制备方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7875513B2 (en) * | 2006-04-26 | 2011-01-25 | Fabio Pellizzer | Self-aligned bipolar junction transistors |
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JPS54120587A (en) * | 1978-03-10 | 1979-09-19 | Fujitsu Ltd | Transistor |
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JPS5778173A (en) | 1980-11-04 | 1982-05-15 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JPH0770539B2 (ja) * | 1985-02-01 | 1995-07-31 | サンケン電気株式会社 | トランジスタ |
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JPS62143466A (ja) * | 1985-12-18 | 1987-06-26 | Matsushita Electronics Corp | 半導体装置 |
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JPH0562989A (ja) * | 1991-08-31 | 1993-03-12 | Nec Corp | 半導体装置の電極構造 |
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-
2003
- 2003-08-02 GB GBGB0318146.8A patent/GB0318146D0/en not_active Ceased
-
2004
- 2004-07-12 WO PCT/GB2004/003018 patent/WO2005015641A1/en active Search and Examination
- 2004-07-12 JP JP2006522386A patent/JP2007501511A/ja active Pending
- 2004-07-12 EP EP04743359A patent/EP1654766A1/en not_active Ceased
- 2004-07-12 CN CNA2004800287699A patent/CN1864267A/zh active Pending
- 2004-07-12 US US10/566,813 patent/US7923751B2/en not_active Expired - Lifetime
- 2004-07-12 KR KR1020067002261A patent/KR101045335B1/ko active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740383B (zh) * | 2009-12-20 | 2011-07-20 | 锦州七七七微电子有限责任公司 | 集成化pnp差分对管的制作方法 |
CN108281480A (zh) * | 2018-02-09 | 2018-07-13 | 哈尔滨工业大学 | 一种同时产生电离和位移缺陷信号的器件及其制备方法 |
CN108281480B (zh) * | 2018-02-09 | 2022-03-04 | 哈尔滨工业大学 | 一种同时产生电离和位移缺陷信号的器件及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US7923751B2 (en) | 2011-04-12 |
US20060208277A1 (en) | 2006-09-21 |
KR101045335B1 (ko) | 2011-06-30 |
GB0318146D0 (en) | 2003-09-03 |
EP1654766A1 (en) | 2006-05-10 |
WO2005015641A1 (en) | 2005-02-17 |
KR20060080915A (ko) | 2006-07-11 |
JP2007501511A (ja) | 2007-01-25 |
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