CN1855483A - 集成无源器件 - Google Patents

集成无源器件 Download PDF

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Publication number
CN1855483A
CN1855483A CNA2006100747566A CN200610074756A CN1855483A CN 1855483 A CN1855483 A CN 1855483A CN A2006100747566 A CNA2006100747566 A CN A2006100747566A CN 200610074756 A CN200610074756 A CN 200610074756A CN 1855483 A CN1855483 A CN 1855483A
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China
Prior art keywords
ipd
mcm
substrate
wafer
chip
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CN100585849C (zh
Inventor
安东尼·M·基乌
伊农·德加尼
查利·春雷·高
孙昆泉
孙立国
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Sychip Inc
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Sychip Inc
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Abstract

本发明描述了一种包含集成无源器件(IPD)作为载体基板(IPD MCM)的多芯片模块(MCM)。寄生电气干扰通过从该表面省去金属、或选择性地使用远离敏感器件元件的MCM的部件中的金属而在IPD的一个或两个界面被控制。这些敏感的器件元件主要是模拟电路元件，尤其是RF电感器元件。在IPD设计中，该敏感元件被与其它元件隔离。这允许选择性金属方法的实现。这也使得在IPD基板顶部的寄生干扰通过IC半导体芯片和IC芯片的接地面的选择性放置而被减小。在本发明的IPD MCM的优选实施例中，该IPD基板是多晶硅，以进一步减小RF干扰。这些组装该模块的不同的方法可以适合保持整体厚度在1.0mm之内。

Description

集成无源器件
技术领域
本发明涉及集成无源器件(IPD)，尤其是以多芯片模块(MCM)形式的集成电路(IC)、在该电路中主要元件是IPD芯片。
背景技术
(本节中所包含的部分技术资料可以不必是现有技术)
现有技术中的射频(RF)电子电路使用大量的无源器件。这些电路中的许多被用在手持无线产品中。因此，无源器件和无源器件电路的小型化是RF器件技术中的一个重要的目标。
由于至少两个原因，使在有源硅器件的级别上的无源器件的集成化和小型化不能实现。第一，迄今为止，典型的无源器件使用不同的材料技术。但是，更根本地，许多无源器件的尺寸是该器件频率的函数，这样尺寸固然地相对大。但是，仍存在着制造出更紧凑的以及更有面积效率的IPD的不懈要求。
已经取得了显著的进步。在许多情况下这些涉及表面贴装技术(SMT)。利用表面贴装技术，常规地制造包含大量无源元件的小基板。
在制造集成无源器件网络方面的近来进展包括薄膜(thin film)技术，其中电阻器、电容器和电感器作为在合适的基板上的集成薄膜器件而被建立。例如参见美国专利No.6,388,290。这种进展展示了作为无源器件技术中的下一代集成的希望。然而，正如基板的材料和特性(纯单晶硅)已经成为有源器件技术成功的关键那样，显然作为IPD集成发展同样是重要的。由于无源薄膜器件直接形成在基板上，因此在基板和无源器件之间的电气干扰成为主要的关注点。美国专利申请系列号10/835,338涉及这些问题，并且描述和要求了一种IPD基板，其提供了结合与期望的电介质特性的加工优点。这个基板也能够被制造得较薄，以减小IPD的外形。
当从小型化的观点来看通常关心的是所谓的器件或电路的“覆盖区”(footprint)时，随之而来的目标是减小厚度。减小IC的覆盖区的通常方法是在一个MCM中叠置两块或更多的芯片。在MCM技术中，封装芯片的厚度通常与覆盖区一样重要。
由于元件、尤其是电感器元件之间的RF干扰的问题，通常使小型化RF电路的MCM方法无效。用于RF电路和IPD通常的方法是在基板上横向扩展器件。通常IPD基板大于普通半导体IC，因此为了实现一个包含IPD基板的MCM，该IPD基板成为用于MCM的载流子基板的合理的选择物，即，半导体芯片将被置于IPD基板的顶部。然而，在IPD基板上叠置器件尤其带来有问题的干扰。在这种MCM配置中的IPD基板面临两个RF场干扰的问题，一个是IPD基板被安装的基板上，另一个是IPD基板顶部的IC芯片。
发明内容
我们已经研制出一个包含作为载体基板(carrier substrate)的IPD的MCM(IPD MCM)。寄生电气干扰在IPD的一个或两个界面被控制，或者通过从该界面除去金属、或选择性地使用在远离敏感器件元件的MCM的部件中的金属。该敏感器件元件主要是模拟电路元件，尤其是RF电感器元件。在IPD设计中，该敏感元件与其它元件隔离。这允许执行选择性金属方案。这也允许通过IC半导体芯片选择性放置来降低在IPD基板顶部的干扰。
在本发明的IPD MCM的优选实施例中，IPD基板是上述作为参考的申请所描述的和所要求的基板。该基板本质上地减小了RF干扰，以及能被制造得薄以减小该MCM的外形。
附图说明
图1示出一种用于制备高电阻率的IPD基板的单晶硅原始晶片；
图2示出具有多晶硅沉积的原始晶片；
图3是示出了超过500个用于构建薄膜IPD的IPD位置的本发明的多晶硅晶片的视图；
图4是示出置于常规基板上的常规的SMT元件的典型IPD的示意性剖面图；
图5是在图3的基板的一个位置上的用于IPD制造的薄膜方法的示意图；
图6是在除去单晶硅处理后的制造好的IPD的视图；
图7是示出一个IPD的实施例的电路图；
图8示出具有置于IPD上的有源IC芯片的IPD；
图9示出具有IPD载体基板和半导体IC芯片的MCM的另一视图；
图10示出MCM的实施例，该MCM具有IPD载体基板、相对于敏感RF元件有选择地放置的半导体IC芯片和从下部IPD界面除去的金属；
图11示出具有IPD载体基板的MCM的可选实施例；
图12是完全装配好的IPD MCM产品的视图。
具体实施方式
下面的细节描述的第一部分涉及用于IPD MCM的优选基板。
图1是原始晶片11的视图。这是从晶块切割下来的单晶硅晶片，是一种在世界范围内的大量用于IC器件制造的晶片。硅晶片被以多种尸寸制造，但是通常该晶片的直径越大，潜在器件费用就越低。当前，硅晶片的有效直径可达12英寸。关于现有技术中的12英寸的硅晶片，该尺寸将在接下来的描述中被用作例子，可以理解的是，更小的晶片，例如6″或8″也是可用的。
在晶片制造设备中，在锯和抛光该晶片后，每一晶片接受质量控制，其中晶片被测量以符合一致的物理尺寸和电气特性的严格标准。通常带有碎片或划痕的晶片将被拒绝。具有过量的或不一致的电导率的晶片将被拒绝。在许多情况下这些被拒绝的晶片被丢弃，以及有时被称作“垃圾晶片”。在此说明书中以及在接下来的权利要求中，“拒绝的”晶片包括从晶块切割下来、被一个或多个物理或电气测试测量、以及由于测试失败而被拒绝的晶片。拒绝的晶片具有相对低的商业价值。一些可以重复利用；一些可以被修复。例如，由于存在于加工期间的缺陷一些晶片被拒绝。这些晶片具有被抛光以除去缺陷结构的潜力，并用于制造。这种晶片也被认为是拒绝晶片。拒绝晶片可以被认为具有的价值小于50％、以及更典型地小于10％的可被接受的晶片的价值。回收的或重复利用的晶片也是低成本IPD基板的可选原料。
根据本发明的一个方面，单晶硅晶片被用作处理晶片以制造多晶硅晶片。可以理解，当由于经济的原因使拒绝晶片是可以选择的晶片时，任何合适的单晶硅晶片都可以使用。在此工艺中，单晶硅晶片被牺牲。作为处理晶片，单晶硅晶片具有重要特性。即使物理上薄(例如200-500微米)，它也在物理上相当坚固，并且能被处理和加工。在大的面积上其非常平。它具有高度抛光的均匀的光滑表面。并且其兼容硅晶片制造工艺与工具。
使用硅晶片作为基板晶片时，厚的多晶硅层12和13沉积在如图2所示的晶片11的两侧。可选地，多晶硅可以仅沉积在一侧。但是，该用作IPD基板的多晶硅层需要相对的厚，例如至少50微米，最好100-300微米。我们发现具有该厚度的层，当沉积在单晶硅基板上时，具有高的应力以及易于物理变形。既然本发明的IPD加工需要平面度，那么最好避免基板显著的变形。我们已经发现通过沉积多晶硅在单晶晶片的两侧，应力会均衡。因此，各层最好(但不是必须)具有等于图2所示的形成的厚度。该最后得到的晶片相对厚，并且非常坚固。为了进一步减小在合成晶片中的应力，该合成晶片可以被热处理。但是，应该注意热处理的应用，由于热处理促进晶粒增长，并且希望得到细的晶粒结构，原因将从下述论述中变得明白。
图2的子组件，例如三层合成基板，可以通过基板制造厂商作为独立产品而生产。该产品的特性，如上述的IPD基板一样，是合成的平面性的三层。
最终希望的基板产品是不具有单晶晶片的多晶硅基板，如将在下面所述。但是，即使该图2中所示的合成晶片不是最终的产品(例如在最终的产品中不存在单晶晶片)，执行至少一些在合成晶片上的加工也是方便的。该加工过的晶片可以在后面的步骤中被变薄以除去多晶硅层中之一，以及该单晶层，留下多晶硅层作为最终的IPD基板。
固有的多晶硅基板的重要属性是高的电阻率。多晶硅的特性决定于晶粒结构，其中该层或本体由许多硅晶粒所构成，由晶粒边界所分开。该晶粒边界电气表现出作为复合中心，急剧地减少本体中自由载流子寿命。依据电气表现，该特性从单晶硅中区别出多晶硅。然而单晶硅是半导体，在多晶硅中的大量的晶粒边界以无掺杂的或本征的状态使其成为绝缘体。多晶硅的电导率部分地是晶粒边界数量的函数，或是该晶粒结构细度的函数。因此非常细的晶粒多晶硅可具有相对高的电导率。多晶硅可以被容易地生产具有大于10KOhm-cm的电导率。在本发明的上下文中，期望得到大于0.1KOhm-cm的电导率值，优选的大于1KOhm-cm的值。
用于制造多晶硅层的方法优选是低压化学汽相沉积(LPCVD)。这种方法以及实施该方法的CVD设备广泛地应用在工业中。简要地，通常用于CVD多晶硅的方法包括在合适温度下的硅烷的高温分解，例如550-650℃。多晶硅几乎被用于每一MOS晶体管的制造，因而其是众所周知的最常见的的工业原料之一。显然，多晶硅的电气和物理特性也是众所周知的。虽然其固有的是高电阻率，如上所述，但是其通常通过在制造过程中的离子注入来减小电阻率，以用于IC应用。很少以其固有形式使用。厚的、大面积的多晶硅层已经被使用在太阳能电池或光电池中。在此，该多晶硅层又通常被注入离子以形成二极管结构。
在下述的本申请中，多晶硅基板被以其固有状态应用，并且希望整个基板的一致的高的电阻率的特性。
既然CVD多晶硅技术已经如此好的发展，那么CVD就是形成多晶硅层12和13的最佳选择。但是，其它的方法也被发现是可用的。例如，已知的多晶硅的电子束蒸发的方法。任何适合用于形成厚的、大面积的、低电阻率的多晶硅基板层的替代方法都在本发明的范围内。
此处描述的IPD的制造方法目的在于晶片规模器件的制造。在该方法中，大量的已完成的、或几乎要完成的器件在多晶硅晶片上制造。在制造基本上完成之后，该晶片被切成IPD芯片。当该晶片的尺寸增大以及IPD芯片尺寸的减小时，晶片级的制造变得更加有吸引力。图3示出12英寸的晶片31，其适于提供超过500个器件位置33。(为了简化，没有示出该晶片平面。)每一位置大约都是厘米见方，足够大以容易地容纳IPD。
晶片规模制造的效率在利用薄膜制造来形成无源器件的方法中成倍增加。通常现有技术的方法，甚至在晶片级，会放置和附着分立的无源元件到该晶片基板。通常这利用表面贴装技术(SMT)而完成。图4示出应用到图3中示出的较早参考的美国专利No.6,388,290的IPD电路的这种方法。该电路严格地并非IPD，，因为其包括有源元件，例如MOS晶体管41。但是，因为下面的显而易见的原因，其是有用的展示。该电路可以被看作具有有源部分和无源部分的混合电路。此处我们主要注意无源部分，即包含四个电感器42和三个电容器44的部分。作为可选择的，该部分可以被作为IPD制造。尽管图3的电路在此处是可用的，并且在下面作为载体以展示本发明的技术，但是利用本发明可以作出各种各样的电路。另一例子，从高-Q观点来看更需要的一种，参见会刊1994IEEE MULTI-CHIP MODULE CONFERENCE MCMC-94，PAGES 15-19，结合在此作为参考。
薄膜无源元件可以由各种薄膜技术形成。这些技术被很好地发展，细节不需要在此重复。例如参见公开于2000年6月13日的美国专利6,075,691和公开于1999年12月21日的美国专利6,005,197。后者专利叙述了一种用于PCB板的多层结构，其能够简单地适用于此处所述的本申请。形成薄膜无源器件的方便的途径是，将无源器件形成在使用一层或多层(通常为多层)的基板上，沉积在该基板上。
用于制造单个无源元件或互连的无源元件的结合体的薄膜方法总体用图5所表示，其中多晶硅基板在51处示出，带有生长的氧化物层52。电阻器体54，由第一级金属形成，具有触点55和56，以及带有触点59的下部电容器板58，两者都包括埋入级。最后形成的带有未示出的触点的上部电容器板60和电感器螺线管61。该结构被聚酰亚胺层63所保护。
图5的三层基板结构51非常厚，其减小了在加工期间的断裂的危险和其它的损坏。在无源电路元件的制造以及IPD完成之后，基板51被变薄以除去下部的多晶硅层和单晶硅层。最终的IPD结构在图6中示出。该优选的变薄的步骤使用化学机械抛光。这种众所周知的加工结合带有化学蚀刻的磨蚀抛光。KOH或合适的替代蚀刻剂用在磨蚀浆中。该合成的晶片被变薄使得仅仅顶部的多晶硅层或部分的顶部多晶硅层被保留。由于单晶层是相对导电的，因此强烈推荐除去全部的单晶层。本发明的目标是提供一种高绝缘性的基板，来作为IPD的适宜平台。
因为单晶层(以及加入的多晶硅层)提供对多晶硅顶层(IPD层)的有效处理，因此IPD层最初可以相对的薄。在当今的IC技术中，在晶片制造完成之后变薄原始晶片是常见的。在许多情况下，基板被有意地做厚以经受处理和加工，在加工中带有变薄步骤以减小器件的外形。在此所述的方法中，IPD层的厚度最初可以与最终的基板厚度具有大致接近的尺寸。该厚度优选50-200微米。
图4的IPD被示出为根据图7中的本发明的一个实施例实现。该IPD形成在图3中示出的一个或多个位置33。多晶硅基板71被示出带有薄膜电感器Lg1、Lg2、LS和LD以及电容器C1、C2和CD。MOS晶体管72以虚线示出，因为尽管其是电路图的一部分时，其并不形成在IPD中。图7布置的的电路是有目的的从图3的电路图设计改变得到的。该电路及该设计的目的在于展示一种具有无源元件的典型类型的电路。它是来自较早参考的现有技术的电路的实施例。关于其效用在此没有作出任何评述。
图7中的布置被设计为所有的电感器元件组成在一起。众所周知电感器元件尤其对环境条件敏感，例如寄生信号。这种认识被应用在图8的示出的有源/无源模块的设计中。多晶硅基板71，带有图7中示出的IPD，具有有源IC芯片81倒装安装于所示出的IPD的顶部。该有源IC芯片的一部分是晶体管72。在此实施例中互连被示出为焊料凸块用于电气互连S、D、G、Lgs、VDS、Pin、Pout、gnd。板外互连的位置(未示出)可以被提供在IPD基板71上。如图7中示出的成组的电感器器件的一个目的在图8中是显然的。有源IC芯片被有意定位使得不会覆盖该敏感的电感器元件。这样，堆叠基板的布置可以有效地节省空间并提供紧凑的器件模块，不用对电感元件的实现妥协。
图9是IPD MCM的另一视图，其中置于印刷电路板(PCB)92上的IPD91被示出。所示IC芯片93安装于IPD上。为了简化仅示出一个IC芯片。通常有不止一个。这些IC芯片可以是模拟器件、数字器件、混合信号器件、RF器件、和/或基于开关或振荡器的微电子机械系统(MEMS)。
将从下述的讨论中变得清楚，即使敏感的RF元件在如上述的在IPD中被隔离，其它不利的因素仍然要被论述。这些与IPD中的敏感元件以及IPD附近的外部感应(主要是金属体)的寄生干扰有关系。这些不利的影响随着IPD芯片尺寸(主要是厚度)的减小而严重。结合本发明的这个方面与上述的便利，全部发明的目的是减小IPD MCM的厚度。
常规的安装MCM到PCB的手段是焊接。再次参考图9，示出焊接接合层94，带有PCB接地面95。IPD的上表面被接地面和用于互连该IC芯片的金属轨道所覆盖，通常放置在两级上。这些在图中以层96表示，并且通过焊接凸块97连接到IC芯片。优选的焊接连接不同于常规的倒装芯片连接，在该倒装芯片连接中倒装片与基板之间的距离被保持在最大以保持可靠性，例如典型地70到120μm。优选的焊接连接具有小的凸块高度，在70μm以下，以调节IPD和IC之间的平面度变化。由于有源IC和IPD之间的热膨胀系数近似，不用担心变短距离而影响焊点的可靠性。而且，距离的减小也有助于减小模块的整体厚度。利用这种包括过模制的使得厚度变小的方法，例如整体厚度不超过1.0mm。该距离的减小也减小了寄生电阻和电感，以进一步改善RF电路的性能。除了焊接之外，其它通常所知的方法，例如金到金、金到铝以及导电粘合剂也都在本发明的范围内。
引线接头98将该接地面和轨道连接到PCB上的互连99。除了引线接头，还可以在IPD上蚀刻孔，该孔连接IPD顶面和底面上的金属轨迹。这种蚀刻加工是通常实行的MEMS制造加工。该带有通孔的IPD通过常规的倒装片组装加工被附着到基板。该通孔连接能进一步减小IPD和基板之间的互连距离。
本领域技术人员可以理解在图9中示出的组件，和其它图中的一样，也被封装在聚合物外壳中。该塑料外壳可以是塑料过模制体，如常规的器件那样、或者可以是塑料的腔封装或其它合适的保护封装。
显然在带有MCM配置的IPD中的敏感RF元件，例如示意性示出的电感器100，易受由覆盖IPD两侧的金属引起的杂散电容的损坏。
图10示出类似于图9的IPD MCM的实施例，但是除去了电感器100下边和上边的金属。容易理解到的电感器100表示IPD一部分，其中一个或多个RF敏感元件被选择性地放置，并且与其它、主要数字、电路和电路元件分离。IPD中的电感器元件可以被结合在IPD基板上象其它元件、象在RF滤波器电路中的同一位置中。但是，通常电感器元件在那些电路中从寄生电场的观点而得到关注。
在IPD下面的金属，在图9中在94示出，保持在IPD的一部分的下面，但是在101被从IPD的包含敏感元件100的部分的下面除去。在IPD该部分下面的金属被不导电的粘性剂附着层所替代。该不导电的粘性剂优选地为电绝缘导热单元片附着材料，例如注有环氧树脂的铝。
此外，在IPD顶部的金属，在图9中的96示出，已经被从覆盖的IPD的敏感元件的区域除去，例如元件100。该金属仍旧在96a，在IPD中的数字元件上。引线接头被做成触点垫片102。在示出金属层96和96a被设为接地面的实施例中，通常是连续的金属板。一些数量的用于连接IC上的焊料凸块的金属跑线可以在IPD的敏感元件上被容忍。因此，多个IC芯片的一个可以被放置在这些区域上。然而，在这些区域中接地面要被避免。优选地，布局被设计为没有金属沿着敏感元件上的表面延展。
应该指出的是这些权宜处理的任一或全部都可以改善IPD MCM的电气性能。
图11示出与图10类似的实施例，在IPD和PCB之间的全部金属层被除去，并被不导电的粘合层105所代替，由于在IPD下面的接地面不再被使用，因此图9中的95示出的金属接地面也被除去。最后得到的结构是带有IPD的基板附着到带有不导电的附着层的基板，该IPD具有主要包含RF元件的第一部分和主要包含非RF元件的第二部分，该IPD具有在第一部分上的第一表面以及在第一部分下的第二表面，至少一个数字IC芯片安置于IPD的第二部分上，IPD的第一和第二表面无金属。该IPD的不包含RF敏感器件的部分也可适用于支撑MEMS器件，例如MEMS振荡器或MEMS开关。
仔细观察图11的实施例将发现，金属层从PCB上除去使得IPDMCM的整体高度被该层的厚度减小。虽然这是一种小的改变，但是从商用的角度来看是显著的。商用IPD MCM已经被示例具有与图11示出的设计类似的设计，其从PCB的底部到封装物的顶部的全部封装高度是1.000mm。该器件部分由于其小的外形而被希望具有商业竞争性。
图12示出总体在111示出的完全装配的IPD MCM产品的剖面图。PCB112被提供在顶部和底部两部分上都具有金属化层113。利用上述的选择之一，IPD在114示出并且通过单元片附着材料116被附着到PCB上。该IPD以引线接头电气互连到PCB上，引线接头之一在118示出。该引线被焊接到PCB的顶层。金属通路120横穿将PCB顶部的金属与底部的金属连接起来。该IPD MCM可以简便地放置并连接到系统基板。IC芯片122被示出为倒装附着到IPD114。焊料凸块123附着并连接该IC芯片到IPD上的金属跑线。该IC芯片可以是数字或RF IC芯片。它通常为IC芯片提供接地面。但是，根据上述提及的原则，接地面被故意地从覆盖电感器元件的IPD区域上省去。在优选的情况下，如果IC芯片被置于电感器元件上，则该接地面从该区域省去。并且，用于该IC芯片的I/O互连优选地但不是必须地置于IC芯片的边缘附近，该芯片不在任何电感器元件上面。
在具有直接在有源IC下方的的接地面的PCB区域中，一个或多个热通道可以置于PCB的顶部和底部金属面之间以散去在运行期间由IPD MCM产生的热量。由有源IC产生的热量从IC进入IPD，到填充氧化铝的单元片附着材料，到顶部的接地面，到热通道(133)，到底部接地面，并由该系统板所散发掉，IPD MCM置于该系统板上。这不同于常规中在IC下伸展开的接地面是持续面的作法。但是，由于需要容纳IPD中的电感器元件，在某些RF元件下没有金属面。因此，该接地面可以是不连续的，并且能被分成各个小块有策略地置于产生热量的IC下。
由于太大而不能在IPD中实现的无源元件，例如电容器、电感器和电阻器，能以常规的表面贴装工艺置于基板上。
组装的最后部分是提供保护外壳给IPD MCM。图12示出封装物127，通常的保护元件由聚合物构成，通常模制在电气组件上。可选地，该保护外壳可以是金属罐、塑料腔或任何合适的保护外壳。这在本领域是众所周知的。
除了提供小型化的无源元件，该IPD也用作IC制造工艺和PCB制造工艺之间的技术桥梁。前沿的ICs可以被制造为特征尺寸在1μm到.065微米(μm)，使用节距从30到300μm的连接焊垫。IPD可以以较不先进的IC工具制造，例如薄膜溅射以及蚀刻，特征尺寸是1到20μm。这些IPD特征能够无缝地适合最小节距的IC连接焊垫。相反，PCB线和轨迹以数十μm制造，使用电镀和蚀刻技术，其通常可以适合60至300μm的大节距的的连接焊垫。具有大连接焊垫节距的IC其表面积大于具有较小连接焊垫节距的IC。通常IC的连接焊垫而并非门和元件的数量是IC整体尺寸的策动因素。因此，如果IC以总体特征尺寸直接连接到PCB基板上，与其表面积成正比的IC的花费就会上升。但是，使用比PCB具有更精细的特征尺寸以及由于简化了制造步骤比IC具有每单位面积更低花费的IPD，在IC的精细特征能力和PCB的总体特征能力之间架起桥梁是一种成本合算的方式。因此，IPD充当了IC和基板之间的成本合算机制的界面。其一方面可以如图12示意性看出，其中示出的IPD MCM以焊接球132附着到系统级板131上。比较焊接球132的节距与焊料凸块123的节距可以看出上述的转变。如上述的，从PCB112的底面到封装物或过模制127的顶部的该封装的总体高度小，小于1.2mm，优选1.0mm或更小，。
对本领域的技术人员而言存在本发明的各种附加的改变。任何依靠该原则偏离说明书的特别教导以及提出的等同物及对现有技术的贡献都被看作落入本发明所描述的和要求的范围之中。

Claims (10)

1、一种集成无源器件多芯片模块(MCMIPD)，包括
a.基板，
b.附着到具有附着层的基板的IPD，其中附着层的至少一部分是不导电的。
2、权利要求1的IPD MCM，其中整个附着层是不导电的。
3、权利要求1的IPD MCM，其中附着层的第一部分是不导电的，而附着层的第二部分是导电的。
4、权利要求1的IPD MCM，其中IPD具有包含至少一个电感器元件的第一部分和包含至少一个数字元件的第二部分，并且其中在IPD的第一部分下面的附着层的部分是不导电的，而在数字元件的下面的附着层的部分是导电的。
5、权利要求4的IPD MCM，其中该IPD MCM进一步包括至少一个置于该IPD顶部的集成电路芯片(IC)。
6、权利要求4的IPD MCM，其中该IPD的顶部被选择地覆盖有接地面。
7、权利要求6的IPD MCM，其中该接地面被选择地仅置于IPD的第二部分上。
8、权利要求1的IPD MCM，其中附着层的不导电部分是电气绝缘导热单元片附着材料。
9、权利要求1的IPD MCM，其中该IPD包括多晶硅晶片基板，在多晶硅晶片上有至少一个薄膜无源器件。
10、权利要求1的IPD MCM，其中包括IPD的厚度、IC芯片的厚度以及保护体的厚度而测得的IPD MCM的整体厚度小于1.2mm。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101894861A (zh) * 2009-05-22 2010-11-24 联发科技股份有限公司 半导体装置
CN101519183B (zh) * 2008-01-31 2011-09-21 台湾积体电路制造股份有限公司 具有集成电路管芯的微机电系统封装
CN103295996A (zh) * 2012-06-29 2013-09-11 上海天马微电子有限公司 封装基板及其制作方法

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041122A (ja) * 2004-07-26 2006-02-09 Shinko Electric Ind Co Ltd 電子部品内蔵要素、電子装置及びそれらの製造方法
KR100660604B1 (ko) 2005-04-21 2006-12-22 (주)웨이브닉스이에스피 금속 박편을 이용한 수동 소자 및 반도체 패키지의제조방법
FR2888460B1 (fr) * 2005-07-08 2010-12-24 Valeo Vision Dispositif d'eclairage et/ou de signalisation pour vehicule, associe a une electronique de haut niveau d'integration
US20070066085A1 (en) * 2005-09-21 2007-03-22 Hsien-Che Teng Method of fabricating dielectric layer
US20070065964A1 (en) * 2005-09-22 2007-03-22 Yinon Degani Integrated passive devices
US8791006B2 (en) * 2005-10-29 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming an inductor on polymer matrix composite substrate
US8669637B2 (en) * 2005-10-29 2014-03-11 Stats Chippac Ltd. Integrated passive device system
US8158510B2 (en) 2009-11-19 2012-04-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD on molded substrate
US8409970B2 (en) 2005-10-29 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of making integrated passive devices
US8258599B2 (en) * 2005-12-15 2012-09-04 Atmel Corporation Electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US20070138628A1 (en) * 2005-12-15 2007-06-21 Lam Ken M Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US7932590B2 (en) * 2006-07-13 2011-04-26 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements
US7355264B2 (en) * 2006-09-13 2008-04-08 Sychip Inc. Integrated passive devices with high Q inductors
US8861214B1 (en) * 2006-11-22 2014-10-14 Marvell International Ltd. High resistivity substrate for integrated passive device (IPD) applications
JP5103245B2 (ja) 2008-03-31 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置
KR101479509B1 (ko) * 2008-08-29 2015-01-08 삼성전자주식회사 반도체 패키지
US8018027B2 (en) * 2009-10-30 2011-09-13 Murata Manufacturing Co., Ltd. Flip-bonded dual-substrate inductor, flip-bonded dual-substrate inductor, and integrated passive device including a flip-bonded dual-substrate inductor
US8552517B1 (en) * 2010-09-14 2013-10-08 Amkor Technology, Inc. Conductive paste and mold for electrical connection of photovoltaic die to substrate
US8486796B2 (en) 2010-11-19 2013-07-16 International Business Machines Corporation Thin film resistors and methods of manufacture
US8624353B2 (en) * 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US8506826B2 (en) * 2011-08-02 2013-08-13 Harris Corporation Method of manufacturing a switch system
US8951893B2 (en) 2013-01-03 2015-02-10 International Business Machines Corporation Fabricating polysilicon MOS devices and passive ESD devices
TWI499013B (zh) * 2013-01-22 2015-09-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US10425724B2 (en) 2014-03-13 2019-09-24 Starkey Laboratories, Inc. Interposer stack inside a substrate for a hearing assistance device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117250A (ja) * 1982-12-24 1984-07-06 Hitachi Micro Comput Eng Ltd 半導体装置
JP2944768B2 (ja) * 1991-02-14 1999-09-06 ティーディーケイ株式会社 集積回路部品とその製造方法
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JP2565300B2 (ja) * 1994-05-31 1996-12-18 日本電気株式会社 半導体装置
JPH0841294A (ja) * 1994-07-27 1996-02-13 Shin Etsu Chem Co Ltd 絶縁性樹脂ペースト及び半導体装置
JP2591499B2 (ja) * 1994-10-21 1997-03-19 日本電気株式会社 半導体装置
JP2734424B2 (ja) * 1995-08-16 1998-03-30 日本電気株式会社 半導体装置
JP3874115B2 (ja) * 1997-03-24 2007-01-31 セイコーエプソン株式会社 半導体装置
TW392392B (en) * 1997-04-03 2000-06-01 Lucent Technologies Inc High frequency apparatus including a low loss substrate
JPH11233712A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びその製法とそれを使った電気機器
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
WO2000039853A1 (de) * 1998-12-23 2000-07-06 Infineon Technologies Ag Vertikal integrierte halbleiteranordnung
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
TW503538B (en) * 2000-12-30 2002-09-21 Siliconware Precision Industries Co Ltd BGA semiconductor package piece with vertically integrated passive elements
JP2002319658A (ja) * 2001-04-20 2002-10-31 Matsushita Electric Ind Co Ltd 半導体装置
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
JP2004214258A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
KR100543729B1 (ko) * 2004-03-24 2006-01-20 아바고테크놀로지스코리아 주식회사 열 방출 효율이 높고 두께는 물론 크기를 감소시킨 고주파모듈 패키지 및 그 조립 방법
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101519183B (zh) * 2008-01-31 2011-09-21 台湾积体电路制造股份有限公司 具有集成电路管芯的微机电系统封装
CN101894861A (zh) * 2009-05-22 2010-11-24 联发科技股份有限公司 半导体装置
CN103295996A (zh) * 2012-06-29 2013-09-11 上海天马微电子有限公司 封装基板及其制作方法
CN103295996B (zh) * 2012-06-29 2016-06-15 上海天马微电子有限公司 封装基板及其制作方法

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KR20060080896A (ko) 2006-07-11
EP1681720A2 (en) 2006-07-19
CN101645444A (zh) 2010-02-10
EP1681720A3 (en) 2008-12-24
TW200701434A (en) 2007-01-01
JP2006191117A (ja) 2006-07-20
KR101070181B1 (ko) 2011-10-05
CN100585849C (zh) 2010-01-27
JP4589237B2 (ja) 2010-12-01

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