CN1805136A - 电路装置及携带设备 - Google Patents

电路装置及携带设备 Download PDF

Info

Publication number
CN1805136A
CN1805136A CNA2005101361934A CN200510136193A CN1805136A CN 1805136 A CN1805136 A CN 1805136A CN A2005101361934 A CNA2005101361934 A CN A2005101361934A CN 200510136193 A CN200510136193 A CN 200510136193A CN 1805136 A CN1805136 A CN 1805136A
Authority
CN
China
Prior art keywords
conductive pattern
peristome
circuit arrangement
semiconductor element
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005101361934A
Other languages
English (en)
Other versions
CN100403531C (zh
Inventor
高桥幸嗣
松木英夫
伊藤正美
青木直行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1805136A publication Critical patent/CN1805136A/zh
Application granted granted Critical
Publication of CN100403531C publication Critical patent/CN100403531C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开了一种在安装方向上没有制约的电路装置(10)。本发明的电路装置(10)包括：导电图案(11)，其具有管芯垫(11A)、第一接合焊盘(11B)以及第二接合焊盘(11C)；半导体元件(TR)，其固定在导电图案上。另外，还具有使导电图案(11)的背面露出并覆盖半导体元件(TR)和导电图案(11)的密封树脂(13)、将从密封树脂(13)露出的导电图案(11)的背面覆盖的覆盖树脂(16)。另外，使导电图案(11)的背面从设于覆盖树脂(16)上的开口部露出，将开口部相对电路装置的中心点旋转对称地配置。

Description

电路装置及携带设备
技术领域
本发明涉及电路装置及携带设备，特别是涉及具有规则配置的外部电极或开口部的电路装置及携带设备。
背景技术
目前，由于电子设备上设置的电路装置使用在手机、携带用的计算机等中，故要求其小型化、薄型化以及轻便化。最近，正在开发有被称为CSP(芯片尺寸封装)的与芯片大小相同的晶片等级CSP。
图10表示采用衬底65作为支承衬底的比芯片尺寸大一些的CSP66。这里，说明将晶体管芯片T安装在衬底65上的结构。
在该衬底65的表面形成有第一电极67、第二电极68以及管芯垫(ダイパツド)69，在背面形成有第一背面电极70A和第二背面电极70B。并且，经由贯通孔TH将第一电极67和第一背面电极70A连接。另外，经由贯通孔TH将第二电极和第二背面电极70B进行电连接。
在管芯垫69上固定有晶体管芯片T，通过金属细线72将晶体管的发射极和第一电极67连接。另外，通过金属细线72将晶体管的基极和第二电极68连接。另外，在衬底65上设有树脂层73以覆盖晶体管芯片T。
另外，在上述的CSP等电路装置中，为与外部进行电信号的发送接收，在装置的背面形成有焊锡等构成的外部电极76(例如下述的参照专利文献1)。并且，CSP66通过外部电极76固定在形成于安装衬底77表面上的导电路78上。
专利文献1：特开平11-274361号公报
但是，在上述的CSP66中，外部电极76的平面位置根据使用者的规格等而形成在规定的位置。即，外部电极76于平面上不配置在规则的位置上。由此，在将CSP66安装在安装衬底77上时，需要考虑安装方向的制约来配置CSP66。其结果，使CSP66的安装成本增加。特别是，在手机等携带设备中，用于安装的空间受到制约。由此，在电路元件的安装方向上受到制约，而对携带设备的小型化造成阻碍。
发明内容
本发明是鉴于上述问题点而研发的。本发明的主要目的是提供一种通过规则地配置外部电极的位置而降低安装方向的制约的电路装置。另外，本发明的其他目的是提供具有这样的电路装置的携带设备。
本发明的电路装置具有半导体元件、与所述半导体元件电连接而与外部进行电信号的发送接收的外部电极，将所述外部电极相对于中心点旋转对称地配置。
另外，在本发明的电路装置中，将所述外部电极以90度为单位旋转对称地配置。
另外，在本发明的电路装置中，所述外部电极具有与所述半导体元件的第一主电极连接的第一外部电极、与所述半导体元件的第二主电极连接的第二外部电极以及与所述半导体元件的控制电极连接的第三外部电极，将所述第一外部电极配置在中心部，将所述第二外部电极和所述第三外部电极以包围所述第一外部电极的方式旋转对称地配置。
另外，在本发明的电路装置中，所述半导体元件是MOSFET，所述第一主电极是源极，所述第二主电极是漏极，所述控制电极是栅极。
另外，在本发明的电路装置中，具有多层的配线结构。
另外，在本发明的电路装置中，内设有与所述半导体元件电连接的无源元件。
另外，在本发明的电路装置中，具有在表面形成第一导电图案、在背面形成第二导电图案的支承衬底，所述第一导电图案与所述半导体元件连接，所述第二导电图案与所述外部电极连接。
另外，本发明的电路装置具有导电图案、固定在所述导电图案上的半导体元件、使所述导电图案的背面露出并覆盖所述半导体元件和所述导电图案的密封树脂以及覆盖从所述密封树脂露出的所述导电图案的背面的覆盖树脂，使所述导电图案的背面从所述覆盖树脂上设置的开口部露出，将所述开口部相对于中心点旋转对称地配置。
另外，在本发明的电路装置中，将所述开口部以90度为单位旋转对称地配置。
另外，在本发明的电路装置中，所述开口部具有使与所述半导体元件的第一主电极连接的所述导电图案露出的第一开口部、使与所述半导体元件的第二主电极连接的所述导电图案露出的第二开口部以及使与所述半导体元件的控制电极连接的所述导电图案露出的第三开口部，将所述第一开口部配置在中心部，将所述第二开口部和所述第三开口部以覆盖所述第一开口部的方式配置。
另外，在本发明的电路装置中，所述半导体元件是MOSFET，所述第一主电极是源极，所述第二主电极是漏极，所述控制电极是栅极。
另外，在本发明的电路装置中，所述第一开口部和所述第二开口部形成圆形，所述第三开口部形成矩形。
另外，在本发明的电路装置中，所述第二开口部的宽度形成得比与所述半导体元件的第二主电极连接的所述导电图案窄，所述第三开口部的宽度比与所述半导体元件的控制电极连接的所述导电图案宽。
另外，本发明的携带设备具有上述的电路装置。
根据本发明的电路装置，外部电极或开口部相对于中心点旋转对称地配置。因此，即使以90度为单位旋转任意角度而安装电路装置，也能够实现可构成规定的电气回路及系统的安装结构。由此，能够降低安装电路装置时在安装方向上的制约。
另外，根据本发明的携带设备，由于具有上述电路装置而能够实现小型化。
附图说明
图1表示本发明的电路装置，(A)是平面图，(B)是剖面图，(C)是电路图；
图2表示本发明的电路装置，(A)是平面图，(B)是剖面图，(C)是剖面图；
图3表示本发明的电路装置，(A)是平面图，(B)是剖面图，(C)是剖面图；
图4表示本发明的电路装置的制造方法，(A)是剖面图，(B)是平面图；
图5表示本发明的电路装置的制造方法，(A)是剖面图，(B)是平面图；
图6表示本发明的电路装置的制造方法，(A)是剖面图，(B)是平面图；
图7表示本发明的电路装置的制造方法，(A)是剖面图，(B)是剖面图，(C)是剖面图；
图8表示本发明的电路装置的制造方法，(A)是剖面图，(B)是平面图；
图9表示本发明的电路装置的制造方法，(A)是剖面图，(B)是平面图；
图10是表示现有的电路装置的剖面图。
符号说明
10电路装置
11导电图案
11A管芯垫
11B第一接合焊盘
11C第二接合焊盘
13密封树脂
14金属细线
15外部电极
16覆盖树脂
17分离槽
18A第一开口部
18B第二开口部
18C第三开口部
21A第一导电图案
21B第二导电图案
具体实施方式
〔第一实施方式〕
参照图1说明本实施方式的电路装置10。图1(A)是电路装置10的平面图，图1(B)是图1(A)的B-B′剖面的剖面图，图1(C)是表示设于电路10内的电气回路的电路图。
参照图1(A)和图1(B)，本实施方式的电路装置10具有构成管芯垫以及接合焊盘的导电图案11、与该导电图案11电连接的半导体元件TR以及使导电图案11的背面露出并将半导体元件TR和导电图案11覆盖的密封树脂13。另外，在本实施方式中，导电图案11、开口部18以及外部电极15相对于电路装置10的中心点旋转对称地配置。这里，作为半导体元件TR以MOSFET(Metal-Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)为例进行说明。另外，在本实施方式中，将管芯垫11A、第一接合焊盘11B以及第二接合焊盘11C统称为导电图案11。
导电图案11由固定半导体元件TR的管芯垫11A、通过金属细线14与半导体元件TR连接的第一接合焊盘11B以及第二接合焊盘11C构成。另外，导电图案11考虑与钎焊材料的粘附性、接合性及镀敷性而选择其材料。具体地，作为导电图案11的材料，选择由以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。这里，导电图案11形成将背面露出并埋入到密封树脂13中的结构，通过分离槽11电分离。导电图案11利用蚀刻形成，其侧面形成弯曲面。另外，导电图案11相互间隔的距离例如为100μm左右。
管芯垫11A在电路装置10的角部配置为四个，在其上部固定半导体元件TR。管芯焊盘11A具有正方形的平面形状，比上部载置的半导体元件TR大一些地形成。另外，各个管芯垫11A形成同等的尺寸。
第一接合焊盘11B配置在电路装置10的中心部，通过金属细线14与半导体元件TR的源极连接。第一接合焊盘11B具有正方形等对称的平面形状。
形成有四个第二接合焊盘11C，其位于配置在四个角部的管芯垫11A之间，并通过金属细线14与半导体元件TR的源极电连接。另外，第二接合焊盘11C具有相对于电路装置10的中心方向沿长度方向延伸的长方形的平面形状。另外，短边方向的第二接合焊盘11C的宽度形成得比管芯垫11A窄。由此，能够减小电路装置10整体的平面尺寸。另外，第二接合焊盘11C配置于电路装置10各侧边的中央部，形成相互同等的尺寸。
这里，半导体元件TR采用MOSFET，背面的漏极固定在管芯垫11A上。也可以使用焊锡和导电性膏将半导体元件TR固定在管芯垫11A上。作为半导体元件TR可采用MOSFET以外的晶体管。例如，可以采用IGBT(Insulated Gate Bipolar Transistor：绝缘栅二极晶体管)及双极晶体管作为半导体元件TR。
密封树脂13使导电图案11的背面露出并覆盖半导体元件TR、金属细线14以及导电图案11。作为密封树脂13，可采用热固化树脂或热可塑性树脂。本发明的电路装置10整体由密封树脂13支承。另外，在将各导电图案11分离的分离槽17中填充有密封树脂13。
分离槽17设置在各导电图案11之间，具有将各导电图案11电分离的作用。并且，分离槽17的宽度基本上在任何位置都均等，例如，大于或等于100μm左右。换言之，各导电图案11等间隔地分隔开。
外部电极15附着在从密封树脂13露出的导电图案11的背面。作为外部电极15的材料，可采用共晶铅焊锡、无铅焊锡、银膏、铜膏等。
这里，可以形成基于外部电极15的BGA(Ball GridArray：球栅阵列)，也可以为省去了外部电极15的结构。在省去了外部电极15的情况下，形成具有在背面露出的导电图案11的LGA(Land GridArray：焊盘阵列)。
覆盖树脂16覆盖使导电图案11露出的电路装置10的背面。形成有外部电极15的区域的覆盖树脂16被部分地去除而形成开口部18。
本实施方式的电路装置10中，位于周边部的管芯垫11A和第二接合焊盘11C相对于中心点以90度为单位旋转对称地配置。在各导电图案11的背面形成的外部电极15也相对于中心点以90度为单位旋转对称地配置。另外，电路装置10的平面的外形形状为正方形。因此，即使电路装置10在平面上旋转90度、180度、270度、360度，导电图案11和外部电极15也位于相同位置。由此，在安装电路装置10时，能够大幅地降低安装方向的制约。
参照图1(C)说明电路装置10的内部组装的电路。在电路装置10中内设四个半导体元件TR。各半导体元件TR的栅极(控制电极)通过金属细线14与第二接合焊盘11C一个个地连接。而各半导体元件TR的源极(第一主电极)与第一接合焊盘11B共同连接。各半导体元件TR的漏极(第二主电极)与固定的管芯垫11A一个个地连接。因此，各半导体元件TR根据从第二接合焊盘11C个别地输入的控制信号来控制在第一接合焊盘11B和管芯垫11A之间流过的电流。在本实施方式中，形成于管芯垫11A和第二接合焊盘11C背面的外部电极15相对于电路装置10的中心点旋转对称地配置。
参照图2说明电路装置10的背面的结构。图2(A)是从背面看到的电路装置10的平面图。图2(B)是图2(A)的B-B′线的剖面图。图2(C)是图2(A)的C-C′线的剖面图。这里，省略了附着于导电图案11背面的外部电极15而进行图示。
参照图2(A)，配置于四角的管芯垫11A的背面从设于覆盖树脂16上的圆形的第二开口部18B部分地露出。第二开口部18B的大小形成得小于管芯垫11A。因此，在第二开口部18B上形成焊锡等构成的外部电极时，利用覆盖树脂16来限制外部电极的位置和平面的尺寸。该结构一般被称为“焊接掩模限定”(solder mask defined)(以下称为SMD结构)。另外，管芯垫11A的背面除了形成有第二开口部18B的位置，还被覆盖树脂16覆盖。因此，通过利用覆盖树脂16覆盖衬底片11A的背面，管芯垫11A的剥离等得到抑制。
第一接合焊盘11B的背面从设在覆盖树脂16上的圆形的第一开口部18A露出。另外，第一开口部18A位于电路装置10的中心部，其大小与第二开口部18B相等。第一开口部18A由于形成得小于第一接合焊盘18B，故附着在第一接合焊盘11B背面的外部电极的结构称为SMD结构。
第二接合焊盘11C的背面从设在覆盖树脂16上的矩形的第三开口部18C露出。另外，第三开口部18C位于各个相邻边的中央部。为了减小电路装置10的平面尺寸，第二接合焊盘11C与管芯垫11A等相比细长地形成。因此，难以将与圆形的第二开口部18B相同大小的开口部形成在第二接合焊盘11C的背面。因此在本实施方式中，通过将第三开口部18C形成矩形而增大第二接合焊盘11C的背面露出的面积。
在本实施方式中，第一开口部18A配置在电路装置10的中央部。第二开口部18B和第三开口部18C相对于电路装置10的中心点以90度为单位旋转对称地配置。因此，即使电路装置10以90度为单位平面地旋转的情况，第二开口部18B也总是位于角部。另外，第三开口部18C总是位于各侧边的中央部。因此，在安装电路装置10时，安装方向的限制被大幅度地降低。
参照图2(B)和图2(C)具体说明第二接合焊盘11C和第三开口部18C的相关结构。
参照图2(B)，在剖面B-B′中，第二接合焊盘11C的背面整个从第三开口部18C露出。即，第三开口部的宽度D2形成得大于第二接合焊盘11C的宽度D1。例如，D2为0.25mm左右，D1为0.23mm左右。即，D2比D1大0.02mm左右。因此，在第二接合焊盘11C的背面附着有由焊锡构成的外部电极时，利用第二接合焊盘11C背面的润湿性来限制外部电极的形状。该结构一般被称为“无焊接掩模限定”(non solder mask defined)(以下称为NSMD结构)。根据该结构，在剖面B-B′中，能够将外部电极粘附在第二接合焊盘11C背面的整个区域上。因此，能够在第二接合焊盘11C的背面形成尽可能大的外部电极。
参照图2(C)，在剖面C-C′中，第二接合焊盘11C的两端部被覆盖树脂16覆盖。即，在该剖面方向上第二接合焊盘11C的宽度D4形成得长于第三开口部18C的宽度D3。例如D4为0.50mm左右，D3为0.30mm左右。第二接合焊盘11C的两端部由于被覆盖树脂16覆盖而压入，能够抑制第二接合焊盘11C的剥离。
另外，在剖面C-C′中，若在第二接合焊盘11C的背面粘附由焊锡构成的外部电极，则通过设置于覆盖树脂16上的第三开口部18C来限制外部电极的平面尺寸。即，在剖面C-C′中，利用SMD结构来限制外部电极的形状。
具有上述结构的电路装置10内设于手机、PDA(Personal DigitalAssistant：个人数字助理)或笔记本电脑等携带设备中。本实施方式的电路装置10由于在安装方向上的制约少，故能够缩小安装所占据的面积。其结果，有助于携带设备的小型化。
参照图3说明其他方式的电路装置10A。
图3(A)所示的电路装置10A的基本结构与上述的电路装置10相同，不同点在于本实施方式的电路装置10A具有配线12A、12B、12C。配线12A、12B、12C由导电图案11的一部分构成，作为将内设于电路装置10A中的电路元件相互电连接的路径起作用。具体地，配线12A从衬底片11A一体地延伸，以将纸面上位于上部的衬底片11A相互连接。另外，配线12B将管芯焊盘11A和第二接合焊盘11C连接而延伸。配线12C将第二接合焊盘11C相互连接而延伸。
图3(B)所示的电路装置10B形成具有支承衬底31的结构。在支承衬底31的表面形成第一导电图案21A，在背面形成第二导电图案21B。另外，第一导电图案21A和第二导电图案21B贯通支承衬底31而在所希望的位置连接。这里，多个电路元件被组装到装置内部。具体地，半导体元件TR和无源元件CH内设于电路装置中。可采用片状电容器和片状电阻等作为无源元件CH。另外，也可以在装置内部构成由多个电路元件形成的复杂系统。作为支承衬底31的材料，可普遍采用铝等金属、硅等半导体以及树脂等。
图3(C)所示的电路装置10C介由数十μm左右厚的薄绝缘层32层积第一导电图案21A和第二导电图案21B。即，形成双层的多层配线结构。这里，也可以形成大于或等于三层的多层配线。其他结构与电路装置10B同样。
〔第二实施方式〕
接下来参照图4～图9说明上述的电路装置10的制作方法。
如图4～图5所示，本发明的第一工序是通过在导电箔40上形成分离槽17而形成凸状突出的导电图案11。
在本工序中，如图4(A)所示，准备片状的导电箔40。该导电箔40采用以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。考虑到以后的蚀刻工序，导电箔的厚度最好为100μm～300μm左右。具体地，如图4(B)所示，在长方形导电箔40上形成有多个单元的块42相互分隔而排列有4～5个。各块42之间设有狭缝43，吸收模制工序等的加热处理所产生的导电箔40的应力。另外，在导电箔40的上下周端以一定间隔设有索引孔，其用于各工序的定位。
首先，如图4(A)所示，在导电箔40上形成作为耐蚀掩模的抗蚀剂PR。对抗蚀剂PR进行构图，使导电箔40中对应于预形成分离槽的区域的表面露出。以该抗蚀剂PR为蚀刻掩模进行湿式蚀刻，由此从抗蚀剂PR露出的导电箔40被蚀刻而形成分离槽。
参照图5说明在该工序中形成的具体导电图案11的形状。图5(A)是形成有分离槽17的导电箔40的剖面图，图5(B)是其平面图。
参照图5(A)，通过在导电箔40的表面上形成分离槽17而形成凸状突出的导电图案11。
图5(B)表示具体的导电图案11。该图与图4(B)所示的块42的一个放大后的结构对应。虚线包围的部分的一个为一个单元45。在一个块42上矩阵状地排列多个单元45，每个单元45上设有相同的导电图案11。这里，管芯垫11A、第一接合焊盘11B以及第二接合焊盘11C构成导电图案11。在此，可以形成2行2列四个单元45，也可以形成多个单元45。在本工序结束之后将抗蚀剂PR剥离。
本发明第二工序如图6(A)的剖面图及图6(B)的平面图所示，是将半导体元件TR固定在导电图案11上。
在此，在各单元45的各个管芯垫11A上固定半导体元件TR。通过金硅共晶接合将半导体元件TR的背面(漏极)接合在管芯垫11A的上面。另外，也可以使用焊锡和导电性膏固定半导体元件TR。
在上述工序结束之后，通过金属细线14进行半导体元件TR的电连接。具体地，通过金属细线14将位于单元45中心的第一接合焊盘11B和半导体元件TR的漏极连接。通过金属细线14将位于管芯垫11A之间的第二接合焊盘11C和半导体元件TR的栅极连接。
如图7所示，本发明的第三工序是形成密封树脂13，并在将各导电图案11分离之后形成覆盖树脂16。
首先，参照图7(A)，形成密封树脂13。密封树脂13覆盖半导体元件TR和金属细线14并填充到分离槽17中而形成。这里，密封树脂13与导电图案11侧面的弯曲结构嵌合而牢固地结合。
然后，参照图7(B)，从背面对导电箔40进行全面地蚀刻，直至填充到分离槽17中的密封树脂13露出。利用该工序使各导电图案11电分离。
参照图7(C)，形成覆盖树脂16以将从密封树脂13露出的导电图案11覆盖。为将露出的导电图案11覆盖，通过涂敷液状的树脂并使其固化而形成覆盖树脂16。
本发明的第四工序是通过如图8所示部分地去除覆盖树脂16而形成开口部。图8(A)是表示使开口部18曝光的工序的剖面图，图8(B)是表示形成有开口部18之后的块42的平面图。另外，图8(A)的剖面图对应于图8(B)的A-A′剖面。
参照图8(A)，首先，使覆盖树脂16曝光以形成开口部。这里，作为覆盖树脂16，使用将已曝光的部分去除的正型抗蚀剂。因此，利用碱性溶剂将覆盖树脂16被光线52曝光了的部分去除。另外，也可以采用负型的抗蚀剂作为覆盖树脂16。此时，图8(A)的曝光图案51和曝光部53A等的位置逆转。
曝光掩模50位于覆盖树脂16的上方，为将形成有开口部的区域之外的覆盖树脂16遮光而在其表面形成有曝光图案51。另外，在与开口部对应的曝光图案50上形成有未被曝光图案51覆盖的曝光部53A等。在该状态下，从曝光掩模51的上方照射平行光线52，则对覆盖树脂16中位于曝光部53下方的部分选择地进行曝光。在进行曝光之后若将覆盖树脂16浸渍到碱溶液中，则覆盖树脂16的感光的部分溶融而被剥离，形成开口部。
曝光部53A和曝光部53C对应于形成在衬底片11A背面的圆形的第二开口部18B。并且，曝光部53A和曝光部53C的直径D3形成得比管芯垫11A的宽度D4短。具体地，曝光部53A、53C的直径D3为0.3mm左右，管芯垫11A的宽度D4为0.5mm左右。因此，通过该工序，管芯垫11A的背面部分地从覆盖树脂16露出。
曝光部53B对应于在第二接合焊盘11C背面形成的矩形的第三开口部18C。另外，曝光部53B的宽度形成得大于第二接合焊盘11C的宽度。具体地，曝光部53B的宽度D2为0.25mm左右，第二接合焊盘11C的宽度D1为0.23mm左右。因此，第二接合焊盘11C的背面在该剖面中整个从覆盖树脂16露出。
如上所述，通过使曝光部53B的宽度大于第二接合焊盘11C，能够使第二接合焊盘11C的整个背面从覆盖树脂16露出。例如，曝光掩模50以数十μm左右的误差平面地配置时，曝光部53B也相对第二接合焊盘11C偏离相对位置而配置。此时，由于曝光部53B的宽度D2相对于第二接合焊盘11C的宽度D1形成得足够大，故能够使第二接合焊盘11C整个背面区域从覆盖树脂16露出。
通过使第二接合焊盘11C的整个背面区域从覆盖树脂16露出，在以后的工序中，可相对第二接合焊盘11C的整个背面区域粘附由焊锡构成的外部电极。
本发明的第五工序如图9所示，通过切割将密封树脂13以各个单元45进行分离。图9(A)是本工序的剖面图，图9(B)是本工序的平面图。
参照图9(A)和图9(B)，在从第一开口部18A等露出的导电图案11的背面粘附外部电极15。作为外部电极15的材料采用焊锡等和导电性膏。另外，在不形成焊锡等的情况下，从覆盖树脂16露出外部的导电图案11而成为外部电极。
在本工序中，利用刮片49沿各单元45之间的分割线分割密封树脂13，分离成一个个电路装置。由于在分割线上仅存在填充到分离槽17中的密封树脂13，故刮片49的损耗少，另外，还能够不产生金属毛刺而分割成极准确的外形。

Claims (15)

1.一种电路装置，其特征在于，具有半导体元件、与所述半导体元件电连接而与外部进行电信号的发送接收的外部电极，将所述外部电极相对于中心点旋转对称地配置。
2.如权利要求1所述的电路装置，其特征在于，将所述外部电极以90度为单位旋转对称地配置。
3.如权利要求1所述的电路装置，其特征在于，所述外部电极具有与所述半导体元件的第一主电极连接的第一外部电极、与所述半导体元件的第二主电极连接的第二外部电极以及与所述半导体元件的控制电极连接的第三外部电极，将所述第一外部电极配置在中心部，将所述第二外部电极和所述第三外部电极以包围所述第一外部电极的方式旋转对称地配置。
4.如权利要求3所述的电路装置，其特征在于，所述半导体元件是MOSFET，所述第一主电极是源极，所述第二主电极是漏极，所述控制电极是栅极。
5.如权利要求1所述的电路装置，其特征在于，具有多层的配线结构。
6.如权利要求1所述的电路装置，其特征在于，内设有与所述半导体元件电连接的无源元件。
7.如权利要求1所述的电路装置，其特征在于，具有在表面形成第一导电图案、在背面形成第二导电图案的支承衬底，所述第一导电图案与所述半导体元件连接，所述第二导电图案与所述外部电极连接。
8.一种电路装置，其特征在于，具有导电图案、固定在所述导电图案上的半导体元件、使所述导电图案的背面露出并覆盖所述半导体元件和所述导电图案的密封树脂以及覆盖从所述密封树脂露出的所述导电图案的背面的覆盖树脂，使所述导电图案的背面从所述覆盖树脂上设置的开口部露出，将所述开口部相对于中心点旋转对称地配置。
9.如权利要求8所述的电路装置，其特征在于，将所述开口部以90度为单位旋转对称地配置。
10.如权利要求8所述的电路装置，其特征在于，所述开口部具有使与所述半导体元件的第一主电极连接的所述导电图案露出的第一开口部、使与所述半导体元件的第二主电极连接的所述导电图案露出的第二开口部以及使与所述半导体元件的控制电极连接的所述导电图案露出的第三开口部，将所述第一开口部配置在中心部，将所述第二开口部和所述第三开口部以覆盖所述第一开口部的方式配置。
11.如权利要求10所述的电路装置，其特征在于，所述半导体元件是MOSFET，所述第一主电极是源极，所述第二主电极是漏极，所述控制电极是栅极。
12.如权利要求10所述的电路装置，其特征在于，所述第一开口部和所述第二开口部形成圆形，所述第三开口部形成矩形。
13.如权利要求10所述的电路装置，其特征在于，所述第二开口部的宽度形成得比与所述半导体元件的第二主电极连接的所述导电图案窄，所述第三开口部的宽度比与所述半导体元件的控制电极连接的所述导电图案宽。
14.如权利要求8所述的电路装置，其特征在于，内设有与所述半导体元件电连接的无源元件。
15.一种携带设备，其特征在于，具有权利要求1～14任一项所述的电路装置。
CNB2005101361934A 2004-12-27 2005-12-20 电路装置及携带设备 Expired - Fee Related CN100403531C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP376147/04 2004-12-27
JP2004376147A JP4592413B2 (ja) 2004-12-27 2004-12-27 回路装置

Publications (2)

Publication Number Publication Date
CN1805136A true CN1805136A (zh) 2006-07-19
CN100403531C CN100403531C (zh) 2008-07-16

Family

ID=36639472

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005101361934A Expired - Fee Related CN100403531C (zh) 2004-12-27 2005-12-20 电路装置及携带设备

Country Status (3)

Country Link
US (1) US7417309B2 (zh)
JP (1) JP4592413B2 (zh)
CN (1) CN100403531C (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292292A (zh) * 2015-11-30 2018-07-17 Pezy计算股份有限公司 管芯和封装件、以及管芯的制造方法和封装件的生成方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5232460B2 (ja) * 2007-12-12 2013-07-10 新光電気工業株式会社 半導体パッケージ
US8125086B2 (en) 2008-05-28 2012-02-28 Hynix Semiconductor Inc. Substrate for semiconductor package
US8148823B1 (en) * 2009-12-14 2012-04-03 Picor Corporation Low loss package for electronic device
JP5685012B2 (ja) * 2010-06-29 2015-03-18 新光電気工業株式会社 半導体パッケージの製造方法
CN107078067A (zh) 2015-03-30 2017-08-18 瑞萨电子株式会社 半导体装置及其制造方法
TWI661476B (zh) * 2018-02-14 2019-06-01 頎邦科技股份有限公司 半導體基板及其加工方法
US11935878B2 (en) * 2021-09-10 2024-03-19 Vanguard International Semiconductor Corporation Package structure and method for manufacturing the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6073257U (ja) * 1983-10-24 1985-05-23 ローム株式会社 半導体装置
KR910001419B1 (ko) * 1987-03-31 1991-03-05 가부시키가이샤 도시바 수지봉합형 집적회로장치
JP2686568B2 (ja) * 1991-04-05 1997-12-08 シャープ株式会社 光学装置
TW368745B (en) * 1994-08-15 1999-09-01 Citizen Watch Co Ltd Semiconductor device with IC chip highly secured
US5844168A (en) * 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
KR100433685B1 (ko) * 1996-04-18 2004-10-06 인터내쇼널 렉티파이어 코포레이션 10마력모터제어기용전력트레인분할장치
JP3053010B2 (ja) * 1997-11-21 2000-06-19 日本電気株式会社 半導体装置
JP3831109B2 (ja) 1998-03-25 2006-10-11 シチズン時計株式会社 半導体パッケージ
JP3679687B2 (ja) * 2000-06-08 2005-08-03 三洋電機株式会社 混成集積回路装置
JP3863816B2 (ja) * 2002-06-28 2006-12-27 三洋電機株式会社 回路装置
US6841852B2 (en) * 2002-07-02 2005-01-11 Leeshawn Luo Integrated circuit package for semiconductor devices with improved electric resistance and inductance
JP4166065B2 (ja) * 2002-09-27 2008-10-15 三洋電機株式会社 回路装置の製造方法
JP2005129900A (ja) * 2003-09-30 2005-05-19 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP4446772B2 (ja) * 2004-03-24 2010-04-07 三洋電機株式会社 回路装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292292A (zh) * 2015-11-30 2018-07-17 Pezy计算股份有限公司 管芯和封装件、以及管芯的制造方法和封装件的生成方法

Also Published As

Publication number Publication date
US20060145322A1 (en) 2006-07-06
CN100403531C (zh) 2008-07-16
JP2006186018A (ja) 2006-07-13
JP4592413B2 (ja) 2010-12-01
US7417309B2 (en) 2008-08-26

Similar Documents

Publication Publication Date Title
CN1700431A (zh) 电路装置及其制造方法、板状体
CN1805136A (zh) 电路装置及携带设备
CN1258954C (zh) 电路器件的制造方法
CN1143375C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1183593C (zh) 半导体装置
CN1497717A (zh) 电路装置及其制造方法
CN1187806C (zh) 电路装置的制造方法
CN1244258C (zh) 电路装置及其制造方法
CN1805657A (zh) 配线电路基板
CN101080958A (zh) 部件内置模块及其制造方法
CN1674277A (zh) 电路装置
CN1241259C (zh) 电路装置的制造方法
CN1201253A (zh) 半导体集成电路器件
CN1359147A (zh) 凸块形成方法、半导体装置及其制造方法和半导体芯片
CN1835661A (zh) 配线基板的制造方法
CN1674758A (zh) 电路装置及其制造方法
CN1311528A (zh) 半导体器件及其制造方法、电路板和电子装置
CN1897274A (zh) 半导体装置
CN1604293A (zh) 半导体装置的制造方法及半导体装置
CN1758431A (zh) 晶背上具有整合散热座的晶圆级封装以及晶片的散热方法
CN1333562A (zh) 半导体模块及其制造方法
CN1301543C (zh) 半导体晶片、半导体装置及其制造方法、电路基板及电子机器
CN1392601A (zh) 电路装置及其制造方法
CN1258208C (zh) 半导体装置及其制造方法、半导体晶片、电路基板及电子机器
CN1678175A (zh) 电路部件模块及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080716

Termination date: 20131220