CN1691292B - 用于制造半导体器件的方法和电子器件 - Google Patents

用于制造半导体器件的方法和电子器件 Download PDF

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Publication number
CN1691292B
CN1691292B CN2005100684632A CN200510068463A CN1691292B CN 1691292 B CN1691292 B CN 1691292B CN 2005100684632 A CN2005100684632 A CN 2005100684632A CN 200510068463 A CN200510068463 A CN 200510068463A CN 1691292 B CN1691292 B CN 1691292B
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China
Prior art keywords
conductive layer
mask
etching
product
layer
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Expired - Fee Related
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CN2005100684632A
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English (en)
Chinese (zh)
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CN1691292A (zh
Inventor
冈本悟
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of CN1691292A publication Critical patent/CN1691292A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
CN2005100684632A 2004-04-28 2005-04-28 用于制造半导体器件的方法和电子器件 Expired - Fee Related CN1691292B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP132677/04 2004-04-28
JP2004132677A JP4519512B2 (ja) 2004-04-28 2004-04-28 半導体装置の作製方法、除去方法

Publications (2)

Publication Number Publication Date
CN1691292A CN1691292A (zh) 2005-11-02
CN1691292B true CN1691292B (zh) 2011-01-12

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CN2005100684632A Expired - Fee Related CN1691292B (zh) 2004-04-28 2005-04-28 用于制造半导体器件的方法和电子器件

Country Status (3)

Country Link
US (1) US7432211B2 (cg-RX-API-DMAC10.html)
JP (1) JP4519512B2 (cg-RX-API-DMAC10.html)
CN (1) CN1691292B (cg-RX-API-DMAC10.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5352081B2 (ja) 2006-12-20 2013-11-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009033727A (ja) * 2007-06-22 2009-02-12 Semiconductor Energy Lab Co Ltd 半導体装置
CN104485336B (zh) 2009-10-21 2018-01-02 株式会社半导体能源研究所 半导体器件
CN119096336B (zh) * 2023-03-29 2025-10-28 京东方科技集团股份有限公司 金属网格的制备方法和天线的制备方法

Citations (2)

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CN1124406A (zh) * 1994-07-28 1996-06-12 现代电子产业株式会社 形成半导体器件图形的方法
US6461923B1 (en) * 1999-08-18 2002-10-08 Advanced Micro Devices, Inc. Sidewall spacer etch process for improved silicide formation

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US5298112A (en) * 1987-08-28 1994-03-29 Kabushiki Kaisha Toshiba Method for removing composite attached to material by dry etching
JPH065563A (ja) 1992-06-19 1994-01-14 Oki Electric Ind Co Ltd レジストのアッシング方法
US5427622A (en) * 1993-02-12 1995-06-27 International Business Machines Corporation Method for uniform cleaning of wafers using megasonic energy
US5387556A (en) * 1993-02-24 1995-02-07 Applied Materials, Inc. Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub.2
JPH07326609A (ja) * 1994-04-07 1995-12-12 Matsushita Electron Corp 半導体装置の製造方法
JPH08181148A (ja) * 1994-12-27 1996-07-12 Kawasaki Steel Corp 半導体装置の製造方法
IL115931A0 (en) * 1995-11-09 1996-01-31 Oramir Semiconductor Ltd Laser stripping improvement by modified gas composition
US6004839A (en) * 1996-01-17 1999-12-21 Nec Corporation Semiconductor device with conductive plugs
JPH09213704A (ja) * 1996-02-05 1997-08-15 Mitsubishi Gas Chem Co Inc 半導体装置の製造方法
JPH09213703A (ja) 1996-02-05 1997-08-15 Matsushita Electron Corp 半導体装置の製造方法
JP3574270B2 (ja) 1996-04-17 2004-10-06 三菱電機株式会社 Ａｌテーパドライエッチング方法
TW376547B (en) * 1997-03-27 1999-12-11 Matsushita Electric Industrial Co Ltd Method and apparatus for plasma processing
JPH10303197A (ja) * 1997-04-24 1998-11-13 Matsushita Electron Corp 半導体装置の製造方法
US6033993A (en) * 1997-09-23 2000-03-07 Olin Microelectronic Chemicals, Inc. Process for removing residues from a semiconductor substrate
KR100252889B1 (ko) * 1997-11-14 2000-04-15 김영환 백금식각방법
KR100269323B1 (ko) * 1998-01-16 2000-10-16 윤종용 반도체장치의백금막식각방법
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JP2003152108A (ja) * 2002-08-22 2003-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
JP4683817B2 (ja) * 2002-09-27 2011-05-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
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CN1124406A (zh) * 1994-07-28 1996-06-12 现代电子产业株式会社 形成半导体器件图形的方法
US6461923B1 (en) * 1999-08-18 2002-10-08 Advanced Micro Devices, Inc. Sidewall spacer etch process for improved silicide formation

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Also Published As

Publication number Publication date
JP4519512B2 (ja) 2010-08-04
US20050241952A1 (en) 2005-11-03
US7432211B2 (en) 2008-10-07
CN1691292A (zh) 2005-11-02
JP2005317699A (ja) 2005-11-10

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Termination date: 20180428