CN1682361A - 制造自调准非易失存储单元的方法 - Google Patents
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Abstract
本发明揭示一种制造自调准非易失存储单元(200)的方法，该存储单元包括一小侧壁分隔件(239)，该小侧壁分隔件设置在主浮动栅极区(212)旁边并与该主浮动栅极区电耦合。小侧壁分隔件和主浮动栅极区在衬底(204)上形成，两者形成所述非易失存储单元的浮动栅极。通过氧化物层(208，232，242)使两者与衬底电绝缘，在小侧壁分隔件和衬底之间的氧化物层的厚度较薄(260；232，242)；而在主浮动栅极区和衬底之间的氧化物层的厚度较厚(263；208)。小侧壁分隔件可做得较小；因此，薄氧化物层可同样做得较小，以便造成一小的通路让电子以隧道贯穿形式进入浮动栅极。
Description
技术领域
本发明涉及自调准非易失存储单元，更具体地说，涉及一种具有一高电容耦合比率以及具有一薄和小隧道氧化物区的自调准非易失存储单元的制造方法。
背景技术
图1所示为在美国专利4,833,096之中的图18所描述的一EEPROM100(电可擦可编程只读存储器)的剖面图，该专利颁授予本发明的同一受让人。
参照本申请的图1，一深的N型阱23在P型衬底40里面形成，而确定了N型沟道和存储单元器件。N型沟道截断物(stop)和场氧化物在该器件区周围形成。沟道截断物和场氧化物通过由热生长一薄氧化物层形成，淀积一厚度为1000-2500的氮化物层并从非器件区移除该氮化物，且在N型阱和N型沟道器件区周围植入硼离子，然后在硼中驱动并在没有覆盖氮化物的非器件区热生长氧化物。
延续的制造程序是在存储单元区的一部分植入第一种N型杂质，热生长第一氧化物层59，并在杂质植入物之上的该层中界定一窗口，在该窗口孔中植入第二种N型杂质，并在窗口中再长成一厚氧化物层。接着淀积一厚度为2500-3400的多晶的硅(“多晶硅”)层，并移除第一氧化物层以便形成浮动栅极71。在温度1000-1050℃之间热生长第二氧化物层，以确保第二氧化物层在多晶硅浮动栅极和衬底之上有一相当均匀的厚度。调整任何增强型器件的阈值以后，淀积由多晶硅或一多晶硅/硅化物夹心层组成的第二栅极层，并选择性地移除第二氧化物层以界定外围器件的栅极95和97以及第二多晶硅栅极99，该第二多晶硅栅极连同浮动栅极71一起形成一存储单元30。然后使用该特定器件的多晶硅栅极作为一自调准的掩模以便形成源极和漏极。
当用以下的方式确定一双层导电线路之后，所述制造程序便结束。
首先，施加一掺以硼/磷的硅玻璃121覆盖物，蚀刻接触孔123，并且加热玻璃使其达到流动温度以使接触孔形成圆角。然后确定导电线路131的第一层。接着淀积一绝缘的金属间化合物(intermetal)层133，蚀刻和再淀积该层以形成实质上平坦的表面。过孔135是湿/干蚀刻的，然后确定第二层导电线路137。一钝化层139可淀积在第二金属层137之上，或如为单金属层器件，可淀积在第一金属层131之上。
如果EEPROM 100有更高的耦合比率，则它的编程或擦除能更快速地完成。存储单元30(和EEPROM 100)的耦合比率是指在单元30的控制栅极99和浮动栅极71之间形成的第一电容(未显示)与第一电容及在存储单元30的浮动栅极71和P型衬底40之间形成的第二电容(未显示)的总和的比率。第一电容和第二电容串联；因此，当存储单元30的耦合比率增加而其它因素相同时，浮动栅极71和P型衬底40之间的电压降亦会增加。结果是电子能容易地以隧道贯穿形式通过薄的隧道氧化物层59进入浮动栅极71。换句话说，存储单元的编程能更快速地执行。
有至少二个增加存储单元耦合比率的方法。第一个方法是增加在存储单元30的控制栅极99和浮动栅极71之间形成的第一电容。其中一个做法是增加在存储单元30的控制栅极99和浮动栅极71之间的重迭区。
第二个方法是减小在存储单元30的浮动栅极71和P型衬底40之间形成的第二电容。做法是减小在存储单元30的浮动栅极71和P型衬底40之间的重迭区。值得注意的是，虽然在存储单元30的浮动栅极71和P型衬底40之间增加一个专用隧道氧化物区59的厚度能减少第二电容和因而增加耦合比率，但电子更难以隧道贯穿形式通过隧道氧化物层59进入浮动栅极71。所以，一个折衷办法是，专用隧道氧化物层59的隧道氧化物区130应该只一小部分是较薄的，作为电子通路，使电子以隧道贯穿形式从P型衬底40进入浮动栅极71而在隧道氧化物区59的剩余部份应该是较厚的。
但是，在运用以上提到的第二种方法时，仍有改善的余地。本发明的目的是改善现有技术中减小在浮动栅极和P型阱或P型衬底之间所形成的第二电容的方法，做法是提供一方法制造一存储单元，其在隧道氧化物区里的一小部份是薄的，为电子创造一通路使其以隧道贯穿形式进入浮动栅极，而在隧道氧化物区的其它部份仍然是较厚的。
发明内容
本发明的非易失存储单元有一个小侧壁分隔件，所述分隔件设置在一个主浮动栅极区旁边并与主浮动栅极区作电耦合。该小侧壁分隔件和主浮动栅极区都在衬底上形成，并且两者构成了非易失存储单元的浮动栅极。
设有一氧化物层使所述两者与衬底电绝缘，在小侧壁分隔件与衬底之间的所述氧化物绝缘层是较薄的；而在主浮动栅极区与衬底之间的所述氧化物绝缘层则是较厚的。该小侧壁间分隔件可以做得较狭窄；因此，氧化物层的较薄部份也可同样地做得较小，以造成一个小的通路，使电子能以隧道贯穿形式进入浮动栅极。
附图说明
图1是现有技术中一典型EEPROM(电可擦可编程只读存储器)的剖面图。
图2A-2J是剖面图，其所示说明本发明的自调准非易失存储单元的制造步骤。图2I所示为最终的存储单元结构。图2J是图2H的不同剖面图。
图3是本发明的非易失存储单元的另一较佳实施例。
具体实施方式
图2H所示为本发明的一非易失存储单元200的最后结构和操作，可通过其制造步骤对其了解更多。参照图2A，本发明的非易失存储单元的制造过程开始时，为用作说明，使用一P型半导体衬底204。厚度大约为300(1＝10-10m)的氧化硅(SiO2)层208在衬底204上形成。在下一个步骤，第一多晶硅(多1)层212被淀积在氧化硅层208上。然后，多1层212的多余部份被蚀刻，只留下如图2A所示的多1区212，该留下的多1区212在以后用作图2H所示存储单元200的浮动栅极212，239，251的一部份。在下一个步骤中，以离子轰击法在n+区216和220植入离子。多1区212可以用作掩模。换句话说，n+区216和220以多1区212的两对边作自调准。
参照图2B，光致抗蚀剂掩模224使用在湿蚀刻掉氧化硅层208的一部份，使暴露出n+区216的表面228。然后，移除掩模224。
参照图2C，在结构上形成一厚度为70并完全覆盖包括表面228的结构的薄氧化硅层232。
参照图2D，所示为淀积第二多晶硅(多2)层236以覆盖薄氧化硅层232。然后，多2层236被干蚀刻，只留下如图2E所示包围多1区212的一多2侧壁分隔件239。该蚀刻操作可利用一各向异性(anisotropic)蚀刻方法实现。此时，由薄氧化硅层232使多2侧壁分隔件239与多1区212电隔离。
参照图2F，厚度为大约70的第二薄氧化物层242在结构上形成，并完全覆盖包括侧壁分隔件239的该结构。该第二薄氧化物层用于提供一新的氧化物层，用于随后在其上生长下述的多晶硅层(多3)。在新氧化物层上242形成后续的多晶硅层是有利的，因为可减少漏泄电流以及其它在严重氧化了的表面形成一多晶硅层所伴生问题。
参照图2G，光致抗蚀剂掩模245使用在湿蚀刻掉薄氧化硅层232和242的一部份，以暴露出在多1区212上的表面248。然后，移除掩模245。
参照图2H，淀积第三多晶硅(多3)层251以覆盖整个结构。这薄的多3层251通过表面248与多1区212有电接触。然后，干蚀刻掉多3层251的多余部份，只留下如图2H所示必要的部份251。
图2H所示结构也可在图2J中从一不同的剖面图看到，它沿图2H中的2J-2J线剖切，和沿图2J中的2H-2H线剖切。
参照图2I，淀积一绝缘的ONO(氧化物/氮化物/氧化物)层254以覆盖结构。然后，使用掩模除去绝缘ONO层254以左的多余部份。在下一个步骤，淀积第四多晶硅(多4)层257覆盖整个结构。
然后，使用掩模除去如图2I所示多4层257两边的多余部份。绝缘ONO层254和多4层的结构与及它们的制造方法在现有技术中是公知的，所以不在此详述。
如图2I所示的最后结构为一非易失性存储单元200。多1区212，多2侧壁分隔件239和多3层251形成一存储单元200的浮动栅极212，239，251。多4层257形成存储单元200的控制栅极257。浮动栅极212，239，251和控制栅极257，彼此由绝缘ONO层254分隔，形成第一平行板电容器(未显示)。而浮动栅极212，239，251和衬底204形成第二平行板电容器(未显示)。第一平行板电容器和第二平行板电容器串联。第二平行板电容器两块平行板之间的绝缘层有两个绝缘部份。第一绝缘部份260是薄的，由薄氧化硅层232和242组成。该第一绝缘部份260从多3层251的最左边缘延伸到多2侧壁分隔件239的最右边缘。氧化硅层208的第二绝缘部份263位于多1区212之下，该第二绝缘部份263实质上比该第一绝缘部份260厚。
最初看，该两绝缘部份260和263应该是厚的，以使第二平行板电容器的电容维持低值，从而使存储单元200的耦合比率维持高值。但是，这样一个高耦合比率不会使单元的编程进行得更加容易，因为由于高的耦合比率，虽然在控制栅极257和漏极216之间的电压差的大部分会出现在浮动栅极212，232，519和漏极216之间，但电子以隧道贯穿方式通过厚的绝缘部份260和263仍会是困难的。本发明的存储单元200解决了这个问题，做法是把绝缘部份260做成薄而小。结果，绝缘部份260成为一条通路(或隧道氧化物区)，使电子以隧道贯穿方式从漏极216进入多2侧壁分隔件239，该多2侧壁分隔件239是用于储单元200编程的浮动栅极212，239，251的部份。使绝缘部份260变薄会增加第二平行板电容器的电容。但是，因为绝缘部份260的面积与绝缘部份263的面积相比是较小的，为使电子以隧道贯穿方式进入浮动栅极212，239，251，第二平行板电容器上所增加的电容与如果使两绝缘部份260和263同时变薄所增加的电容相比，是较少的。结果是，这使电子更容易地以隧道贯穿方式从漏极216通过薄的绝缘部份260进入多2侧壁分隔件239，该侧壁分隔件239是浮动栅极212，239，251的部份从而对存储单元200进行编程。
对存储单元200进行的编程，可藉施加一高电压(例如12V-15V)于控制栅极257，及施加地电位于漏极216和源极220完成。在Fowler-Nordheim隧道效应之下，电子将以隧道贯穿方式通过薄的绝缘部份260进入属于浮动栅极212，239，251一部分的多2侧壁分隔件239。被困在浮动栅极212，239，251里的电子增加了存储单元200的阈电压，使得在读取模式中，漏极216和源极220之间没有导电通道。换句话说，一个已编程的存储单元200代表逻辑0。
未被编程的存储单元200在它的浮动栅极212，239，251里没有被困的电子，因而有正常的阈电压。在读取模式中，一未被编程的存储单元200在其漏极216和源极220之间的绝缘部份263之下形成一导电通道。换句话说，一个未被编程的存储单元200代表逻辑1。
在读取模式期间，相对于源极220施加于存储单元200的控制栅极257的电压必须高于一未被编程单元的正常阈电压，但必须低于已编程的存储单元所增加了的阈电压。结果是，在读取模式期间，所选的已编程存储单元200不导通，而所选的未被编程存储单元200导通。
擦除一已编程存储单元200的运作可藉施加一高电压(例如12V)于漏极216，而施加地电位于控制栅极257和源极220。被困在浮动栅极212，239，251里的电子以隧道贯穿方式通过薄的绝缘部份260进入漏极216。从而，该单元成为未被编程的。
参照图3，所示为另一实施例，其中的存储单元300与图2I的存储单元200是相同的，只是薄氧化硅层232从多1区212的顶部被完全地移除，该移除是使用一个化学-机械抛光(CMP)方法，以便暴露出多1区212的表面248。之后，多3层251，绝缘的ONO层254和多4层257依次在结构上形成，如图2H所示的存储单元200的情形那样。
本发明的非易失存储单元还包括一在现有技术中是公知的选择晶体管，因此不在此论述。
Claims (12)
1.一种在半导体衬底上制造一自调准非易失存储单元的方法，其步骤包括：
在所述衬底上形成第一绝缘层；
在所述第一绝缘层上形成一主浮动栅极区；
修改与所述主浮动栅极区之一边相邻的所述第一绝缘层的第一部份，使其形成一薄绝缘区，所述薄绝缘区与所述主浮动栅极区之下的所述第一绝缘层的第二部份相比较薄；
在所述薄绝缘区之上形成一小侧壁分隔件；
在所述第一绝缘层及所述小侧壁分隔件之上形成第二绝缘层；
移除所述第二绝缘层的一部份及所述主浮动栅极区之上的所述薄绝缘层，以暴露出所述主浮动栅极区顶部的一表面；
在所述小侧壁分隔件及所述主浮动栅极区上形成薄连接层，并与之物理接触，所述薄连接层通过所述表面与所述主浮动栅极区接触，从而所述小侧壁分隔件与所述主浮动栅极区电连接，并且由此所述主浮动栅极区、所述小侧壁分隔件和所述薄连接层形成所述非易失存储单元的一浮动栅极；
至少在所述浮动栅极之上形成第三绝缘层；以及
在所述第二绝缘层之上及至少在所述浮动栅极之上方形成一控制栅极。
2.根据权利要求1所述的方法，其特征在于，修改所述第一绝缘层的第一部份的步骤包括：
移除所述第一绝缘层的所述第一部份；以及
从曾经是所述第一绝缘层的第一部份形成所述薄绝缘层。
3.根据权利要求2所述的方法，其特征在于，形成一小侧壁分隔件的步骤包括：
至少在所述薄绝缘区之上形成一导电层；以及
蚀刻所述导电层以便形成小侧壁分隔件。
4.根据权利要求3所述的方法，其特征在于蚀刻导电层包括各向异性蚀刻。
5.根据权利要求1所述的方法，其特征在于，形成所述薄绝缘区的步骤包括：
至少在曾经是所述第一绝缘层的第一部份之上以及在主浮动栅极区之上形成一薄绝缘层。
6.根据权利要求5所述的方法，其特征在于，形成一小侧壁分隔件的步骤包括：
至少在所述薄绝缘区之上形成一导电层；以及
蚀刻所述的导电层以便形成所述小侧壁分隔件。
7.根据权利要求5所述的方法，其特征在于蚀刻所述的导电层包括各向异性蚀刻。
8.根据权利要求7所述的方法，其特征在于形成第三绝缘层包括形成一氧化物/氮化物/氧化物(ONO)层。
9.根据权利要求1所述的方法，其特征在于，形成一小侧壁分隔件的步骤包括：
至少在所述薄绝缘区之上形成一导电层；以及
蚀刻所述导电层以便形成所述小侧壁分隔件。
10.根据权利要求1所述的方法，其特征在于蚀刻所述的导电层包括各向异性蚀刻。
11.根据权利要求1所述的方法，其特征在于移除所述主浮动栅极区之上的所述薄绝缘层的一部份包括使用光致抗蚀剂掩模及湿蚀刻，以便帮助移除所述薄绝缘层的一部份。
12.根据权利要求1所述的方法，其特征在于移除所述主浮动栅极区之上的所述薄绝缘层的一部份包括利用化学—机械抛光方法，以便移除所述薄绝缘层的一部份。
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| US10/236,670 US6624029B2 (en) | 2000-11-30 | 2002-09-06 | Method of fabricating a self-aligned non-volatile memory cell |
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| US6831325B2 (en) * | 2002-12-20 | 2004-12-14 | Atmel Corporation | Multi-level memory cell with lateral floating spacers |
| US6878986B2 (en) * | 2003-03-31 | 2005-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded flash memory cell having improved programming and erasing efficiency |
| US20050239250A1 (en) * | 2003-08-11 | 2005-10-27 | Bohumil Lojek | Ultra dense non-volatile memory array |
| US7154779B2 (en) * | 2004-01-21 | 2006-12-26 | Sandisk Corporation | Non-volatile memory cell using high-k material inter-gate programming |
| US7476926B2 (en) * | 2005-01-06 | 2009-01-13 | International Business Machines Corporation | Eraseable nonvolatile memory with sidewall storage |
| US8099783B2 (en) * | 2005-05-06 | 2012-01-17 | Atmel Corporation | Security method for data protection |
| US20080119022A1 (en) * | 2006-11-22 | 2008-05-22 | Atmel Corporation | Method of making eeprom transistors |
| US8642441B1 (en) * | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| US9318337B2 (en) * | 2013-09-17 | 2016-04-19 | Texas Instruments Incorporated | Three dimensional three semiconductor high-voltage capacitors |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4833096A (en) | 1988-01-19 | 1989-05-23 | Atmel Corporation | EEPROM fabrication process |
| US5021848A (en) | 1990-03-13 | 1991-06-04 | Chiu Te Long | Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof |
| US5108939A (en) * | 1990-10-16 | 1992-04-28 | National Semiconductor Corp. | Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region |
| US5618742A (en) | 1992-01-22 | 1997-04-08 | Macronix Internatioal, Ltd. | Method of making flash EPROM with conductive sidewall spacer contacting floating gate |
| US5477068A (en) | 1992-03-18 | 1995-12-19 | Rohm Co., Ltd. | Nonvolatile semiconductor memory device |
| US5479368A (en) | 1993-09-30 | 1995-12-26 | Cirrus Logic, Inc. | Spacer flash cell device with vertically oriented floating gate |
| US5640031A (en) | 1993-09-30 | 1997-06-17 | Keshtbod; Parviz | Spacer flash cell process |
| JP3403877B2 (ja) | 1995-10-25 | 2003-05-06 | 三菱電機株式会社 | 半導体記憶装置とその製造方法 |
| KR100192546B1 (ko) * | 1996-04-12 | 1999-06-15 | 구본준 | 플래쉬 메모리 및 이의 제조방법 |
| DE19638969C2 (de) | 1996-09-23 | 2002-05-16 | Mosel Vitelic Inc | EEPROM mit einem Polydistanz-Floating-Gate und Verfahren zu deren Herstellung |
| US5963806A (en) | 1996-12-09 | 1999-10-05 | Mosel Vitelic, Inc. | Method of forming memory cell with built-in erasure feature |
| JP3183396B2 (ja) | 1997-11-20 | 2001-07-09 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
| JPH11186416A (ja) * | 1997-12-19 | 1999-07-09 | Rohm Co Ltd | 不揮発性半導体記憶装置およびその製造方法 |
| US5972752A (en) | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
| US6043530A (en) | 1998-04-15 | 2000-03-28 | Chang; Ming-Bing | Flash EEPROM device employing polysilicon sidewall spacer as an erase gate |
| US6074914A (en) | 1998-10-30 | 2000-06-13 | Halo Lsi Design & Device Technology, Inc. | Integration method for sidewall split gate flash transistor |
| US6479351B1 (en) * | 2000-11-30 | 2002-11-12 | Atmel Corporation | Method of fabricating a self-aligned non-volatile memory cell |
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| WO2004023543A1 (en) | 2004-03-18 |
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| CA2494527A1 (en) | 2004-03-18 |
| TW200406890A (en) | 2004-05-01 |
| US20030013255A1 (en) | 2003-01-16 |
| NO20051713L (no) | 2005-05-19 |
| TWI236734B (en) | 2005-07-21 |
| US6624029B2 (en) | 2003-09-23 |
| JP2005538549A (ja) | 2005-12-15 |
| EP1552549A4 (en) | 2008-06-04 |
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