CN1649173A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1649173A
CN1649173A CNA2005100067394A CN200510006739A CN1649173A CN 1649173 A CN1649173 A CN 1649173A CN A2005100067394 A CNA2005100067394 A CN A2005100067394A CN 200510006739 A CN200510006739 A CN 200510006739A CN 1649173 A CN1649173 A CN 1649173A
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安武信昭
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Abstract

本发明提供半导体器件及其制造方法，防止随着具有加高源/漏极构造的MOSFET的栅极电极的微细化而在栅极电极和源/漏极区域之间引起短路的问题。在硅衬底(10)上形成的具有加高源/漏极构造的MOSFET，包括：栅极侧壁绝缘膜，在栅极电极(20)的上部侧面具有第1氮化膜(16)、氧化膜(17)和第2氮化膜(18)构成的三层构造，在栅极电极的下部侧面具有由氧化膜(17)和第2氮化膜(18)构成的两层构造；以及加高源/漏极区域，由在硅衬底的表面有选择地形成的杂质区域和从该表面生长的杂质区域构成。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，特别涉及具有加高源/漏极(raised S/D)构造的MISFET(绝缘栅型晶体管)的构造。
背景技术
在半导体集成电路中，随着元件的高集成化，设计规则也一年一年地在逐渐缩小。在MIS型半导体集成电路中，为了抑制随着栅极长度的缩小而带来的短沟道效应，要求浅化扩散层深度。同时，需要防止因浅化扩散层深度而增大扩散层电阻。为了浅化这些扩散层深度、且将扩散层电阻保持在低水平，对只在源/漏极区域外延生长硅层而抬高的加高源/漏极构造、以及自对准地形成了硅和金属的化合物、即硅化物的自对准硅化物(salicide)构造进行组合，这是有效的。
图13(a)及图13(b)，为了说明对现有的具有加高源/漏极构造的MOSFET(栅极氧化膜型晶体管)的微细的多晶硅栅极电极进行加工时的情形，示意地示出了剖面构造。
用硬掩膜133覆盖在间隔着栅极氧化膜131淀积在硅衬底130上的多晶硅上，在这样的状态下，通过刻蚀加工形成微细的栅极长度的栅极电极134，用氧化膜(例如TEOS膜)135覆盖栅极电极侧面，形成LDD构造的浅扩散层136。之后，淀积SiN膜，通过各向异性刻蚀形成栅极侧壁绝缘膜137，形成LDD构造的深扩散层138。在上述各向异性刻蚀时，硬掩膜133的形状劣化，在栅极电极134的肩部的上方附近容易产生硬掩膜133的缺失(塌肩)或薄膜化。并且，在为了通过刻蚀除去栅极侧壁绝缘膜137的下部而进行氟氧化膜(DHF)处理时，栅极电极侧面的氧化膜135退后。
之后，为了形成加高源/漏极构造，只在源/漏极区域外延生长硅层130a，此时，如图13(b)所示，多晶硅134a容易从栅极电极134的肩部向硬掩膜133的缺失部生长，有可能因生长的多晶硅134a而在栅极电极134和加高源/漏极区域之间引起短路。
另外，在专利文献1中公开了这样的构造：在具有提高(加高)源/漏极构造的MIS型的半导体器件中，通过在从半导体衬底突出来的栅极电极的侧壁配置多个侧壁层构造，在侧壁层离开衬底而生成的间隙中填充提高源/漏极区域的至少一部分的区域。
【专利文献1】  日本特开2002-231942号公报
发明内容
如上所述，现有的具有加高源/漏极构造的MOSFET有如下问题：伴随栅极电极的微细化，有可能在栅极电极和源/漏极区域之间引起短路。
本发明就是为了解决上述问题而做出的，目的在于提供一种半导体器件，能防止伴随具有加高源/漏极构造的MOSFET的栅极电极的微细化而在栅极电极和源/漏极区域之间引起短路的问题。
本发明的半导体器件的特征在于，形成了绝缘栅型晶体管，该绝缘栅型晶体管包括：在半导体衬底上间隔着栅极绝缘膜形成的栅极电极；在上述栅极电极的上部侧面具有由第1氮化膜、氧化膜和第2氮化膜构成的三层构造，并在上述栅极电极的下部侧面具有由上述氧化膜和第2氮化膜构成的两层构造的栅极侧壁绝缘膜；以及由在上述半导体衬底的表面有选择地形成的杂质区域和从该表面生长的杂质区域构成的加高源/漏极区域。
本发明的半导体器件的制造方法的特征在于，包括以下工序：在硅衬底上间隔着栅极氧化膜依次淀积多晶硅-锗层、多晶硅层和第1氧化膜的工序；使上述第1氧化膜图形化，以上述第1氧化膜的图形为硬掩膜，通过各向异性刻蚀对上述多晶硅层/多晶硅-锗层之中的至少多晶硅层的一部分进行刻蚀的工序；在整个面上形成第1氮化膜，通过各向异性刻蚀使上述第1氮化膜图形化并形成第1栅极侧壁的工序；以上述第1氧化膜的图形和第1栅极侧壁为掩膜进行选择刻蚀，并对上述多晶硅层/多晶硅-锗层之中的多晶硅-锗层的一部分进行刻蚀，由此形成具有多晶硅-锗层的下部比上层的多晶硅层细的形状的栅极电极的工序；在上述硅衬底的表面有选择地形成源/漏极区域的浅扩散层的工序；在整个面上依次淀积第2氧化膜和第2氮化膜后，用光刻法和各向异性刻蚀使上述第2氮化膜和第2氧化膜图形化，由此形成在栅极电极的侧面上部存在三重侧壁、在侧面下部存在两重侧壁的栅极电极侧壁的工序；通过选择外延生长法在上述源/漏极区域上生长硅并形成加高源/漏极区域的工序；通过离子注入法在上述硅衬底的表面形成上述源/漏极区域的深扩散层的工序；在除去上述栅极电极上的第1氧化膜后，在上述栅极电极上和上述源/漏极区域上形成硅化物层的工序；以及形成接触上述源/漏极区域的布线的工序。
发明的效果如下：
根据本发明的半导体器件及其制造方法，能防止伴随具有加高源/漏极构造的MOSFET的栅极电极的微细化而在栅极电极和源/漏极区域之间引起短路的问题。
附图说明
图1是表示具有本发明的第1实施方式涉及的加高源/漏极构造的MOSFET的制造工序的一部分的剖面图。
图2是表示接着图1的工序的工序的剖面图。
图3是表示接着图2的工序的工序的剖面图。
图4是表示接着图3的工序的工序的剖面图。
图5是表示接着图4的工序的工序的剖面图。
图6是表示接着图5的工序的工序的剖面图。
图7是表示接着图6的工序的工序的剖面图。
图8是表示接着图7的工序的工序的剖面图。
图9是表示具有本发明的第2实施方式涉及的加高源/漏极构造的MOSFET的制造工序的一部分的剖面图。
图10是表示接着图9的工序的工序的剖面图。
图11是表示具有本发明的第3实施方式涉及的加高源/漏极构造的MOSFET的制造工序的一部分的剖面图。
图12是表示接着图11的工序的工序的剖面图。
图13(a)及(b)是为了说明对现有的具有加高源/漏极构造的MOSFET的微细的多晶硅栅极电极进行加工时的情形，示意地示出了构造的剖面图。
具体实施方式
(第1实施方式)
图1～图8是表示具有本发明的第1实施方式涉及的加高源/漏极构造的MOSFET的制造工序的剖面图。
首先，如图1所示，在硅(Si)衬底10上形成浅沟的元件隔离区域(STI)11，并在整个硅衬底上形成栅极氧化膜12，之后依次淀积多晶硅-锗(poly-Si Ge)层13、多晶硅(poly-Si)层14和第1氧化膜(SiO2膜)15。
接着，如图2所示，通过光刻(Lithography)法和各向异性刻蚀使SiO2膜15图形化，以该SiO2膜15的图形为硬掩膜，通过各向异性刻蚀只对上述多晶硅层14/多晶硅-锗层13的上部(多晶硅层14)进行刻蚀。
接着，如图3所示，形成10nm左右的第1氮化膜(SiN)，通过各向异性刻蚀对第1氮化膜进行刻蚀，形成第1栅极侧壁16。接着，以上述SiO2膜15的图形和第1栅极侧壁16为掩膜进行选择刻蚀，由此对上述多晶硅层14/多晶硅-锗层13的下部(多晶硅-锗层13)进行刻蚀，形成栅极电极20。该栅极电极20如图4所示，具有多晶硅-锗层13比上层的多晶硅层14细(即，栅极电极20的下部的宽度比上部的宽度细)的凹槽形状。接着，进行离子注入，在硅(Si)衬底10的表面有选择地形成LDD(Lightly Doped Drain，轻掺杂漏极)构造的浅扩散层(扩展区域；SDE)21a。
接着，如图5所示，在依次淀积了第2氧化膜(例如TEOS氧化膜)17和第2氮化膜18后，用光刻法和各向异性刻蚀使第2氮化膜18和TEOS氧化膜17图形化，形成栅极电极侧壁。由此，在栅极电极20的侧面，只在上部存在三重侧壁(作为第1栅极侧壁16的第1氮化膜、TEOS氧化膜17和第2氮化膜18)，在下部存在两重侧壁(TEOS氧化膜17和第2氮化膜18)。
接着，如图6所示，通过选择外延生长法在源/漏极形成预定区域上生长硅(用21b表示硅生长部)，通过离子注入法在硅衬底的表面形成LDD构造的源/漏极区域的深扩散层21c，由此形成加高源/漏极区域。此时，栅极电极20的上部由作为第1栅极侧壁16的第1氮化膜覆盖，防止了栅极电极20的肩部露出，因此能抑制从栅极电极20的肩部生长多晶硅。
接着，在通过湿法刻蚀除去栅极电极20上的第1氧化膜15后，如图7所示，在栅极电极20上和加高源/漏极区域上形成硅化物层(例如NiSi层)22。
之后，如图8所示，通过通常的工序，形成接触加高源/漏极区域的布线。在此，23是第3氮化膜，24是层间绝缘膜，25是金属布线插塞(plug)和金属布线。
如上所示，根据具有第1实施方式的加高源/漏极构造的MOSFET，能得到以下所述的效果。
(1)通过只在栅极电极20的上部形成由第1氮化膜构成的侧壁16，能防止栅极电极20的肩部的露出，在形成加高源/漏极区域时，能抑制从栅极电极20的肩部生长多晶硅。
(2)通过使用可进行选择刻蚀的多晶硅层14/多晶硅-锗层13的两层构造的栅极电极20，不仅能吸收与侧壁16相当的栅极电极20的尺寸的粗度，还能实现光刻的极限尺寸以下的栅极电极长度。
(3)栅极电极20的凹槽形状对用于形成源、漏极、扩展区域的离子注入，给出偏移量(offset)(具有与偏移量间隔物同样的效果)，因此能改善短沟道效应。
(第2实施方式)
图9～图10是表示具有本发明的第2实施方式涉及的加高源/漏极构造的MOSFET的制造工序的剖面图。
首先，如图9所示，到层叠的多晶硅层14/多晶硅-锗层13上的SiO2膜15的图形化为止，与第1实施方式一样实施，然后以SiO2膜15的图形为掩膜刻蚀到多晶硅层14的中段。
接着，如图10所示，形成10nm左右的第1氮化膜，通过各向异性刻蚀对第1氮化膜进行刻蚀，形成第1栅极侧壁16，之后，以SiO2膜15的图形和第1栅极侧壁16为掩膜，对多晶硅层14/多晶硅-锗层13进行刻蚀。此时，通过进行选择刻蚀，形成具有多晶硅-锗层13比上层的多晶硅层14细的凹槽形状的栅极电极20b。以下的工序与第1实施方式相同。
(第3实施方式)
图11～图12是表示具有本发明的第3实施方式涉及的加高源/漏极构造的MOSFET的制造工序的剖面图。
首先，如图11所示，到多晶硅层14/多晶硅-锗层13上的SiO2膜15的图形化为止，与第1实施方式一样实施，然后以SiO2膜15的图形为掩膜刻蚀到多晶硅-锗层13的中段。
接着，如图12所示，形成10nm左右的第1氮化膜，通过各向异性刻蚀对第1氮化膜进行刻蚀，形成第1栅极侧壁16，之后，以SiO2膜15的图形和第1栅极侧壁16为掩膜对层叠的多晶硅层14/多晶硅-锗层13进行刻蚀。此时，通过进行选择刻蚀，形成栅极电极20a，该栅极电极20a在多晶硅-锗层13中具有没有栅极侧壁的下层部分比有栅极侧壁的上层部分细的凹槽形状。以下的工序与第1实施方式相同。

Claims (6)

1.一种半导体器件，其特征在于，形成了绝缘栅型晶体管，该绝缘栅型晶体管包括：
栅极电极，在半导体衬底上间隔着栅极绝缘膜形成；
栅极侧壁绝缘膜，在上述栅极电极的上部侧面具有由第1氮化膜、氧化膜和第2氮化膜构成的三层构造，并在上述栅极电极的下部侧面具有由上述氧化膜和第2氮化膜构成的两层构造；以及
加高源/漏极区域，由在上述半导体衬底的表面有选择地形成的杂质区域和从该表面生长的杂质区域构成。
2.如权利要求1所述的半导体器件，其特征在于：
上述加高源/漏极区域，在表面具有硅化物层。
3.如权利要求1或2所述的半导体器件，其特征在于：
上述栅极电极具有由多晶硅-锗层、多晶硅层和硅化物层构成的层叠构造。
4.如权利要求1～3中任一项所述的半导体器件，其特征在于：
上述栅极电极具有下部的宽度比上部的宽度细的形状。
5.如权利要求1～4中任一项所述的半导体器件，其特征在于：
上述源/漏极区域具有由杂质浓度低的区域和杂质浓度高的区域构成的LDD构造。
6.一种半导体器件的制造方法，其特征在于，包括以下工序：
在硅衬底上间隔着栅极氧化膜依次淀积多晶硅-锗层、多晶硅层和第1氧化膜的工序；
使上述第1氧化膜图形化，以上述第1氧化膜的图形为硬掩膜，通过各向异性刻蚀对上述多晶硅层/多晶硅-锗层之中的至少多晶硅层的一部分进行刻蚀的工序；
在整个面上形成第1氮化膜，通过各向异性刻蚀使上述第1氮化膜图形化并形成第1栅极侧壁的工序；
以上述第1氧化膜的图形和第1栅极侧壁为掩膜进行选择刻蚀，并对上述多晶硅层/多晶硅-锗层之中的多晶硅-锗层的一部分进行刻蚀，由此形成具有多晶硅-锗层的下部比上层的多晶硅层细的形状的栅极电极的工序；
在上述硅衬底的表面有选择地形成源/漏极区域的浅扩散层的工序；
在整个面上依次淀积第2氧化膜和第2氮化膜后，用光刻法和各向异性刻蚀使上述第2氮化膜和第2氧化膜图形化，由此形成在栅极电极的侧面上部存在三重侧壁、在侧面下部存在两重侧壁的栅极电极侧壁的工序；
通过选择外延生长法在上述源/漏极区域上生长硅并形成加高源/漏极区域的工序；
通过离子注入法在上述硅衬底的表面形成上述源/漏极区域的深扩散层的工序；
在除去上述栅极电极上的第1氧化膜后，在上述栅极电极上和上述源/漏极区域上形成硅化物层的工序；以及
形成接触上述源/漏极区域的布线的工序。
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