CN1638124A - 射频半导体器件及其制造方法 - Google Patents

射频半导体器件及其制造方法 Download PDF

Info

Publication number
CN1638124A
CN1638124A CNA2004100559816A CN200410055981A CN1638124A CN 1638124 A CN1638124 A CN 1638124A CN A2004100559816 A CNA2004100559816 A CN A2004100559816A CN 200410055981 A CN200410055981 A CN 200410055981A CN 1638124 A CN1638124 A CN 1638124A
Authority
CN
China
Prior art keywords
wafer
hole
inductance
cvd
pvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100559816A
Other languages
English (en)
Other versions
CN100337330C (zh
Inventor
表成奎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Key Foundry Co Ltd
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1638124A publication Critical patent/CN1638124A/zh
Application granted granted Critical
Publication of CN100337330C publication Critical patent/CN100337330C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种高频器件，包括提供一电感的第一晶片，该电感带有穿过所述第一晶片的通孔接触栓塞；及与所述第一晶片连结的第二晶片，其中所述第二晶片提供逻辑器件及在其上部的电感连接线。

Description

射频半导体器件及其制造方法
技术领域
本发明涉及一种射频集成电路及其制造方法，特别是，涉及通过充分增加其上形成元件的半导体衬底和电感之间的距离，使寄生电容最小的射频集成电路及其制造方法。
背景技术
根据信息和通讯领域范例的变化，增加了不考虑时间和地点进行通讯的需求。无线移动通讯领域已经迅速地发展来满足这样的需求。由于无线通讯的发展，要求在射频下工作的射频资源、材料、器件和电路。这些射频资源、材料、器件和电路被使用在射频域中，因而被划分为射频元件和集成电路。
射频集成电路技术包括器件制造技术、电路设计技术和射频封装技术的结合。一个具有竞争性的RF CMOS可以通过同等地提高每项技术来进行研发。特别是，对降低生产的单位成本的研究最为基本。因此，需要研发一种低价格的RF-CMOS技术，通过简化和稳定整个工艺以降低工艺的单位成本。所述RF-CMOS或Bipolar(双极)/BiCMOS(双CMOS)的主要元件包括一RF MOSFET(射频MOS场效应管)，一电感，一变容二极管，一MIM电容和一电阻。但是，在RF-CMOS和Bipolar/BiCMOS中，电感都具有低的品质因数(此后叫做Q)。为了提高射频电感的Q值，除了器件的形状外，已经建议使用厚厚地淀积低电阻金属的方法。电感的Q值根据匝数、金属线的宽度、金属线的厚度、金属线之间的间隔，半径和形状来变化。
下面将描述设计该电感的一般准则。
1)金属线之间的间隔必须最小化。这里，可以通过使电感区域最小化和使互感最大化来增加Q值。
2)在多层金属线结构的情况下，电感必须被安装在顶部金属层上，以使对衬底的寄生电容最小化。
3)金属线的形成必须尽可能宽和厚。也就是，必须获得低的串联电阻。但是，如果金属线的宽度过度增加，电感的区域将增大，这样会导致高的寄生电容及衬底损失。因此，必须设定适当的条件。
4)为了降低负互耦效应(negative mutual coupling effect)，必须使用空心电感。该电感的内径必须为金属线宽度的五倍。
5)如果匝数增加，电感的区域也会增大从而促进电阻效应。此时，寄生电容增大而减小了Q值。因此，必须设定匝数的适当条件。
除了上述的五个条件外，由于去耦，已经对在电感下插入沟槽道和增加绝缘层的厚度或者插入接地板的方法进行了研究。
为了改进电感设计的准则和解决上述去耦问题，作为射频半导体器件如RD-CMOS器件的无源元件的电感通过镶嵌工艺(damascene process)来形成。但是，当电感由镶嵌工艺来形成时，存在对增加衬底和电感之间距离的限制，使得最小化对衬底的寄生电容很困难。
在器件上形成电感的常规方法为使用具有厚度为2到6μm的厚单层金属线来减少电感金属的电阻部分，或将电感形成于较低的金属线层上而与上部平行，并且通过通孔连接电感。但是，由单层金属电感获得的Q值是受到限制的。为了形成较厚的金属电感，工艺的数量增加，由于增加了整个高度布局，也会发生工艺失败。也就是在一个芯片内形成较厚的金属电感很困难。而且，已经建议使用根据MEMS技术形成电感的方法。其为两次曝光方法(double exposure method)，用于形成厚的单一光刻胶层，并且形成大约为50μm的下沉通孔同时连接到下层金属线和电感。但是，在通过两次曝光形成均匀深度的电感线的工艺中或在移除光刻胶层后形成钝化层的工艺中，电感的结构和特性会变差。因此，已经对电感设计的准则和克服去耦的方法进行了研究。
在讨论本发明的技术对象之前，将简要地对本发明所必需的3D集成技术(3D integration technology)进行说明。
由于世界范围的国际技术竞争的加速，许多研究和进展集中到微电子系统的小型化上。芯片尺寸封装(chip scale packaging)，倒装芯片和多芯片模块已经常用于例如移动电话、手提式计算机和芯片卡的各种电子产品上。将来的电子系统要求具有各种功能的非常复杂的器件。为满足这种要求芯片的面积急速增加。这意味由多功能器件的集成带来的产量问题、由器件的复杂性带来的昂贵费用，及技术上的限制。而且，由于微电子系统的性能、多功能和可靠性，在子系统之间的连线有所限制。这些因素被认为是将来一代IC的关键性能瓶颈。3D集成技术被预期为具有最高潜力的技术以能够代替片上嵌入式系统技术。
发明内容
根据将无源元件应用到射频半导体器件例如RF-CMOS，Bipolar/SiGe和BiCMOS的准则之一，在多层金属线结构的情况下，为了使对衬底的寄生电容最小化，电感必须形成在顶部金属层上。而且，为了克服去耦，在电感中插入一沟槽道并且增加绝缘层的厚度。本发明涉及一种射频集成电路及其制造方法，它通过充分增加在其上已经形成元件的半导体衬底和电感之间的距离，通过根据为3D集成技术的芯片尺寸集成工艺(CIP)在一个特殊的晶片上形成所述电感，并且将所述晶片连结到另一其上已经形成逻辑元件的晶片上从而使寄生电容最小化。
本发明的一个方面提供一种射频集成电路，包括：提供电感的第一晶片，该电感具有穿过第一晶片的通孔接触栓塞(via contact plug)；及连结到第一晶片上的第二晶片，其中第二晶片提供在其上部的逻辑器件和电感连接线。
根据本发明的另一个方面，制造一种高频器件的方法，包括的步骤是：a)提供第一晶片，包括以下步骤：a1)在所述第一晶片上形成通孔；a2)在具有通孔的第一晶片上形成绝缘层；a3)通过对绝缘层构图而在绝缘层中形成多个第一沟槽道和第二沟槽道，其中第二沟槽道与通孔连接；a4)通过在第一沟槽道中填充导电材料形成电感并且通过在第二沟槽道中填充导电材料形成通孔接触栓塞；及a5)通过研磨第一晶片的背面露出通孔接触栓塞的底部区域；b)提供第二晶片，包括以下步骤：b1)在第二晶片上形成逻辑器件；及b2)在第二晶片上形成电感连接线；并且c)将第一晶片和第二晶片连结起来。
大的垂直通孔被形成为0.5μm到50μm的大小且1μm到300μm的深度。
第一晶片的通孔接触栓塞和电感连接线在电学上彼此连接。
附图说明
通过下面对本发明的描述并参考附图，本发明将更完整地被理解。在所附的附图中：
图1A到1G表示根据本发明优选实施例，在第一晶片上形成具有通孔接触栓塞的电感的方法的剖面图；
图2表示根据本发明优选实施例，在第二晶片上形成具有多层线结构的逻辑器件的方法的剖面图；
图3表示将图1G所示第一晶片连结图2所示第二晶片的射频半导体器件的剖面图。
具体实施方式
下面将参考附图对根据本发明优选实施例的射频集成电路和其制造方法进行详细的说明。
在所描述的情况下，一薄膜被安置在另一薄膜或半导体衬底“上”，一薄膜可直接与另一薄膜或半导体衬底接触，或者可在其中间布置第三薄膜。在附图中，为了清楚和准确地说明，每层的厚度或尺寸被放大。只要可能，相同的附图标记将在整个附图和说明中使用并且表示相同的或类似的部件。
图1A到1G表示根据本发明优选的实施例，在第一晶片上形成一具有通孔接触栓塞的电感以形成例如RF-CMOS、Bipolar/SiGe和BiCMOS的射频半导体器件的方法的剖面图。
参考图1A，通过蚀刻第一半导体衬底11的一部分形成一大的垂直通孔12。根据本发明，所述大的垂直通孔12为通过使用CIP来形成具有高性能的电感结构的基本元件。大的垂直通孔12的深度通过考虑形成有典型元件的衬底和所述电感之间的距离使其能够防止产生寄生电容而决定。也就是说，大的垂直通孔12的深度起着决定形成于晶片上的电感和衬底之间的距离的作用。因此，大的垂直通孔12被形成为具有约0.5μm到50μm的尺寸和约1μm到300μm的深度。
参考图1B，在具有大的垂直通孔12的第一半导体衬底11的一个表面上形成一绝缘层13。绝缘层13由低温氧化物(LTO)或高温氧化物(HTO)形成。当在后续工艺中形成扩散阻挡层(diffusion barrier layer)或种子层(seedlayer)时，形成的所述绝缘层防止金属离子进入衬底11。
参考图1C，光刻胶层14的涂覆用于在形成有绝缘层13的第一半导体衬底11上形成电感结构。光刻胶层14的厚度决定了形成所述电感的金属线的厚度。
参考图1D，镶嵌图形(damascene pattern)15的形成由光刻胶图形(photoresist pattern)14P来限定，光刻胶图形14P通过对光刻胶层14的一部分包括设置有大的垂直通孔12的部分进行构图来形成。镶嵌图形15在结构上被连接到大的垂直通孔12上。
参考图1E，在包括大的垂直通孔12和镶嵌图形15的第一衬底11上依次形成一扩散阻挡层16和一种子层17。扩散阻挡层16由从离子化的PVDTiN，CVD TiN，MOCVD TiN，离子化的PVD Ta，离子化PVD TaN，CVDTa，CVD TaN，CVD WN，PVD TiAlN，PVD TiSiN，PVD TaSiN，CVD TiAlN，CVD TiSiN，CVD TaSiN及其堆叠材料所组成的组群中选择一材料形成，厚度为约100到约400。种子层17由从Cu、Ag、Au、Ti和Al的组中选择的一金属并通过使用PVD方法、CVD方法、ALD方法、电镀方法或无电镀方法来形成，厚度大致为50和3000。
参考图1F，在用一导电材料填充大的垂直通孔12和所述镶嵌图形后，进行一化学机械抛光(CMP)工艺直到所述光刻胶图形14P的上表面暴露出来，使得在镶嵌图形15中形成一电感18并且在大的垂直孔12内形成通孔接触栓塞19。
形成电感18及通孔接触栓塞19的导电材料可以是Cu、Al或在半导体器件中作为典型电感材料被使用的W。
可以通过使用普通电镀工艺(general plating process)、选择性电镀工艺(selective plating process)、普通淀积工艺(general deposition process)、选择性淀积工艺(selective deposition process)或相似工艺来完成导电材料的填充工艺。
参考图1G，在电感18和通孔接触栓塞19被形成后，通过一背面研磨工艺(backside grinding process)对衬底11的背面进行研磨直到通孔接触栓塞19的背面被暴露出来。因此，形成有电感18和通孔接触栓塞19的第一晶片100被制造出来。
图2表示根据本发明优选的实施例，在第二晶片上形成具有多层线结构的逻辑器件以制造例如RF-CMOS、Bipolar/SiGe和BiCMOS的射频半导体器件的方法的剖面图。
参考图2，一器件隔离层22被形成在第二半导体衬底21上，在其上已经进行了阱形成工艺，然后通过栅形成工艺、源/漏形成工艺、接触工艺(contact process)和类似工艺，形成一PMOS晶体管23和一NMOS晶体管24。此后，通过实施多金属线形成工艺，形成第一到第五金属线25到29。这里，根据本发明的优选实施例示意性地描述为具有五个金属线层的金属线结构。但是，本发明也可以使用具有更多或更少金属线层的其它金属线结构。为了在顶部金属层上形成电感，最后形成一电感连接线30。因此，一用于形成射频半导体器件的逻辑器件被形成以作为其中不形成电感的第二晶片200。
同样，大的垂直通孔可以像在第一晶片100上一样地使用在第二晶片200上。通过使用形成具有第一晶片100的通孔接触栓塞的电感的工艺，大的垂直通孔，可以与电感连接线30同时形成。
图3表示将图1G所示的第一晶片100连结到图2所示的第二晶片200上的射频半导体器件的剖面图。在所述射频半导体器件中，第一晶片100的通孔接触栓塞19在电学上连接到第二晶片200的电感连接线30。第一晶片100和第二晶片200通过在合成气体例如氩气(Ar)气体，氮气(N2)气体，氢气(H2)+氩气(Ar)气体或类似气体的气氛中并且在约200℃到约50℃的温度下1分钟到2小时的热处理工艺被连结在一起。在所述热处理工艺中向所述晶片到晶片施加约100mbar到约10000mbar的压力。
与以前的叙述相同，根据本发明，通过形成包括所述电感的晶片和包括所述逻辑器件的晶片，并且通过使用以CIP方法形成一大的垂直通孔来将晶片连接到晶片的3D集成技术，来制造例如RF-CMOS、Bipolar/SiGe和BiCMOS的射频半导体器件。结果，由于所述电感的形成远离其中形成逻辑器件的衬底，能够使寄生电容最小化并且可期待高性能的射频半导体器件。
虽然以示例的方式参考附图对本发明进行了说明，但是并不限于此。应该明白，本领域普通技术人员在不背离本发明的范围和精神下可作出各种替代、变形和改变。

Claims (12)

1.一种高频器件，包括：
提供一电感的第一晶片，其具有穿过所述第一晶片的通孔接触栓塞；
与所述第一晶片连结的第二晶片，其中所述第二晶片提供逻辑器件及在其上部的电感连接线。
2.一种制造高频器件的方法，包括以下步骤：
a)提供第一晶片，包括以下步骤：
a1)在所述第一晶片中形成一通孔；
a2)在具有所述通孔的所述第一晶片上形成一绝缘层；
a3)通过对所述绝缘层构图而在绝缘层中形成多个第一沟槽和第二沟槽，其中所述第二沟槽与所述通孔连接；
a4)通过在所述第一沟槽中填充导电材料形成一电感并且通过在所述第二沟槽中填充导电材料形成通孔接触栓塞；及
a5)通过研磨所述第一晶片的背面露出所述通孔接触栓塞的底部区域；
b)提供第二晶片，包括以下步骤：
b1)在所述第二晶片上形成逻辑器件；及
b2)在所述第二晶片上形成电感连接线；及
c)将所述第一晶片和所述第二晶片连结，其中所述通孔接触栓塞和所述电感连接线彼此连接。
3.如权利要求2所述的方法，其中所述通孔的直径范围从0.5μm到50μm，所述通孔的深度范围从1μm到300μm。
4.如权利要求2所述的方法，其中所述绝缘层由低温氧化物(LTO)或高温氧化物(HTO)形成。
5.如权利要求2所述的方法，进一步包括以下步骤：
在具有所述第一沟槽和第二沟槽的第一晶片上形成扩散阻挡层；并且
在所述扩散阻挡层上形成种子层。
6.如权利要求5所述的方法，其中所述扩散阻挡层由从离子化的PVDTiN，CVD TiN，MOCVD TiN，离子化的PVD Ta，离子化PVD TaN，CVDTa，CVD TaN，CVD WN，PVD TiAlN，PVD TiSiN，PVD TaSiN，CVD TiAlN，CVD TiSiN和CVD TaSiN组成的组中选择的至少一种材料形成。
7.如权利要求5所述的方法，其中所述种子层由从Cu、Ag、Au、Ti和Al组成的组中选择的一种材料来形成。
8.如权利要求5所述的方法，其中所述种子层通过使用从PVD方法、CVD方法、ALD方法、电镀方法或无电镀方法组成的组中选择的一种方法来形成。
9.如权利要求5所述的方法，其中所述导电材料为从Cu、Al和W组成的组中选择的一种。
10.如权利要求2所述的方法，其中在所述步骤c)中，施加到所述第一和第二晶片上的压力范围为100mbar到10000mbar。
11.如权利要求10所述的方法，其中在所述步骤c)中，在200℃到500℃温度下进行1分钟到2小时的热处理。
12.如权利要求10所述的方法，其中所述热处理在氩气、氮气、氢气和氩气的混合气体或氢气和氮气的混合气体的环境下进行。
CNB2004100559816A 2003-12-30 2004-08-03 射频半导体器件及其制造方法 Active CN100337330C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020030100166A KR100569590B1 (ko) 2003-12-30 2003-12-30 고주파 반도체 장치 및 그 제조방법
KR100166/03 2003-12-30
KR100166/2003 2003-12-30

Publications (2)

Publication Number Publication Date
CN1638124A true CN1638124A (zh) 2005-07-13
CN100337330C CN100337330C (zh) 2007-09-12

Family

ID=34698740

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100559816A Active CN100337330C (zh) 2003-12-30 2004-08-03 射频半导体器件及其制造方法

Country Status (4)

Country Link
US (1) US7037800B2 (zh)
JP (1) JP4664013B2 (zh)
KR (1) KR100569590B1 (zh)
CN (1) CN100337330C (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102136531A (zh) * 2011-02-12 2011-07-27 西安神光安瑞光电科技有限公司 发光二极管及其制造方法
CN102844850A (zh) * 2010-04-15 2012-12-26 德克萨斯仪器股份有限公司 用于制造贯穿衬底的微通道的方法
CN103165571A (zh) * 2013-02-28 2013-06-19 江阴长电先进封装有限公司 一种新型硅基低阻电感结构及其晶圆级封装方法
CN111162166A (zh) * 2018-11-07 2020-05-15 美光科技公司 具有三维电感结构的半导体装置

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196668A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 半導体装置及びその製造方法
US7534722B2 (en) * 2005-06-14 2009-05-19 John Trezza Back-to-front via process
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
KR100694424B1 (ko) * 2006-02-17 2007-03-12 주식회사 하이닉스반도체 멀티 칩 패키지 장치 및 그 형성 방법
US8455350B2 (en) * 2006-08-18 2013-06-04 Globalfoundries Singapore Pte. Ltd. Integrated circuit system employing gate shield and/or ground shield
KR20080018052A (ko) * 2006-08-23 2008-02-27 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR100737155B1 (ko) * 2006-08-28 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자의 고주파 인덕터 제조 방법
CN101663742B (zh) * 2006-12-29 2013-11-06 丘费尔资产股份有限公司 具有贯穿芯片连接的前端处理晶片
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
KR100889556B1 (ko) * 2007-08-31 2009-03-23 주식회사 동부하이텍 반도체 소자의 인덕터 및 그 제조방법
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
KR100991220B1 (ko) 2008-07-21 2010-11-04 삼성전자주식회사 접착된 계면을 갖는 기판 내의 콘택 구조체, 이를 구비하는반도체 소자 및 이를 제조하는 방법들
JP2010067916A (ja) * 2008-09-12 2010-03-25 Panasonic Corp 集積回路装置
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
US9799562B2 (en) * 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US8362599B2 (en) * 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
JP5421742B2 (ja) * 2009-11-24 2014-02-19 パナソニック株式会社 トランス
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8466061B2 (en) 2010-09-23 2013-06-18 Infineon Technologies Ag Method for forming a through via in a semiconductor element and semiconductor element comprising the same
US8587127B2 (en) * 2011-06-15 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
KR101934045B1 (ko) 2012-03-22 2019-01-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP6012262B2 (ja) 2012-05-31 2016-10-25 キヤノン株式会社 半導体装置の製造方法
KR102031908B1 (ko) * 2013-02-06 2019-10-14 삼성전자주식회사 관통 전극을 갖는 반도체 소자 및 그 형성 방법
US9418985B2 (en) 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
US9048127B2 (en) * 2013-09-25 2015-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional circuit including shielded inductor and method of forming same
US9637375B2 (en) * 2014-04-15 2017-05-02 Taiwan Semiconductor Manufacturing Company Limited MEMS device having a getter structure and method of forming the same
US9786613B2 (en) 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
CN107731783A (zh) * 2017-11-15 2018-02-23 武汉新芯集成电路制造有限公司 一种键合晶圆及其工艺
JP7378166B2 (ja) * 2018-10-30 2023-11-13 北京航空航天大学 Ｍｅｍｓソレノイドトランス及びその製造方法
KR20220048806A (ko) * 2020-10-13 2022-04-20 현대자동차주식회사 절연 기판 및 이를 적용한 양면냉각 파워모듈

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453413A (en) * 1987-08-25 1989-03-01 Fuji Electric Co Ltd Formation of impurity diffusion layer
JP3195106B2 (ja) * 1992-03-04 2001-08-06 株式会社東芝 平面型磁気素子の製造方法
JP2001028354A (ja) * 1999-05-12 2001-01-30 Sony Corp 半導体装置の製造方法
JP4005762B2 (ja) * 1999-06-30 2007-11-14 株式会社東芝 集積回路装置及びその製造方法
JP2002057037A (ja) * 2000-08-09 2002-02-22 Fuji Electric Co Ltd 複合集積回路およびその製造方法
JP2002100733A (ja) * 2000-09-21 2002-04-05 Nec Corp 高周波集積回路装置
JP2003045961A (ja) * 2001-07-27 2003-02-14 Mitsubishi Electric Corp 多層配線構造、その多層配線構造を具備した半導体装置、インダクタおよび半導体装置の製造方法
US6744114B2 (en) * 2001-08-29 2004-06-01 Honeywell International Inc. Package with integrated inductor and/or capacitor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102844850A (zh) * 2010-04-15 2012-12-26 德克萨斯仪器股份有限公司 用于制造贯穿衬底的微通道的方法
CN102844850B (zh) * 2010-04-15 2016-08-10 德克萨斯仪器股份有限公司 用于制造贯穿衬底的微通道的方法
CN102136531A (zh) * 2011-02-12 2011-07-27 西安神光安瑞光电科技有限公司 发光二极管及其制造方法
CN103165571A (zh) * 2013-02-28 2013-06-19 江阴长电先进封装有限公司 一种新型硅基低阻电感结构及其晶圆级封装方法
CN103165571B (zh) * 2013-02-28 2015-10-28 江阴长电先进封装有限公司 一种新型硅基低阻电感结构及其晶圆级封装方法
CN111162166A (zh) * 2018-11-07 2020-05-15 美光科技公司 具有三维电感结构的半导体装置
CN111162166B (zh) * 2018-11-07 2023-12-22 美光科技公司 具有三维电感结构的半导体装置

Also Published As

Publication number Publication date
JP4664013B2 (ja) 2011-04-06
US20050139954A1 (en) 2005-06-30
CN100337330C (zh) 2007-09-12
US7037800B2 (en) 2006-05-02
JP2005197638A (ja) 2005-07-21
KR100569590B1 (ko) 2006-04-10
KR20050070527A (ko) 2005-07-07

Similar Documents

Publication Publication Date Title
CN100337330C (zh) 射频半导体器件及其制造方法
US9196670B2 (en) Through substrate features in semiconductor substrates
US6838774B2 (en) Interlocking conductor method for bonding wafers to produce stacked integrated circuits
JP5274004B2 (ja) 半導体基板内に導電性ビア構造体を製造する方法
CN102163566B (zh) 在具有三维堆叠结构的晶片中形成焊盘的方法
US6479902B1 (en) Semiconductor catalytic layer and atomic layer deposition thereof
CN100552926C (zh) 半导体器件、配线基板及其制造方法
US20020163072A1 (en) Method for bonding wafers to produce stacked integrated circuits
US20180233446A1 (en) Integrating metal-insulator-metal capacitors with air gap process flow
US20080061443A1 (en) Method of manufacturing semiconductor device
TW201036104A (en) Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
US11217560B2 (en) Die assembly and method of manufacturing the same
US9184113B1 (en) Methods of forming coaxial feedthroughs for 3D integrated circuits
US10475878B2 (en) BEOL capacitor through airgap metallization
US6803304B2 (en) Methods for producing electrode and semiconductor device
KR100577527B1 (ko) 고주파 소자 및 그 제조 방법
CN112151496B (zh) 一种内嵌电感的tsv结构及其制备方法
US20070041680A1 (en) Process for assembling passive and active components and corresponding integrated circuit
CN101131994A (zh) 半导体器件及其制造方法
CN102420103A (zh) 铜大马士革工艺金属-绝缘层-金属电容结构及制造工艺
KR100789570B1 (ko) 반도체 소자 및 그 제조방법
KR100854927B1 (ko) 반도체 소자 및 그 제조방법
US7743482B2 (en) Fabricating method of a semiconductor device
US20110156258A1 (en) Semiconductor device having through via and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: MAGNACHIP SEMICONDUCTOR LTD

Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC.

Effective date: 20090904

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090904

Address after: North Chungcheong Province

Patentee after: MagnaChip Semiconductor, Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: HYNIX SEMICONDUCTOR Inc.

TR01 Transfer of patent right

Effective date of registration: 20201020

Address after: Han Guozhongqingbeidao

Patentee after: Key Foundry Co.,Ltd.

Address before: Han Guozhongqingbeidao

Patentee before: MagnaChip Semiconductor, Ltd.

TR01 Transfer of patent right