CN1581505A - 减少漏损的半导体二极管 - Google Patents
减少漏损的半导体二极管 Download PDFInfo
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- CN1581505A CN1581505A CNA2004100392432A CN200410039243A CN1581505A CN 1581505 A CN1581505 A CN 1581505A CN A2004100392432 A CNA2004100392432 A CN A2004100392432A CN 200410039243 A CN200410039243 A CN 200410039243A CN 1581505 A CN1581505 A CN 1581505A
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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Abstract
本发明是关于在先进的互补型金属氧化物半导体(ComplementaryMetal-Oxide-Semiconductor;CMOS)科技中,做静电放电保护的半导体二极管组件。本发明的减少漏损的半导体二极管,其中,二极管100形成于一绝缘层上有硅(Silicon-On-Insulator;SOI)的基材上,其包含一置于绝缘层142上的硅层。主动区形成于此硅层中,并包含以主体区110分隔的一p+型掺杂区108与一n+型掺杂区106。一高介电常数的栅极介电层114置于主体区110上,且一栅极112置于此栅极的介电层114上。举例来说,此二极管可用来做ESD保护。
Description
技术领域
本发明涉及半导体组件的领域,特别是有关于在先进的互补型金属氧化物半导体(Complementary Metal-Oxide-Semiconductor;CMOS)科技中,做静电放电保护的半导体二极管组件。
技术背景
晶体管尺寸的缩小已导致绝缘层,例如栅极介电层,变薄。这些较薄的介电层在较低电压时会失效。因此,组件尺寸的缩小会增加对电压、电性过压(ElectricalOverstress;EOS)与静电放电(Electrostatic Discharge;ESD)的电路灵敏度。这些错误的类型在先进的半导体科技中是主要的考量。特别是对于与其它具有高于集成电路(Integrated Circuit;IC)芯片本身电压的电压的芯片或讯号相接的集成电路芯片。
以硅为基础的IC特别容易受静电放电伤害影响,例如一个含集成电路的组件的使用者身上带有静电荷,且随后碰触此含集成电路的组件。人体中引起的静电放电可产生超过5000伏特的电压。如此一个突然的高电压会灾难性地摧毁这集成电路。
因此,IC芯片通常在接口电路中含有保护装置或二极管,以提供IC芯片额外的ESD保护。Voldman等人在美国专利编号第5,629,544号,其发明题目为「有硅化物膜与沟渠隔离的半导体二极管」(Semiconductor diode with silicide films and trenchisolation),教示使用与多晶硅(Poly-silicon;poly-Si)结合的二极管结构来保护主体硅(Bulk Silicon)与绝缘层上有硅(Silicon-On-Insulator;SOI)电路。Voldman等人在美国专利编号第6,015,993号与第6,232,163号,论述了耐高电压的二极管结构在混合电压、混合讯号与模拟/数字转换的应用。这些习知的技术可运用在主体与绝缘层上有硅的晶体管科技上。
图1a绘示制作于主体硅基材12上的习知二极管10结构的剖面图。图1b绘示制作于包含基材16与埋入式氧化层18的绝缘层上有硅圆片上的习知晶体管结构14的剖面图。此组件通常被称为侧面单向双极绝缘栅极式晶体管(Lateral UnidirectionalBipolar Insulated Gate Type Transistor)或Iubistor。图1a和图1b通常也称做栅极二极管,因为栅极堆栈20位于二极管的主体区。
在这两个结构中,n+区22与p+区24形成在多晶硅栅极堆栈20的相异侧,其中多晶硅栅极堆栈20以介电材料26与基材分隔,且介电材料26通常为氧化硅。位于图1a基材与图1b主动层中的n+区22与p+区24是用以作为二极管的两极。例如图1a与图1b中的多晶硅栅极堆栈20便可与阳极(例如n+区22)相连。
发明内容
本发明的目的在提供一种做静电放电保护的半导体二极管,与先进晶体管的工艺兼容,并可减少反向漏电流。
本发明的许多方面可见于具有主体区形成于其一部分的基材的半导体二极管中。高介电常数的栅极介电材料置于主体区与栅极电极间。P型掺杂区与n型掺杂区邻近在主体区的不同侧。基材可以是半导体主体、主体硅、硅锗(silicon-germanium),或绝缘层上有硅。高介电常数的介电材料可以是氧化铝、氧化铪、氮氧化铪、硅酸铪、氧化锆、氮氧化锆、硅酸锆、氧化钇、氧化镧、氧化铈、氧化钛、氧化钽或上述材料的组合。栅极电极可以是多晶硅、多晶硅锗、金属、金属氮化物、金属硅化物或上述材料的组合。栅极电极可具有p型掺杂区与n型掺杂区。
本发明深入的方面可见于用以静电放电保护的二极管中,此二极管具有一主体区在绝缘层上有硅基材的硅层中。栅极电极以高介电常数的栅极介电材料与主体区分隔。邻近于主体区的不同侧分别掺以p型掺质和n型掺质。
本发明更深入的方面可见于制造二极管的方法中。此方法的制造步骤包括提供绝缘层上有硅基材,并定义一主动区于此基材的硅层中。高介电常数的栅极介电材料形成于此主动区,且一栅极电极沉积在栅极介电材料上。P型掺杂区与n型掺杂区定义在此主动区。
本发明的许多方面可见于定义p型掺杂区与n型掺杂区中,定义p型掺杂区与n型掺杂区的制作步骤为形成一注入掩膜版并掺杂主动区的第一部份,接着形成另一注入掩膜版并掺杂主动区的第二部份。本发明的其它方面可见于形成环绕主动区的隔离区的步骤中。
本发明所提供的半导体二极管不仅可用来保护半导体组件免受静电放电伤害,也可应用于其它以减少漏电流为设计目标的半导体组件。
附图说明
图1a与图1b所示为习知二极管的剖面图;
图2a与图2b所示为二极管组件于静电放电保护应用的示意图;
图3所示为指出漏电流路径的栅极二极管剖面图;
图4所示为本发明实施例的剖面图;
图5所示为能带图;
图6所示为本发明另一实施例的剖面图;
图7所示为本发明又一实施例的剖面图;
图8所示为实现本发明的组件剖面图;
图9所示为本发明的组件的工艺步骤流程图;
图10a至图10f所示为本发明的组件的工艺步骤的结果剖面图。
符号说明
10:晶体管
12:主体硅基材
14:晶体管
16:基材
18:埋入式氧化层
20:栅极层
22:n+区
24:p+区
26:介电材料
28:二极管串
30:漏电流
32、32’:二极管
38:输出/输入垫
100:栅极二极管
102:基材
104:浅沟渠隔离区域
106:n+型掺杂区
106a:n掺杂区
106b:n信道晶体管的源极与汲极
108:p+型掺杂区
108a、108b、108c:p掺杂区
110:主体区
112:栅极
112a、112b、112c:栅极电极
114:介电层
114a、114b、114c:介电层
116:第一漏损路径
118:第二漏损路径
120:n型掺杂区
122:p型掺杂区
122a、122b、122c:栅极电极部分区域
124:重叠区域
126:耗尽区
128:累积区
130、132、134:导电材料
136:间隙壁
136a、136b、136c:间隙壁
140:基材
142:绝缘层
144:绝缘层142的表面
146a、146b、146c:主动区
148、150:注入掩膜版
具体实施方式
上述说明已广泛地描绘出本发明的特色与技术优点,以使接下来的本发明详细说明更易于了解。形成本发明申请专利范围主题的额外特色与优点会于此后描述。熟习此技艺者应能察知,揭露的概念与特定的实施例可立即用来当作修改或设计其它结构或过程的基础,以实现本发明的同样目的。熟习此技艺者亦应知道,相等结构亦不脱离本发明的权利要求书的精神与范围。
目前较佳实施例的制作与使用详述于后。然而,应了解本发明提供许多可实施的发明概念,可实施在许多不同的情况。所讨论的特定的实施例只呈现制作与使用本发明的某些特定方式,并不能限制本发明的范围。
本发明会以特定情况的较佳实施例来描述,亦即用来保护半导体组件免受静电放电伤害的栅极二极管。然而,本发明也可应用于其它以减少漏电流为设计目标的半导体组件。
如同以下所作的更详细描述,本发明的较佳实施例与减少漏损的二极管有关。图2a与图2b绘示了这些二极管如何用于静电放电保护。图3绘示漏损路径的例子。图4至图8绘示各式实施例的二极管,图9与图10a至图10f绘示一实施例的制造过程。
图2a与图2b绘示了如何配置这些二极管来保护集成电路的例子。首先请参考图2a,第一二极管32耦合在供应电压源VDD与输出/输入垫38之间。举例来说,二极管32可包含与输出/输入垫38耦合的p型掺杂区及与供应电压源VDD耦合的n型掺杂区。第二二极管32’耦合在输出/输入垫38与参考电压Vss或接地端之间。在这情况中,p型掺杂区接地且n型掺杂区与输出/输入垫38相接。
输出/输入垫38用来指出任何可能易受高电压支配的节点。这些节点最典型的是在芯片与外界(例如:与系统连接时的外部电路或系统在组合时的操作装置)之间的输入与输出。输出/输入垫38被当做I/O垫,代表输入/输出。然而,该注意的是,在此专利中,术语I/O是指包含只有输入、只有输出以及输入与输出都有(或任何其它可能易受高电压支配的节点)的垫。
图2b绘示又一实施例,其中二极管串28代替了图2a中的单一二极管32与二极管32’。在较佳实施例中,二极管串28中的每个二极管32至少包括本发明的一二极管,如下所述。于再一实施例中,只有一个或多个(但非全部)二极管32是本发明的二极管,其余的则不是。
用来做ESD保护的半导体二极管32应具有低串联电阻、低次启始漏损(Sub-threshold Leakage)与低反向漏损。串联电阻是达成良好ESD的重要因素。ESD保护程度随着二极管串联电阻的减少而增进。串联电阻的特性在使用二极管串28与每个二极管的串联电阻降低ESD效果的混合电压环境里格外重要。
二极管的电阻大部分取决于二极管的体积、组成二极管主体的材料电阻率、电流路径的距离,以及金属硅化物薄膜电阻或与n+及p+扩散带相接的其它接触的电阻。此外,反向漏损是另一重要因素。图2a指出反向二极管漏电流30。高反向漏损导致高备用电力消耗。在某些先进的IC芯片应用中,低电力耗损特别重要。
图3绘示栅极二极管100的剖面图。在这范例中,栅极二极管100形成于主体半导体基材102上。基材102较佳是硅基材,但也可包含其它半导体,例如:锗、砷化镓或硅锗。浅沟渠隔离(Shallow Trench Isolation;STI)区域104是用来电性隔离栅极二极管100与芯片上其它组件(例如其它二极管与晶体管)。本发明亦可使用其它隔离方式,例如场效隔离(Field Isolation)。
栅极二极管100包含以主体区110分隔的n+型掺杂区106与p+型掺杂区108。栅极112置于主体区110上,并以介电层114分隔栅极112与主体区110。在所描述的实施例中,栅极包含与p型掺杂区122相邻的n型掺杂区120。在其它实施例中,其它导体可用来形成栅极112。
两条半导体栅极二极管100的反向漏损路径绘示于图3中。第一漏损路径116是一反向p-n接合漏电流,其与p-n接合面积大小有关。较小的p-n接合面积有较低漏损。第二漏损路径118是流经栅极介电层114或门极的绝缘层的漏损。第一与第二漏损路径都造成图2a指出的反向二极管漏电流30。当栅极介电材料随着组件缩小而变薄时,第二漏损部分会变大。本发明的较佳实施例教示出一可抑制第二漏损部分的组件结构,与形成此组件的方法。
利用此较佳实施例的技术,可借着使用至少包括高介电常数(high-k)材料或具有相对介电常数εr的介电材料的栅极介电材料,大大地减少在第二漏损电流路径上流动的电流。实现本发明的二极管结构的详细剖面图绘示于图4。
现在请参考图4,介电层114至少包括高介电常数的介电材料。高介电常数的介电层114较佳是具有大于约5的介电常数,更佳是具有大于约10的介电常数,再更佳是具有大于约20的介电常数。高介电常数的介电层114可以是氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅酸铪(HfSiO4)、氧化锆物(ZrO2)、氮氧化锆(ZrON)、硅酸锆(ZrSiO4)、氧化钇(Y2O3)、氧化镧(La2O3)、氧化铈(CeO2)、氧化钛(TiO2)、氧化钽(Ta2O5)或者这些材料中两种或两种以上的组合。
在较佳实施例中,高介电常数的介电层114是氧化铪。除了高介电常数的介电材料,介电层114可额外包含另一介电材料,例如:氧化硅、氮氧化硅或氮化硅。换句话说,介电层114可以是至少包括高介电常数介电材料层的堆栈介电材料。
栅极介电材料的氧化硅等效厚度(Equivalent Thickness;EOT)较佳是大于约5埃(angstrom),更佳是大于约10埃,再更佳是大于约20埃。介电层114的物理厚度可大于约5埃,较佳是大于约20埃,更佳是大于约40埃。在其它实施例中,介电层114的物理厚度可小于约100埃,较佳是小于约50埃,更佳是小于约10埃。
第二漏损路径118经过栅极112与其中一掺杂区p+型掺杂区108之间的重叠区域124。在阳极或p+型掺杂区108与接地的输出/输入垫(请参考图2a)电性相接,阴极或n+型掺杂区106与供应电压(请再次参考图2a)电性相接的例子中,沿着图4的A-A’剖面线的能带图描绘于图5。
图5的能带图绘示了接地的p+型掺杂区108与在供应电压处偏压的p型掺杂区122。这偏压组态的结果,一耗尽区126存在于p+型掺杂区108,一累积区128存在于栅极112的p型掺杂区122。累积区128是由空穴所组成。空穴从栅极112,穿过介电层114,到p+型掺杂区108的量子力隧穿(Quantum Mechanical Tunneling)导致了漏电流。借着使用高介电常数材料来当作介电层114,在同样电容下,栅极介电层可做得较厚,而较厚的栅极介电层可有效地抑制隧穿漏电流。
回到图4,可形成导电材料130,以包覆位于栅极112中的n型掺杂区120与p型掺杂区122,以及导电材料134与导电材料132分别包覆住基材的n+型掺杂区106与p+型掺杂区108。导电材料130(与导电材料132及导电材料134)可以是金属、金属氮化物、金属硅化物、金属氧化物或上述材料的组合。其中,可使用的金属例如为钼、钨、钛、钽、铂及铪。金属氮化物可使用,包括但非只限于氮化钼、氮化钨、氮化钛及氮化钽。金属硅化物可使用,包括但非只限于硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂及硅化铒。金属氧化物可使用,包括但非只限于氧化钌及氧化铟锡。
图4中的浅沟渠隔离区域104至少包括介电填充材料,较佳是氧化硅。然而,一般可知的是任何其它的介电材料或介电材料的组合亦可用来形成此浅沟渠隔离区域104。
间隙壁136形成于栅极112的侧边上,可至少包括介电材料,例如氮化硅或氧化硅。间隙壁136可为图4所示的简单间隙壁,或为此领域中已知且使用的复合间隙壁。
图6绘示本发明的另一实施例,其中栅极二极管100形成于绝缘层上有硅的基材上。在这例子中使用沟渠隔离,在此为浅沟渠隔离区域104。在图6中,绝缘层上有硅的基材较佳是具有一硅层(包含p+型掺杂区108、主体区110与n+型掺杂区106)位于基材140上的由氧化硅构成的绝缘层142上。N+型掺杂区106/p+型掺杂区108/主体区110的厚度(tSi)较佳是在约20埃至约1000埃的范围内,更佳是在约20埃至约300埃的范围内。薄硅层的使用导致小的接合区,所以有低的反向漏损。
图7绘示本发明的又一实施例,其中栅极二极管100形成于绝缘层上有硅的基材上,并使用平台隔离(Mesa Isolation)。借着使用平台隔离,未为半导体层所覆盖的绝缘层142的表面144在组件制造过程中暴露出来,而暴露出来的绝缘层142可在化学过程中蚀刻或凹进。形成一氮化物层来保护表面144可防止对绝缘层142的蚀刻。导电材料,例如金属硅化物(未绘示),可形成于栅极112与n+型掺杂区106及p+型掺杂区108上。
图8绘示本发明的替换实施例,其中栅极112至少包括金属,例如金属硅化物、金属氮化物或上述材料的组合。当以有平台隔离的SOI组件为例子时,任何在此所描述的实施例可包含一金属栅极。在这实施例中的栅极112不包含多晶硅或多晶硅锗。其中,可使用的金属例如为钼、钨、钛、钽、铂及铪。金属氮化物可使用,包括但非只限于氮化钼、氮化钨、氮化钛及氮化钽。金属硅化物可使用,包括但非只限于硅化镍物、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂及硅化铒。金属氧化物可使用,包括但非只限于氧化钌及氧化铟锡。
接着,描述制造这二极管结构的方法。图9绘示制造本发明的二极管结构的工艺步骤流程图。图10a至图10f绘示此二极管及n信道与p信道CMOS晶体管的工艺剖面图。
首先请参考图10a,SOI基材包含具有绝缘层142置于其上的基材140与半导体层144。然而,亦可使用绝缘层上有半导体基材或主体半导体基材。主动区形成于绝缘层上有硅基材的硅层上。三主动区146a、主动区146b、主动区146c(集合称为主动区146)绘示于第10b图。在此例中,二极管(或Iubistor)会形成于主动区146a,n信道晶体管会形成于主动区146b,而p信道晶体管会形成于主动区146c。其它主动区(未绘示)会包含一个或多个此类或其它组件。
在这实施例中,主动区146为隔离区所隔离,即平台隔离技术。使用平台隔离,一气隙会形成于主动区146之间,以在组件制作时隔离这些区域。在金属化之前,介电材料,例如硅氧化物,微晶玻璃(doped glass)或此类材料会填满这些沟渠区。在另一实施例中,则使用浅沟渠隔离。在此实施例中,主动区之间的沟渠用绝缘材料,例如硅氧化物填满。
介电层114接着沉积于主动区146上。在图标的实施例中,介电层114也覆盖在主动区146间埋入式绝缘层142上。这结果是选择性的。如先前所述,介电层114较佳是高介电常数材料。介电层114可利用化学气相沉积步骤或溅镀沉积步骤形成。在较佳实施例中,介电层114是先形成一接口氧化层,接着再形成高介电常数材料层。
构成栅极112的材料接着沉积于介电层114上,并被蚀刻以形成栅极电极112a、栅极电极112b与栅极电极112c,如第10c图所示。栅极电极材料较佳是多晶体硅,但亦可使用锗化硅、金属、金属硅化物、金属氮化物、金属氧化物或上述材料的组合。未被栅极112覆盖的栅极介电层114可被移除,如第10c图所示,或者被留下来覆盖主动区146。
现在请参考第10d图,使用注入掩膜版148来屏蔽主动区146b以及邻近于栅极电极112a的第一边缘的一部份主动区146a。使用第一类型的掺质来掺杂未被屏蔽的主动区146的区域108,并移除注入掩膜版148。在本发明的实施例中,第一类型的掺质是p型掺质。这掺质也可掺杂栅极112的区域122a。如第10d图所示,掺杂步骤同时在主动区146c中形成p信道晶体管的源极与汲极108c,并在主动区146a中形成二极管的p型掺杂区108a(及其它在芯片上的p型掺杂区)。
接着,如第10e图所示,形成注入掩膜版150,以使第二类型的掺质可掺入主动区146a与主动区146b的区域106,以与门极电极112a的区域120中。在本发明的实施例中,第二类型的掺质是n型掺质。在第二类型的掺质导入后,即移除注入掩膜版150。如第10e图所示,掺杂步骤同时在主动区146b中形成n信道晶体管的源极与汲极106b,并在主动区146a中形成二极管的n型掺杂区106a(及其它在芯片上的n型掺杂区)。
两种类型的掺质均可藉传统离子注入、浸入式电浆离子注入、或其它已知技术来导入。n+型掺杂区106与p+型掺杂区108通常掺杂至浓度在约1016cm-3至约1020cm-3的范围内,但较佳是掺杂至浓度大于约1019cm-3。注入掩膜版148与注入掩膜版150较佳是光阻,但也可以是氧化硅、氮化硅或其它罩幕材料。
间隙壁136可形成于栅极112的侧边上,如图10f所示。在间隙壁136形成后,额外的掺质可被导入主动区146及/或门极112中。这些步骤可兼容于用以在芯片上制作n信道和p信道晶体管的CMOS工艺。举例来说,侧壁的间隙壁136形成于晶体管的侧壁上,而额外的掺质可在晶体管注入源极/汲极时导入。当未绘示出时(例如,请参考第10d图与第10e图),屏蔽步骤较佳是用来形成更重掺杂的掺杂区。
如图10f所示,导电材料130,例如金属硅化物,可形成于栅极112与n+型掺杂区106及p+型掺杂区108上,以增加这些区域的导电性。再次地,导电材料(例如,请参考图4的导电材料130、导电材料132与导电材料134)可同时在同芯片上形成晶体管的源极、汲极与栅极,以及二极管的掺杂区与栅极。
虽然本发明及其优点已详细说明,但在不脱离本发明的权利要求书的精神和范围内,当可作各种不同的变化、取代及修改。
Claims (63)
1.一种半导体二极管,其特征在于至少包括:
一基材;
一主体区形成在部份的该基材中;
一栅极介电层位于该主体区上,其中该栅极介电层至少包括一高介电常数介电材料;
一栅极电极位于该栅极介电层上;以及
一p型掺杂区与一n型掺杂区形成于邻近该主体区的不同侧的该基材中。
2.如权利要求1所述的半导体二极管,其特征在于:该基材是一主体半导体基材。
3.如权利要求1所述的半导体二极管,其特征在于:该基材至少包括硅以及锗。
4.如权利要求1所述的半导体二极管,其特征在于:该基材是一绝缘层上有硅(silicon-on-insulator)基材,且该绝缘层上有硅基材至少包括一硅层位于一绝缘层上,其中该主体区、该p型掺杂区与该n型掺杂区形成于该硅层中。
5.如权利要求4所述的半导体二极管,其特征在于:该绝缘层为氧化硅。
6.如权利要求4所述的半导体二极管,其特征在于:该硅层的厚度在约20埃(angstrom)至约1000埃的范围内。
7.如权利要求4所述的半导体二极管,其特征在于:该硅层的厚度在约20埃至约300埃的范围内。
8.如权利要求1所述的半导体二极管,其特征在于:该栅极电极为多晶体硅、金属、金属氮化物、金属硅化物、金属氧化物、钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒、氧化钌、氧化铟锡、或其组合。
9.如权利要求8所述的半导体二极管,其特征在于:还至少包括金属硅化物形成于该栅极电极、该p型掺杂区与该n型掺杂区上。
10.如权利要求8所述的半导体二极管,其特征在于:该栅极电极的一第一部份以p型掺杂,而该栅极电极的一第二部份以n型掺杂。
11.如权利要求1所述的半导体二极管,其特征在于:该高介电常数介电材料是选自于由氧化铝、氧化铪、氮氧化铪、硅酸铪、氧化锆、氮氧化锆、硅酸锆、氧化钇、氧化镧、氧化铈、氧化钛、氧化钽与其组合所组成的一族群。
12.如权利要求1所述的半导体二极管,其特征在于:该高介电常数介电层具有一相对介电常数大于约5。
13.如权利要求1所述的半导体二极管,其特征在于:该高介电常数介电层具有一相对介电常数大于约10。
14.如权利要求1所述的半导体二极管,其特征在于:该高介电常数介电层具有一相对介电常数大于约20。
15.如权利要求1所述的半导体二极管,其特征在于:该栅极介电层具有一物理厚度小于约100埃。
16.如权利要求1所述的半导体二极管,其特征在于:该栅极介电层具有一物理厚度小于约50埃。
17.如权利要求1所述的半导体二极管,其特征在于:该p型掺杂区与该n型掺杂区中至少一者具有一掺杂浓度大于约1019cm-3。
18.如权利要求1所述的半导体二极管,其特征在于:还至少包括复数个间隙壁位于该栅极电极的侧壁上。
19.如权利要求18所述的半导体二极管,其特征在于:所述间隙壁的材料是选自于由氧化硅、氮氧化硅、氮化硅与其组合所组成的一族群。
20.一种半导体组件包括静电放电保护,其特征在于该半导体组件至少包括:
一绝缘层上有硅基材,其中该绝缘层上有硅基材至少包括一硅层位于一绝缘层上;
一第一掺杂区形成于该硅层中,且该第一掺杂区掺杂以一第一导电类型的复数个掺质;
一第二掺杂区形成于该硅层中,且该第二掺杂区掺杂以一第二导电类型的复数个掺质,其中该第二导电类型与该第一导电类型相反;
一主体区形成于该第一掺杂区与该第二掺杂区间的该硅层中;
一高介电常数栅极介电层位于该主体区上;
一栅极电极位于该高介电常数栅极介电层上;
一输入/输出垫与该第一掺杂区电性连接;以及
一参考电压节点与该第二掺杂区连接。
21.如权利要求20所述的半导体组件,其特征在于:该绝缘层至少包括氧化硅。
22.如权利要求20所述的半导体组件,其特征在于:该硅层具有一厚度在约20埃至约1000埃之间的范围内。
23.如权利要求20所述的半导体组件,其特征在于:该硅层具有一厚度在约20埃至约300埃之间的范围内。
24.如权利要求20所述的半导体组件,其特征在于:该栅极电极为多晶体硅、金属、金属氮化物、金属硅化物、金属氧化物、钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒、氧化钌、氧化铟锡、或其组合。
25.如权利要求24所述的半导体组件,其特征在于:还至少包括金属硅化物形成于该栅极电极、该第一掺杂区与该第二掺杂区上。
26.如权利要求24所述的半导体组件,其特征在于:该栅极电极的一第一部份以p型掺杂,而该栅极电极的一第二部份以n型掺杂。
27.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层是选自于由氧化铝、氧化铪、氮氧化铪、硅酸铪、氧化锆、氮氧化锆、硅酸锆、氧化钇、氧化镧、氧化铈、氧化钛、氧化钽与其组合所组成的一族群。
28.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层具有一相对介电常数大于约5。
29.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层具有一相对介电常数大于约10。
30.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层具有一相对介电常数大于约20。
31.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层具有一物理厚度小于约100埃。
32.如权利要求20所述的半导体组件,其特征在于:该高介电常数栅极介电层具有一物理厚度小于约50埃。
33.如权利要求20所述的半导体组件,其特征在于:该第一掺杂区与该第二掺杂区中至少一者具有一掺杂浓度大于约1019cm-3。
34.如权利要求20所述的半导体组件,其特征在于:还至少包括复数个间隙壁位于该栅极电极的侧壁上。
35.如权利要求34所述的半导体组件,其特征在于:所述间隙壁至少包括一材料,且该材料是选自于由氧化硅、氮氧化硅、氮化硅与其组合所组成的一族群。
36.如权利要求20所述的半导体组件,其特征在于:该第一掺杂区至少包括一p型区与该输入/输出垫电性连接,该第二掺杂区至少包括一n型区与一VDD电源供应端电性连接。
37.如权利要求20所述的半导体组件,其特征在于:该第二掺杂区至少包括一p型区与一地线电性连接,且该第二掺杂区至少包括一n型区与该输入/输出垫电性连接。
38.一种制作二极管的方法,其特征在于至少包括:
提供一绝缘层上有硅基材,其中该绝缘层上有硅基材至少包括一硅层位于一绝缘层上;
定义一主动区于该硅层中;
形成一栅极介电层在该主动区上,其中该栅极介电层至少包括一高介电常数介电材料;
形成一栅极电极在该栅极介电层上;
形成一p型掺杂区于邻近于该栅极电极的一第一边缘的该主动区中;以及
形成一n型掺杂区于邻近于该栅极电极的一第二边缘的该主动区中,其中该第一边缘与第二边缘不同侧。
39.如权利要求38所述的制作二极管的方法,其特征在于形成该p型掺杂区与该n型掺杂区的步骤至少包括:
形成一第一注入掩膜版暴露出该主动区的一第一部份;
掺杂该硅层的主动区的该第一部份;
形成一第二注入掩膜版暴露出该主动区的一第二部份;以及
掺杂该硅层的主动区的该第二部份。
40.如权利要求38所述的制作二极管的方法,其特征在于还至少包括:
形成复数个隔离区环绕该主动区;以及
掺杂该主动区。
41.如权利要求38所述的制作二极管的方法,其特征在于:该p型掺杂区与该n型掺杂区的掺杂浓度大于约1019cm-3。
42.如权利要求38所述的制作二极管的方法,其特征在于形成该栅极介电层的步骤至少包括:
形成一接口氧化层;以及
形成一高介电常数介电层。
43.如权利要求38所述的制作二极管的方法,其特征在于还至少包括形成复数个间隙壁位于该栅极电极的复数个侧边的步骤。
44.如权利要求43所述的制作二极管的方法,其特征在于:所述间隙壁的材质是选自于由氧化硅、氮氧化硅、氮化硅与其组合所组成的一族群。
45.如权利要求38所述的制作二极管的方法,其特征在于:该硅层具有一厚度在约20埃至约1000埃的范围内。
46.如权利要求38所述的制作二极管的方法,其特征在于:该硅层具有一厚度在约20埃至约300埃的范围内。
47.如权利要求38所述的制作二极管的方法,其特征在于:该栅极电极为多晶体硅、金属、金属氮化物、金属硅化物、金属氧化物、钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒、氧化钌、氧化铟锡、或其组合。
48.如权利要求47所述的制作二极管的方法,其特征在于还至少包括形成一金属硅化物于该栅极电极、该p型掺杂区与该n型掺杂区上的步骤。
49.如权利要求38所述的制作二极管的方法,其特征在于:该高介电常数介电材料是选自于由氧化铝、氧化铪、氮氧化铪、硅酸铪、氧化锆、氮氧化锆、硅酸锆、氧化钇、氧化镧、氧化铈、氧化钛、氧化钽与其组合所组成的一族群。
50.如权利要求38所述的制作二极管的方法,其特征在于:该高介电常数介电材料具有一相对介电常数大于约5。
51.如权利要求50所述的制作二极管的方法,其特征在于:该高介电常数介电材料具有一相对介电常数大于约10。
52.如权利要求51所述的制作二极管的方法,其特征在于:该高介电常数介电材料具有一相对介电常数大于约20。
53.如权利要求38所述的制作二极管的方法,其特征在于:该栅极介电层具有一物理厚度小于约100埃。
54.如权利要求53所述的制作二极管的方法,其特征在于:该栅极介电层具有一物理厚度小于约50埃。
55.一种同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于至少包括:
提供一硅层,其中该硅层至少包括复数个隔离区,且所述隔离区定义出一第一主动区、一第二主动区与一第三主动区;
形成一栅极介电层于各第一主动区、第二主动区与第三主动区上,其中该栅极介电层至少包括一高介电常数介电层;
形成一栅极电极层于该栅极介电层上;
蚀刻该栅极电极层,以形成一第一栅极电极位于该第一主动区上、一第二栅极电极位于该第二主动区上、及一第三栅极电极位于该第三主动区上;
屏蔽该第一主动区及邻近于该第二栅极电极的一第一边缘的部份第二主动区;
注入p型掺质到该第三主动区及第二主动区的未屏蔽部分;
屏蔽该第三主动区及邻近于该第二栅极电极的一第二边缘的部份第二主动区;以及
注入n型掺质到该第一主动区及邻近于该第二栅极电极的第一边缘的第二主动区的未屏蔽部分。
56.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该硅层至少包括一主体半导体基材的一上端部分。
57.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该硅层至少包括一硅层位于一绝缘层上。
58.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于形成该栅极介电层的步骤至少包括:
形成一接口氧化层;以及
形成该高介电常数介电层。
59.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于还至少包括:
形成复数个间隙壁于该第一栅极电极、该第二栅极电极、以及该第三栅极电极的侧壁上;
屏蔽该第一主动区邻近于第二栅极电极的第一边缘的第二主动区的部份;
注入p型掺质到该第三主动区及邻近于第二栅极电极的第二边缘的第二主动区的部份;
屏蔽该第三主动区及邻近于该第二栅极电极的第二边缘的第二主动区的部份;以及
注入n型掺质到该第一主动区及邻近于该第二栅极电极的第一边缘的第二主动区的部份。
60.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该栅极电极层为多晶体硅、钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒、氧化钌、氧化铟锡、或其组合。
61.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该高介电常数介电层为氧化铪、氧化铝、氮氧化铪、硅酸铪、氧化锆、氮氧化锆、硅酸锆、氧化钇、氧化镧、氧化铈、氧化钛、氧化钽物、或其组合。
62.如权利要求55所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该高介电常数介电层具有一相对介电常数大于约10。
63.如权利要求62所述的同时形成一二极管及复数个互补型金属氧化物半导体晶体管的方法,其特征在于:该高介电常数介电层具有一相对介电常数大于约20。
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US10/641,813 US20050035410A1 (en) | 2003-08-15 | 2003-08-15 | Semiconductor diode with reduced leakage |
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US8940596B2 (en) | 2011-05-05 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making structure having a gate stack |
CN102769029B (zh) * | 2011-05-05 | 2015-11-25 | 台湾积体电路制造股份有限公司 | 具有栅极叠层的器件 |
US9831235B2 (en) | 2011-05-05 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making structure having a gate stack |
CN103996679A (zh) * | 2014-06-12 | 2014-08-20 | 上海华力微电子有限公司 | Soi nmos esd器件及其制备方法 |
CN106206565A (zh) * | 2015-05-08 | 2016-12-07 | 创意电子股份有限公司 | 二极管与二极管串电路 |
CN106206565B (zh) * | 2015-05-08 | 2019-04-23 | 创意电子股份有限公司 | 二极管与二极管串电路 |
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US20050035410A1 (en) | 2005-02-17 |
TW200507267A (en) | 2005-02-16 |
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CN1331239C (zh) | 2007-08-08 |
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