CN1574348A - 半导体装置及开关元件 - Google Patents

半导体装置及开关元件 Download PDF

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Publication number
CN1574348A
CN1574348A CNA2004100593395A CN200410059339A CN1574348A CN 1574348 A CN1574348 A CN 1574348A CN A2004100593395 A CNA2004100593395 A CN A2004100593395A CN 200410059339 A CN200410059339 A CN 200410059339A CN 1574348 A CN1574348 A CN 1574348A
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Prior art keywords
semiconductor device
mosfet
electrode
chips
semiconductor
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CNA2004100593395A
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CN100388482C (zh
Inventor
吉羽茂治
福田浩和
境春彦
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1574348A publication Critical patent/CN1574348A/zh
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Publication of CN100388482C publication Critical patent/CN100388482C/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

一种半导体装置。现有单片双型MOSFET是并列两个MOSFET的芯片，使漏极电极短路的结构，故安装面积大，也不能降低漏极电极间的电阻，市场要求的小型化、薄型化也有限。本发明的半导体装置将两个MOSFET的半导体芯片的漏极电极之间直接连接，将两芯片重叠。在双型MOSFET中，不需要将漏极电极导出至外部，仅是两个栅极端子及两个源极端子，故将这四端子利用引线架或导电图案导出至外部。由此可实现装置的小型化及低导通电阻化。

Description

半导体装置及开关元件
技术领域
本发明涉及半导体装置，尤其涉及可内装于二次电池的进行电池管理的MOSFET可实现小型化的半导体装置。
背景技术
随着移动终端的普及，开始要求小型且大容量的锂离子电池。进行该锂离子电池的充放电的电池管理的保护电路衬底根据移动终端轻量化的要求，必须是更小型且能充分承受负荷短路的衬底。该保护电路装置为了内装于锂离子电池的容器内而要求小型化，运用大量使用芯片部件的COB(Chip onBoard)技术应运而生，以适应小型化的要求。但是由于将开关元件串联连接在锂离子电池上，该开关元件的导通电阻也要求极小，这在移动电话中为了延长通话时间或待机时间是必不可少的要素。
图5表示进行具体的电池管理的保护电路。将两个功率MOSFETQ1、Q2串联连接在锂离子电池LiB上，用控制器IC检测锂离子电池LiB的电压并进行两个功率MOSFETQ1、Q2的开闭控制，针对过充电、过放电或负荷短路，保护锂离子电池LiB。两个功率MOSFETQ1、Q2共同连接漏极电极D，两端配置各自的源极电极S，各自的栅极电极G与控制器IC连接。
该功率MOSFETQ1、Q2为了保护薄的栅氧化膜不被静电击穿，栅极电极和源极电极间连接有保护用双向稳压二极管。
充电时两端连接电源，充电电流沿箭头方向向锂离子电池供给并进行充电。当锂离子电池LiB过充电时，控制器IC检测电压，功率MOSFETQ2的栅电压自H(高电平)变为L(低电平)，功率MOSFETQ2断开，使电路切断，保护锂离子电池LiB。
放电时两端连接负荷，进行移动终端的工作直至规定的电压。但当锂离子电池LiB过放电时，控制器IC检测到电压，使功率MOSFETQ1的栅电压自H变为L，使功率MOSFETQ1断开，使电路切断，保护锂离子电池LiB。
在负荷短路时或流过过电流时，功率MOSFETQ1、Q2流过大电流，功率MOSFETQ1、Q2的两端电压急剧上升，故由控制器IC检测出该电压，与放电时同样，使功率MOSFETQ1断开，切断电路，保护锂离子电池LiB。但是，由于在保护电路工作前的短期间流过大电流，故对功率MOSFETQ1、Q2要求峰值漏极电流的大电流化。
这种使用两个MOSFET芯片用于电池管理，使两芯片的漏极电极通用，集成为一个芯片的所谓单片双型MOSFET的需要很高。
图6表示现有单片双型MOSFET的一例。单片双型MOSFET33将两个功率MOSFET33a、33b集成为一个芯片，表面具有源极电极11和栅极电极12。背面整面上蒸镀有金属，两个功率MOSFET33a、33b共通设置漏极电极(未图示)。各功率MOSFET33a、33b相对芯片的中心线X-X线对称配置，各自的栅垫片电极12独立配置在芯片的角部。在源极电极11之下配置有多个MOSFET的单元(セル)。
图7是将上述功率MOSFET安装在引线架上的图。图7(A)是上面图，D-D线的剖面图示于图7(B)。
引线架37是以铜为原料的冲切框架，在该框架的端板37h上利用由银膏构成的压片固定着功率MOSFET的芯片33。功率MOSFET的芯片33的下面利用金制的背面粘贴电极(未图示)形成有漏极电极，上面利用铝合金的溅射形成栅垫片电极12和源极电极11。另外，为了降低焊料及导电材料的电阻，在其上部蒸镀Au等的金属多层膜。MOSFET的漏极电极固定在框架的端板37h上，该端板37h与漏极端子37d连结。栅极电极介由栅垫片电极12利用接合引线34与栅极端子37g连接，源极电极11利用接合引线34与源极端子37s电连接。
芯片33及框架利用模型及传递模模制而被树脂密封，树脂层38构成封装外形。框架利用焊料等安装在印刷线路板上。
另外，图7中漏极电极作为漏极端子37d被引出，但在用于图5所示的保护电路的双型MOSFET的场合，仅利用各芯片的源极端子37s和栅极端子37g四个端子。
另外，如图8所示，设置分别与表面的源极电极及栅极电极连接的焊料凸点35，介由焊料凸点35与外部端子37电连接，利用倒装法安装在封装上也可以(例如参照专利文献1)。
专利文献1：特开2002-368219号公报
如上所述，用于例如锂离子电池的保护的MOSFET是使用两个MOSFET的半导体芯片，在使漏极电极相互短路的状态下，将各FET的源极电极及栅极电极引出到外部的四端子元件。
而且，这种情况下，通常采用将两个MOSFET的芯片单片化的双型MOSFET。但是，在双型MOSFET中，为了将两个芯片排列形成单片，需要一个MOSFET的两倍的面积，安装面积增大。
在如图7所示的引线接合方式的安装中，由于增加了接合引线的电阻，故存在不能降低导通电阻的问题。而在如图8所示的倒装法中，由于取代接合引线使用焊料凸点作为连接部间，故与引线接合方式相比可降低连接部件的电阻。但是，在引线接合方式中，两芯片的电流在电阻低于衬底的框架部分(R1)中流动，而在倒装法中是在衬底内流动，故增加了漏极电极间的电阻量R2，故该方法中导通电阻的降低也有限。
在倒装法中还有将金属板固定在芯片背面降低漏极电极间的电阻的方法，但安装面积需要芯片尺寸的两倍，故小型化存在问题。
发明内容
本发明就是鉴于上述问题而开发的，为了解决上述问题，本发明第一方面提供一种半导体装置，其将两个具有表面电极及背面电极的半导体芯片的背面电极之间直接连接，将所述两芯片重叠，将所述两芯片的表面电极导出至外部。
本发明第二方面提供一种半导体装置，其包括：半导体元件，其将具有表面电极及背面电极的两个半导体芯片的背面电极之间直接连接并使两芯片重叠；外部端子，其介由连接部件与所述表面电极连接；树脂层，其至少覆盖所述重叠的半导体元件。
另外，其特征在于，所述两芯片是同一图案。
其特征在于，所述两芯片是同一图案的MOSFET，将该MOSFET的漏极电极相互短路，将栅极电极及源极电极导出外部，形成4端子元件。
其特征在于，所述连接部件为金属细线。
其特征在于，所述连接部件为焊料凸点。
其特征在于，所述连接部件为金属板。
其特征在于，所述外部端子为引线架的一部分。
其特征在于，所述外部端子为埋入所述树脂层的导电图案，该导电图案的背面自所述树脂层露出。
其特征在于，所述重叠的半导体元件固定安装在绝缘性衬底表面上，所述表面电极介由设于所述绝缘性衬底的通孔与所述绝缘性衬底背面的所述外部端子连接。
本发明第三方面提供一种开关元件，其构成进行电池管理的保护电路，其特征在于，将同一图案的两个MOSFET的漏极电极相互直接连接，并将所述两个MOSFET的源极电极及栅极电极引出外部，形成四端子元件。
附图说明
图1是说明本发明的半导体装置的(A)侧面图，(B)平面图，(C)剖面图；
图2是说明本发明的半导体装置的(A)平面图，(B)剖面图，(C)剖面图；
图3是说明本发明的半导体装置的(A)平面图，(B)剖面图，(C)剖面图；
图4是说明本发明半导体装置的剖面图；
图5是说明现有技术及本发明的二次电池的充放电用保护电路的电路图；
图6是说明现有半导体装置的平面图；
图7是说明现有半导体装置的(A)平面图，(B)剖面图；
图8是说明现有半导体装置的侧面图。
具体实施方式
参照图1～图4，以MOSFET的半导体芯片为例详细说明本发明的实施例。
图1首先显示本发明的半导体元件23。图1(A)是半导体元件23的侧面图，图1(B)是一个半导体元件23a的平面图，图1(C)是图1(B)的A-A线剖面图。
如图1(A)所示，半导体元件23由第一及第二MOSFET的半导体芯片23a、23b构成。两芯片23a、23b分别在衬底表面配置多个MOSFET的单元7，具有连接在该单元7的源极电极11及与单元内的栅极电极连结的栅垫片电极12。两芯片的背面设有漏极电极19，将该漏极电极19相互间直接连接，重叠两芯片23a、23b。半导体元件23在设有单元的两主面上设置焊料凸点等连接部件24，进行两芯片23a、23b的源极电极及栅极电极的引出。
图1(B)显示第一MOSFET的芯片23a的平面图。另外，第二芯片与第一MOSFET图案相同，故省略说明。
实际动作区域16中排列有构成功率MOSFET的多个MOS晶体管的单元7。源极电极11与实际动作区域16上的各单元7的源区连接设置。栅极连结电极17与各单元7的栅极电极连接且设于实际动作区域16的周围。另外，在源极电极11，如虚线圆所示连接有焊料凸点(或接合引线)等连接部件24，进行源极电极11及栅极电极6的引出。在栅垫片电极12之下形成有保护用稳压二极管13。
如图1(C)所示，在N沟道的功率MOSFET中，在N+型半导体衬底1之上设置由N-型外延层构成的漏区2，在其上设置P型沟道层3。制作由沟道层3至漏区2的槽4，在槽4的内壁被覆栅氧化膜5，并设置由充填于槽4的多晶硅构成的栅极电极6。在与槽4邻接的沟道层3表面上形成N+型源区8，在相邻的两个源区8之间的沟道层3表面形成P+型主体接触区9，并形成MOSFET的各单元7。槽4之上由层间绝缘膜10覆盖。
源极电极11介由层间绝缘膜10设置在实际动作区域16上，与MOS晶体管的源区8接触。栅垫片电极12配置在实际动作区域16的外侧。栅垫片电极12是与源极电极11在同一工序形成的电极，在栅极电极6上延伸设置而接触。在栅垫片电极12正下方设有保护用稳压二极管13，稳压二极管13的中心与栅垫片电极12接触，最外周与源极电极11连结。
在该源极电极11和栅垫片电极12上例如设置Pd/Ti或Au/Tiw的势垒金属层14。源极电极11及栅极电极6由金凸点或焊料凸点24引出，与外部端子(在此未图示)连接，所述金凸点由镀金层在源极电极11及栅垫片电极12之上形成约25μm的高度。
漏极电极19是在半导体芯片背面设置金等的背面粘贴电极形成背面电极。
将这样形成的两个半导体芯片23a、23b如图1(A)那样固定。作为固定方法之一例，首先将晶片切割，分割为一个个半导体芯片，然后，将一个半导体芯片23b的焊料凸点24装在框架上。然后，使用焊料、共晶体、膏剂等将第二片芯片23a装在露出的半导体芯片23b的漏极电极19上，将漏极电极19相互间固定(参照图2(B))。
也可以在晶片状态下，将两张晶片相互间通过图像识别进行对位，利用焊料、共晶体、膏剂等将晶片的背面电极(漏极电极19)相互间固定，然后分割为一个个半导体芯片，形成图1(A)的半导体元件23。
本实施例的半导体元件23如上所述，是将第一及第二半导体芯片23a、23b的漏极电极19相互间直接连接，将两芯片重叠而形成的。通过将两个MOSFET的漏极电极相互间连接，使漏极电极19短路。在仅利用栅极端子及源极端子四端子的元件中，漏极端子不需要引出外部，故只要从半导体元件23的两主面分别将源极电极11及栅极电极6引出即可。也就是说，可以一个芯片的安装面积提供用于图5所示的保护电路的、双型MOSFET。另外，通过将漏极电极19相互间连接，并且，如图7所示，通过使漏极电极19相互间连接，去掉了现有电极间存在的框架(Cu)的电阻分量R1。即使与图8所示的结构相比，也可降低漏极电极间的电阻分量R2，可将漏极电极间的电阻抑制到最小限度。
图2～图4中显示将上述半导体元件23安装于封装中的例子。本发明的半导体装置由半导体元件23、外部端子27、连接部件24及树脂层28构成。
首先，将半导体元件23固定在引线架27上，用树脂层覆盖，并作为外部端子27引出。图2(A)是平面图。两芯片重叠，向纸面左侧延伸的引线与下侧的第二MOSFET23b的源极电极及栅垫片电极连接。向纸面右侧延伸的引线与上侧的第一MOSFET23a的源极电极及栅垫片电极连接。
图2(A)的B-B线剖面如图2(B)。这样，引线架为例如以铜为原料的冲切框架，第一MOSFET23a及第二MOSFET23b的栅极电极介由焊料凸点24a与作为栅极端子27g的引线连接。第一MOSFET23a及第二MOSFET23b的源极电极介由焊料凸点24a与作为源极端子27s的引线连接。
半导体元件23及引线架27利用模型及传递模模制而树脂密封，树脂层28构成封装外形。自各MOSFET的芯片引出源极端子27s、栅极端子27g，形成四端子元件，利用焊料等安装在印刷线路板(未图示)上。
在双型MOSFET的情况下，由于漏极电极19短路使用，故不需要作为漏极端子的电极的引出。因此，可如上所述进行安装，可以一个芯片的安装面积进行封装，可实现装置的小型化。
如图2(C)所示，也可以使第一MOSFET和引线架的连接部件采用焊料凸点24a，第二MOSFET和引线架的连接部件采用接合引线24b。当取代金属极、焊料凸点使用引线时，可使用现有设备，有利于降低成本。另外，通过使用引线具有便于增加配线的自由度的优点。
图3是将本发明的半导体元件安装在芯片尺寸封装上的图。在芯片尺寸封装中，半导体元件23固定在绝缘性衬底21表面，图3(A)所示的平面图的C-C线剖面图示于图3(B)。
图3(A)的虚线所示的部分是引出下侧的第二MOSFET的电极的源极端子27s、栅极端子27s。由于是芯片尺寸封装，故引出上侧的第一MOSFET的电极的端子也引出到封装背面。
如图3(B)所示，绝缘性衬底21表面上与各电极对应设有多个导电图案25，还设有与各导电图案25对应的通孔26。通孔26贯通绝缘性衬底21，内部埋设钨等导电材料。在背面上对应各通孔26具有导电材料构成的外部端子27(27s、27g)。半导体元件23的源极电极及漏极电极与对应的各导电图案25连接，由外部端子27s、27g引出外部。
这种情况下，由于所有导电图案25设在绝缘性衬底21的同一面上，故例如如图3(B)所示，第一MOSFET的连接部件采用焊料凸点24a，第二MOSFET连接部件使用金属板24c连接，与外部端子27电连接。这样，如果使用金属板24c，则与使用接合引线24b时相比可减少连接部件的电阻量。
另外，如果对特性没有影响，则也可以取代金属板24c采用接合引线24b，还可以如图3(C)所示，并用接合引线24b和金属板24c。例如面积大的源极电极的引出使用金属板24c，而栅极电极使用接合引线24b。由于栅极电极只要引出信号即可，故往往只要电阻小且配线自由度大的接合引线24b就足够了。
封装周围的四侧面由树脂层28和绝缘性衬底21的切断面形成，封装上面由平坦的树脂层28的表面形成，封装下面由绝缘性衬底21的背面侧形成。
图4是多片模制芯片尺寸封装的图，是将导电图案埋入作为支承衬底的绝缘性树脂的结构。平面图与图3(A)同样，故省略图示。
支承衬底绝缘性树脂28完全覆盖半导体芯片23及作为外部端子27的多个导电图案25，在导电图案25间充填绝缘性树脂28，与导电图案25的侧面的弯曲结构(省略图示，但实际上引线侧面是弯曲的)嵌合而牢固地结合。由绝缘性树脂28支承导电图案25。固定在导电图案25上的半导体元件23也一并被覆盖，并共通模制。树脂材料若为环氧树脂等热硬性树脂则可由传递模模制实现，聚酰亚胺树脂、硫化聚苯等热塑性树脂可由注射成型法实现。
作为一例，导电图案25是一张设有分离槽的导电箔，以使在形成图的最终结构之前，最终结构中作为外部端子的部分突出。在该导电箔上固定半导体元件23，连接各电极和导电图案25，在树脂密封后，通过对导电箔的背面进行研磨、研削、蚀刻、激光的金属蒸发等，进行化学及/或物理除去，分离为导电图案25。由此，形成在绝缘性树脂28背面露出导电图案25的背面的结构。也就是说，形成绝缘性树脂28的背面和导电图案25的背面实质上一致的结构。
各导电图案25作为外部端子27(27s、27g)露出。虽然在此省略了图示，但在其后的工序中，背面的一部分被抗蚀剂覆盖，在所需的位置开口，供给焊料。由此，在安装时，可利用焊料等的表面张力原样水平移动，进行自对准。另外，即使是这种结构，如图4(B)所示，也可以并用连接部件。
该方法比图3所示的芯片尺寸封装便宜且导电图案的形成容易，故通用性高。
另外，如图3及图4所示，如果是芯片尺寸封装，则不需要引线架的导出部分，故可使装置进一步小型化。
图2中是以冲切金属板形成的折曲式引线架为例进行说明的，但不限于此，例如通过蚀刻图案形成端板部、引线部构成的蚀刻架也可同样实施，且比折曲式封装更易小型化、薄型化。
另外，在本实施例中，显示了封装形态或连接部件的组合的一例，但不限于此，仅是由权利要求范围所限定。
另外，本实施例的半导体元件23可恰当地用于进行锂离子电池充放电的电池管理的保护电路装置。也就是说，将半导体元件23用作保护电路装置的开关元件。FET在导通状态的内部电阻小，可减小电力损失和电压损失。
再次参照图5进行说明。本实施例的半导体元件23是将两个MOSFET23a、23b的漏极电极相互间之间连接并重叠的结构，但其电路与图5所示的MOSFETQ1、Q2同样。也就是说，进行保护电路装置的开关的半导体元件23如图5所示串联连接在锂离子电池上。
在这种保护电路装置中，MOSFETQ1(MOSFET23a)构成阻止过放电开关，MOSFETQ2(MOSFET23b)构成阻止过充电开关。阻止过放电开关Q1在电池电压低于最低设定电压时，利用控制器IC切换为断开，防止电池的过放电。阻止过充电开关Q2在电池电压高于最大设定电压时，利用控制器IC切换为断开，防止电池的过充电。
MOSFET23a、23b具有分别并联连接的寄生二极管。寄生二极管使MOSFET23a、23b以分别向相反方向流动的电流保持导通状态。因此，即使例如电池电压变得高于最大设定电压，阻止过充电开关Q2断开，电池放电仍可进行。相反，即使阻止过放电开关Q1断开，充电也仍可进行。
但是，在过放电或过充电状态下，在保护电路工作前的短期间会有大电流流过，故对构成电路的开关元件要求峰值漏极电流的大电流化。
本实施例的半导体元件23将两个MOSFET的漏极电极直接连接形成重叠结构，故与现有的单片双型MOSFET相比可大幅度降低漏极电阻。也就是说，可使峰值漏极电流进一步大电流化，因此，可提供作为保护电路装置的开关元件理想的MOSFET。
根据本发明，可由一个MOSFET的芯片尺寸实现双型MOSFET，可实现小型化。另外，通过直接固定两个MOSFET的漏极电极，将漏极电极间的电阻抑制到最小限度。
也就是说，可实现下述半导体装置，该半导体装置是将两个MOSFET的芯片的漏极电极短路，引出源极端子、栅极端子四端子的双型MOSFET的，可同时实现装置小型化及低导通电阻化的半导体装置。

Claims (11)

1、一种半导体装置，其特征在于，将两个具有表面电极及背面电极的半导体芯片的背面电极之间直接连接，将所述两芯片重叠，将所述两芯片的表面电极导出至外部。
2、一种半导体装置，其特征在于，其包括：半导体元件，其将具有表面电极及背面电极的两个半导体芯片的背面电极之间直接连接并使两芯片重叠；
外部端子，其介由连接部件与所述表面电极连接；
树脂层，其至少覆盖所述重叠的半导体元件。
3、如权利要求1或2所述的半导体装置，其特征在于，所述两芯片是同一图案。
4、如权利要求1或2所述的半导体装置，其特征在于，所述两芯片是同一图案的MOSFET，将该MOSFET的漏极电极相互短路，将栅极电极及源极电极导出外部，形成4端子元件。
5、如权利要求2所述的半导体装置，其特征在于，所述连接部件为金属细线。
6、如权利要求2所述的半导体装置，其特征在于，所述连接部件为焊料凸点。
7、如权利要求2所述的半导体装置，其特征在于，所述连接部件为金属板。
8、如权利要求2所述的半导体装置，其特征在于，所述外部端子为引线架的一部分。
9、如权利要求2所述的半导体装置，其特征在于，所述外部端子为埋入所述树脂层的导电图案，该导电图案的背面自所述树脂层露出。
10、如权利要求2所述的半导体装置，其特征在于，所述重叠的半导体元件固定安装在绝缘性衬底表面上，所述表面电极介由设于所述绝缘性衬底的通孔与所述绝缘性衬底背面的所述外部端子连接。
11、一种开关元件，其构成进行电池管理的保护电路，其特征在于，将同一图案的两个MOSFET的漏极电极相互直接连接，并将所述两个MOSFET的源极电极及栅极电极引出外部，形成四端子元件。
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