WO2013104220A1 - 一种电路、阵列基板及制作方法、显示器 - Google Patents

一种电路、阵列基板及制作方法、显示器 Download PDF

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Publication number
WO2013104220A1
WO2013104220A1 PCT/CN2012/085695 CN2012085695W WO2013104220A1 WO 2013104220 A1 WO2013104220 A1 WO 2013104220A1 CN 2012085695 W CN2012085695 W CN 2012085695W WO 2013104220 A1 WO2013104220 A1 WO 2013104220A1
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Prior art keywords
thin film
film transistor
drain
gate
source
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PCT/CN2012/085695
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English (en)
French (fr)
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陈海晶
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京东方科技集团股份有限公司
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Publication of WO2013104220A1 publication Critical patent/WO2013104220A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors

Definitions

  • the present invention relates to the field of display manufacturing, and in particular, to a circuit including a plurality of connected thin film transistors, an array substrate, a manufacturing method thereof, and a display. Background technique
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • advantages such as: self-illumination, fast response, wide viewing angle, etc., can be used for flexible display, transparent display, 3D (3D) display, etc.
  • the OLED display comprises: an OLED array substrate and an organic light emitting device; wherein the structure of the organic light emitting device mainly comprises: an anode, a cathode and an organic functional layer; wherein the organic functional layer can be further subdivided into: a hole transport layer ( HTL layer), Emitting Layer (EML layer), Electron Transport Layer (ETL layer), and the like.
  • HTL layer hole transport layer
  • EML layer Emitting Layer
  • ETL layer Electron Transport Layer
  • Its main working principle is that the organic functional layer is driven by the electron field formed by the anode and the cathode, and is caused by carrier injection and recombination.
  • OLED displays can be divided into active matrix OLED displays and passive matrix OLED displays.
  • active matrix OLED displays are widely used in large-screen, high-resolution display fields.
  • a plurality of pixel units in an array form are formed on the array substrate of the active matrix OLED display, and each of the pixel units includes two thin film transistors - a switching thin film transistor as a pixel unit switch and a power line driven OLED array A driving thin film transistor on the substrate.
  • the two thin film transistors are of a bottom gate type structure, so that the drain of the switching thin film transistor needs to be connected to the gate of the driving thin film transistor through the through hole.
  • An embodiment of the present invention provides a circuit, an array base including a plurality of connected thin film transistors
  • the board and the manufacturing method and the display are used to simplify the manufacturing process in the production process of the display.
  • a circuit comprising a plurality of connected thin film transistors, comprising at least a connected first thin film transistor and a second thin film transistor, wherein a drain of the first thin film transistor and a gate of the second thin film transistor are electrically connected
  • the drain of the first thin film transistor and the gate of the second thin film transistor are disposed in the same layer.
  • An array substrate comprising: mutually perpendicular scan lines and data lines, a power line parallel to the data lines, and pixel units defined by the scan lines and the data lines; at least a first film is formed in the pixel unit a transistor, a second thin film transistor, wherein a gate of the first thin film transistor and the scan line are electrically connected, a source and the data line are electrically connected, a drain and a gate of the second thin film transistor Electrically connecting; a source of the second thin film transistor and the power line are electrically connected, a drain and an anode of the organic light emitting device are electrically connected; and a drain of the first thin film transistor and the second The gate of the thin film transistor is disposed in the same layer.
  • a display comprising: the above array substrate and an organic light emitting device; wherein the organic light emitting device comprises: an anode, a cathode and an organic functional layer.
  • a method for fabricating an array substrate comprising:
  • a top conductive film covering the through holes on the second insulating layer, and forming at least a source and a drain of the switching thin film transistor, a gate and a source and a drain of the driving thin film transistor, and a data line and a power line through a patterning process;
  • the source of the switching thin film transistor is directly connected to the data line
  • the source of the driving thin film transistor is directly connected to the power line
  • the drain of the switching thin film transistor is directly connected to the gate of the driving thin film transistor;
  • a method for fabricating an array substrate comprising:
  • a third insulating layer is formed, and a via hole for electrically connecting the anode of the organic light emitting device is formed on the third insulating layer.
  • the circuit, the array substrate, the manufacturing method, and the display provided by the embodiment of the present invention, the drain of the switching thin film transistor and the gate of the driving thin film transistor are disposed in the same layer, that is, the pattern formed by the same layer of the conductive film;
  • the ones can be directly connected without passing through the through holes, so that the manufacturing process in the display production process can be simplified under the condition that the two are electrically connected, and the yield can be improved to some extent.
  • FIG. 1 is a top plan view showing a main structure of a display including an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of Figure 1; 3A-3H are schematic diagrams of steps of a method for fabricating an array substrate in FIG. 1 and FIG. 2;
  • FIG. 4 is a schematic top plan view showing a main structure of a display including an array substrate according to a second embodiment of the present invention;
  • Figure 5 is a schematic cross-sectional view of Figure 4. detailed description
  • a Thin-Film Transistor includes: a gate, a source, and a drain.
  • the source and drain of the TFT are distinguished as follows: For a p-type TFT, the end with the higher potential is called the source, the end with the lower potential is called the drain; the end of the n-type TFT is opposite, and the end with the lower potential is called The source is the source, and the higher potential is called the drain.
  • the potential of both ends may change, causing the source and drain names to change. These factors may cause unclear or incomplete representation.
  • the input and output of the signal are uniformly referred to according to the input and output of the signal: the signal input end of the TFT is referred to as the source, and the signal output terminal of the TFT is called Specifically, in the embodiment of the present invention, one end of the switching thin film transistor electrically connected to the data line (ie, the data signal is connected) is referred to as a source, and one end electrically connected to the gate of the driving thin film transistor is called An end of the driving thin film transistor electrically connected to the power supply line (ie, connected to the power supply signal) is referred to as a source, and an end electrically connected to the anode of the organic light emitting device is referred to as a drain.
  • Embodiments of the present invention provide a circuit including a plurality of connected thin film transistors, including at least a connected first thin film transistor and a second thin film transistor, a drain of the first thin film transistor and a gate of the second thin film transistor Electrically connected, a drain of the first thin film transistor and a gate of the second thin film transistor are disposed in the same layer.
  • the drain of the first thin film transistor and the gate of the second thin film transistor which are disposed in the same layer are formed by the same patterning process.
  • Such a circuit including a connected thin film transistor and a process for fabricating the same can be applied to an integrated circuit such as a shift register circuit, a drive circuit, and the like.
  • a thin film crystal can be made The drain of the body tube and the gate of the other thin film transistor are disposed in the same layer and electrically connected, and the connection between them does not require the use of a via hole. In this way, the process can be simplified and its electrical connection performance can be increased.
  • the present invention is not limited to the case where there are only two transistors.
  • connection between the plurality of transistors can also be performed by the above method; for example, the drain of the first thin film transistor is connected to the gate of the second thin film transistor, The drain of the second thin film transistor is connected to the gate of the third thin film transistor, and the structure of the connected two-pole layer provided by the present invention can also be used to simplify the fabrication process.
  • the above circuit can be applied to a GOA (gate driver on Array) circuit in a display.
  • the GOA circuit includes a plurality of GOA units, each GOA unit corresponding to one gate line, that is, an output terminal of each GOA unit is connected to a gate line; and an output end of a GOA unit is connected to an input end of the next GOA unit.
  • Each GOA unit in a conventional GOA circuit includes a plurality of TFT structures, and at least one TFT of the same GOA unit needs to be connected to the gate of another TFT, so that the two are applied by the present invention.
  • the TFT needs to be connected in two layers of the same layer, so that there is no need to pass through holes, thereby simplifying the manufacturing process in the display production process.
  • the above circuit can also be applied to the driving of each pixel of the OLED display.
  • the display includes a plurality of pixel units arranged in an array, and each of the pixel units includes first and second thin film transistors, wherein the first thin film transistor is a switching thin film transistor, and the second thin film transistor Driving the thin film transistor; the gate of the switching thin film transistor is connected to the scan signal, the source is connected to the data signal, and the drain is electrically connected to the gate of the driving thin film transistor; the source of the driving thin film transistor is connected to the power signal, The drain and the anode of the organic light emitting device are electrically connected; the drain of the switching thin film transistor and the gate of the driving thin film transistor are disposed in the same layer.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor are disposed in the same layer, the two can be directly connected without passing through the via hole, thereby simplifying the display production under the condition that the two are electrically connected.
  • the manufacturing process in the process since the drain of the switching thin film transistor and the gate of the driving thin film transistor are disposed in the same layer, the two can be directly connected without passing through the via hole, thereby simplifying the display production under the condition that the two are electrically connected.
  • a first embodiment of the present invention provides an array substrate, with reference to FIGS. 1 and 2, including: mutually perpendicular scan lines 10 and data lines 20, power lines 30 parallel to the data lines 20, and the scan lines 10 and a pixel unit defined by the data line 20; at least a switch thin is formed in the pixel unit a transistor 40, a driving thin film transistor 50; wherein the gate 40a of the switching thin film transistor 40 and the scan line 10 are electrically connected, the source 40b and the data line 20 are electrically connected, the drain 40c and the The gate 50a of the driving thin film transistor 50 is electrically connected; the source 50b of the driving thin film transistor 50 is electrically connected to the power line 30, and the drain 50c is electrically connected to the anode 601 of the organic light emitting device 60; The drain 40c of the switching thin film transistor and the gate 50a of the driving thin film transistor are disposed in the same layer.
  • the array substrate may further include: a first insulating layer 102 for insulating, a second insulating layer 103, and a third insulating layer 104 covering the two thin film transistors 40, 50.
  • the OLED display includes: an array substrate and an organic light emitting device, if an OLED display is to be fabricated, an anode 601 of the organic light emitting device 60, an organic functional layer 602 of the organic light emitting device, and an organic light emitting device are also required to be formed on the array substrate.
  • the cathode 603 may further form a pixel defining layer 106 on the array substrate.
  • the gate, the source, the drain, and the gate, source, and drain of the scan line, the data line, the power line, and the switching thin film transistor are distributed.
  • the first deposited conductive film is referred to as the underlying conductive film
  • the later deposited conductive film is referred to as the top conductive film.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor may each be part of a pattern formed by a patterning process of the top conductive film, or may be part of a pattern formed by the underlying conductive film through a patterning process.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor may each be part of a pattern formed by the top conductive film through a patterning process, for FIG. 4 and FIG.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor may each be part of a pattern formed by the underlying conductive film through a patterning process.
  • the two can be directly connected without passing through the through hole, thereby simplifying the display production process under the condition that the two are electrically connected.
  • the production process in turn, can increase the yield to some extent.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor are both a portion of the pattern formed by the patterning process of the top conductive film;
  • the gate 40a of the switching thin film transistor 40 is a part of a pattern formed by a patterning process of the underlying conductive film; and the source 40b, the drain 40c of the switching thin film transistor, and the gate of the driving thin film transistor
  • the 50a and the source 50b and the drain 50c are part of a pattern formed by the patterning process of the top conductive film.
  • the thickness of the insulating layer (ie, the first insulating layer 102) between the gate 40a of the switching thin film transistor and the active layer 401 of the switching thin film transistor is larger than the gate 50a of the driving thin film transistor.
  • the insulating layer (ie, the second insulating layer 103) between the active layers 501 of the driving thin film transistor has a large thickness.
  • the material and characteristics of the gate insulating layer can be used to adjust the characteristics of the thin film transistor.
  • the first insulating layer 102 functions as a gate insulating layer of the switching thin film transistor 40
  • the second insulating layer 103 serves as a gate insulating layer of the driving thin film transistor 50. Since the switching transistor needs better charge retention performance, the thickness of the first insulating layer 102 can be increased to reduce the leakage current of the gate electrode, and the driving transistor needs a larger current to increase the brightness of the organic light emitting device, thereby reducing the second The thickness of the insulating layer 103 increases the on-state current.
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor may be a commonly used non-oxide semiconductor material, for example, silicon, amorphous silicon, or polysilicon;
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor is an oxide semiconductor.
  • the active layer 401 of the switching thin film transistor and/or the material of the active layer 501 of the driving thin film transistor is an oxide semiconductor containing at least one of indium, gallium, and the like.
  • the characteristics of a thin film transistor using an oxide semiconductor as an active layer are superior to those of a thin film transistor using a non-oxide semiconductor as an active layer.
  • an oxide semiconductor enhances characteristics such as mobility, on-state current, and switching characteristics of a thin film transistor with respect to amorphous silicon.
  • the oxide semiconductor has good uniformity with respect to polysilicon, does not require an increase in the compensation circuit, and has advantages in the number of masks and the difficulty in fabrication, and therefore has an advantage in producing a large-sized display.
  • the oxide semiconductor thin film can be prepared by sputtering or the like without costly additional equipment, which has cost advantages.
  • the embodiment of the invention further provides a display, comprising: any one of the above array substrate and the organic light emitting device; wherein the organic light emitting device comprises: an anode, a cathode and an organic functional layer.
  • the display includes an organic light emitting device (OLED), such a display can be generally referred to as an OLED display.
  • OLED organic light emitting device
  • the OLED display including the organic light emitting device may further include a color filter substrate provided with three color pixel structures of red, blue and green. If the organic light emitting device in the OLED display can emit light of one of red, blue, and green colors, the OLED display including the organic light emitting device may include only the above array substrate and the light emitting display device, and may further include a The transparent substrate protects the layer structure on the array substrate and the structure of the light emitting display device.
  • the embodiment of the present invention further provides the method for fabricating the array substrate in the above-mentioned FIG. 1 and FIG. 2, comprising: Step S101, referring to FIG. 3A, fabricating an underlying conductive film on the base substrate 101, and forming at least the switching thin film transistor 40 by a patterning process.
  • the gate and scan line (not shown in the figure).
  • the material of the underlying conductive film may be any metal such as molybdenum, aluminum, copper or chromium, or an alloy containing these metals, or a conductive compound such as ITO (Indium Tin Oxides). . These materials may be prepared by evaporation or by sputtering, or may be formed by fine plating to form an underlying conductive film.
  • Step S102 referring to FIG. 3B, the first insulating layer 102 is formed;
  • the first insulating layer 102 may be a thin film of silicon oxide, silicon nitride, silicon oxynitride or the like, or may be a laminated structure of these thin films. These insulating films may be prepared by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method or by sputtering.
  • PECVD Pullasma Enhanced Chemical Vapor Deposition
  • Step S103 referring to FIG. 3C, fabricating a semiconductor thin film, and forming an active layer 401 of the switching thin film transistor, an active layer 501 of the driving thin film transistor by a patterning process;
  • the active layer 40 of the switching thin film transistor is located above the gate 40a of the switching thin film transistor, and the active layer 501 of the driving thin film transistor is located in a region other than the region where the switching thin film transistor is located in the pixel unit.
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor may be a commonly used non-oxide semiconductor material, for example, silicon, amorphous silicon, or polysilicon;
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor is an oxide semiconductor.
  • the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor is an oxide semiconductor containing at least one metal of indium, gallium, and rhodium.
  • the semiconductor thin film can be produced by a sputtering method using an oxide semiconductor material, or can be prepared by a spin coating method.
  • Step S104 referring to FIG. 3D, a second insulating layer 103 is formed, and two via holes are formed on the second insulating layer 103 covering the active layer of the switching thin film transistor 40 through a via connection process to cover the driving thin film transistor 50. Two through holes are formed on the second insulating layer 103 on the active layer;
  • the four through holes in the figure expose a portion of the active layer 401 of the switching thin film transistor and the active layer 501 of the driving thin film transistor.
  • the second insulating layer may be a thin film of silicon oxide, silicon nitride, silicon oxynitride or the like, or may have a laminated structure of these thin films.
  • the above insulating film may be prepared by a PECVD method or by a sputtering method.
  • the via holes can be formed by ion reactive etching.
  • Step S105 referring to FIG. 3E, a top conductive film is formed to cover the through holes on the second insulating layer 103, and at least a source 40b and a drain 40c of the switching thin film transistor are formed by a patterning process, and the gate 50a of the thin film transistor is driven.
  • a source 50b, a drain 50c, and a data line and a power line (not shown); wherein the source 40b of the switching thin film transistor is directly connected to the data line, and the source 50b of the driving thin film transistor is directly connected to the power line, and the switch
  • the drain 40c of the thin film transistor is directly connected to the gate 50a of the driving thin film transistor.
  • the source 40b and the drain 40c of the switching thin film transistor are respectively connected to the active layer 401 of the switching thin film transistor through the via hole in the step S104; the source 50b and the drain 50c of the driving thin film transistor respectively pass through the step S104.
  • the hole is connected to the active layer 501 of the driving thin film transistor.
  • the material of the top conductive film may be any one of molybdenum, aluminum, copper, chromium, etc., or an alloy containing these metals, or a conductive compound such as ITO, or a stack of the above conductive materials. Layer structure. These materials may be prepared by evaporation or by sputtering, or may be formed by fine plating to form a top conductive film.
  • two thin film transistors can be simultaneously formed by four mask patterning processes, and the two thin film transistors can have different characteristics.
  • the drain of the first thin film transistor and the gate of the second thin film transistor are disposed in the same layer and electrically connected, and the connection between them does not require the use of via holes.
  • a third insulating layer it is also required to form a third insulating layer, and form a via hole for electrically connecting with the anode of the organic light emitting device on the third insulating layer; specifically, the following two ways, wherein the first method is utilized A planarization layer is formed on the array substrate to be fabricated, and a planarization layer is not formed on the array substrate manufactured by the second method.
  • the first way includes: Step S106-S107;
  • Step S106 referring to FIG. 3F, a third insulating layer 104 is formed.
  • the third insulating layer 104 may be silicon oxide, silicon nitride, or a multilayer structure of silicon oxide and silicon nitride.
  • the insulating film can be prepared by a PECVD method or by sputtering.
  • Step S107 referring to FIG. 3G, a planarization layer 105 is formed, and a via hole is formed at least on the third insulating layer 104 and the planarization layer 105 covering the drain 50c of the driving thin film transistor through a via connection process.
  • the material of the planarization layer may be an organic material such as polyimide or the like, and the planarization layer may be prepared by spin coating.
  • an anode 601 of an organic light-emitting device is formed to cover the via holes formed in the third insulating layer 104 and the planarization layer 105.
  • the anode 601 of the organic light-emitting device 60 is connected to the drain 50c of the driving thin film transistor through the via hole.
  • the partial structure of the OLED display shown in FIG. 2 is finally formed, and the pixel defining layer 106, the organic functional layer 602 of the organic light emitting device 60, and the cathode 603 of the organic light emitting device 60 are sequentially formed.
  • a third insulating layer is formed, and a via hole is formed on the third insulating layer by a patterning process. At this time, the fabrication of the array substrate is completed, and if the OLED display is manufactured, the anode of the organic light-emitting device, the pixel defining layer, the organic functional layer of the organic light-emitting device, and the cathode of the organic light-emitting device are continuously fabricated.
  • the above manufacturing method enables the drain of the switching thin film transistor and the gate of the driving thin film transistor to be disposed in the same layer and directly connected without passing through the through hole, thereby simplifying the production in the display production process under the condition that the two are electrically connected.
  • the process in turn, can increase the yield to some extent.
  • An embodiment of the present invention provides an array substrate.
  • the method includes: a scan line 10 and a data line 20 perpendicular to each other, a power line 30 parallel to the data line 20, and the scan line 10 and the data line.
  • the source 50b of the driving thin film transistor 50 and the power line 30 are electrically connected and leaked.
  • the pole 50c is electrically connected to the anode 601 of the organic light emitting device 60; and, the drain 40c of the switching thin film transistor and the gate 50a of the driving thin film transistor are disposed in the same layer.
  • the array substrate may further include: a first insulating layer that functions as an insulation
  • the OLED display may include: an array substrate and an organic light emitting device, if an OLED display is to be fabricated, an anode 601 of the organic light emitting device 60, an organic functional layer 602 of the organic light emitting device, and an organic light emitting device are also required to be formed on the array substrate.
  • the cathode 603 may further form a pixel defining layer 106 on the array substrate.
  • the two can be directly connected without passing through the through hole, thereby simplifying the display production process under the condition that the two are electrically connected.
  • the production process in turn, can increase the yield to some extent.
  • the drain of the switching thin film transistor and the gate of the driving thin film transistor are both part of a pattern formed by the underlying conductive film through a patterning process
  • the source 40b of the switching thin film transistor, the drain 40c, and the gate 50a and the source 50b and the drain 50c of the driving thin film transistor are part of a pattern formed by the patterning process of the underlying conductive film;
  • the gate 40a of the switching thin film transistor is a part of a pattern formed by a patterning process of the top conductive film.
  • the thickness of the insulating layer (ie, the second insulating layer 103) between the gate 40a of the switching thin film transistor and the active layer 401 of the switching thin film transistor is larger than the gate 50a of the driving thin film transistor.
  • the insulating layer (ie, the first insulating layer 102) between the active layers 501 of the driving thin film transistor has a large thickness.
  • the material and characteristics of the gate insulating layer can be used to adjust the characteristics of the thin film transistor.
  • the second insulating layer 103 functions as a switching thin film crystal
  • the gate insulating layer of the tube 40 serves as a gate insulating layer of the driving thin film transistor 50. Since the switching transistor needs better charge retention performance, the thickness of the second insulating layer 103 can be increased to reduce the leakage current of the gate electrode, and the driving transistor needs a larger current to increase the brightness of the organic light emitting device, thereby reducing the first
  • the thickness of the insulating layer 102 increases the on-state current.
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor may be a commonly used non-oxide semiconductor material, for example, silicon, amorphous silicon, or polysilicon;
  • the material of the active layer 401 of the switching thin film transistor and/or the active layer 501 of the driving thin film transistor is an oxide semiconductor.
  • the active layer 401 of the switching thin film transistor and/or the material of the active layer 501 of the driving thin film transistor is an oxide semiconductor containing at least one of indium, gallium, and the like.
  • the characteristics of a thin film transistor using an oxide semiconductor as an active layer are superior to those of a thin film transistor using a non-oxide semiconductor as an active layer.
  • an oxide semiconductor enhances characteristics such as mobility, on-state current, and switching characteristics of a thin film transistor with respect to amorphous silicon.
  • the oxide semiconductor has better uniformity, does not require an increase in the compensation circuit, and has advantages in both the number of masks and the difficulty in fabrication, and therefore has an advantage in producing a large-sized display.
  • the oxide semiconductor thin film can be prepared by sputtering or the like without additional equipment, and has a cost advantage.
  • the embodiment of the invention further provides an OLED display, comprising any of the above array substrate and the organic light emitting device provided in the embodiment of the invention; wherein the organic light emitting device comprises: an anode, a cathode and an organic functional layer.
  • the OLED display including the organic light emitting device may further include a color filter substrate provided with three color pixel structures of red, blue and green. If the organic light emitting device in the OLED display can emit light of one of red, blue, and green colors, the OLED display including the organic light emitting device may include only the above array substrate and the light emitting display device, and may further include a The transparent substrate protects the layer structure on the array substrate and the structure of the light emitting display device.
  • the embodiment of the present invention further provides the method for fabricating the array substrate in FIG. 4 and FIG. 5, including: Step S201, forming an underlying conductive film on the base substrate 101, and forming at least a source 40b of the switching thin film transistor by a patterning process,
  • the drain electrode 40c drives the gate 50a and the source 50b of the thin film transistor 50, the drain 50c, and the data line 20 and the power line 30; wherein, the switching thin film transistor 40
  • the source 40b is directly connected to the data line 20
  • the source 50b of the driving thin film transistor is directly connected to the power line 30
  • the drain 40c of the switching thin film transistor is directly connected to the gate 50a of the driving thin film transistor.
  • Step S202 forming a first insulating layer 102, and forming at least on the first insulating layer 102 covering the source 40b of the switching thin film transistor 40, the drain 40c, the driving thin film transistor source 50b, and the drain 50c through a via connection process. Through hole.
  • Step S203 forming a semiconductor film covering the via holes on the first insulating layer 102, and forming an active layer 401 of the switching thin film transistor and an active layer 501 of the driving thin film transistor by a patterning process.
  • Step S204 a second insulating layer 103 is formed.
  • Step S205 a top conductive film is formed, and at least a gate electrode 40a and a scan line 10 of the switching thin film transistor are formed by a patterning process.
  • two thin film transistors can be simultaneously formed by four mask patterning processes, and the two thin film transistors can have different characteristics.
  • the drain of the first thin film transistor and the gate of the second thin film transistor are disposed in the same layer and electrically connected, and the connection between them does not require the use of via holes.
  • a third insulating layer it is also required to fabricate a third insulating layer, and form a via hole for electrically connecting with the anode of the organic light emitting device on the third insulating layer; specifically, the following two ways, wherein the first method is used A planarization layer is formed on the array substrate, and a planarization layer is not formed on the array substrate manufactured by the second method.
  • the first way includes: Steps S206-S207.
  • Step S206 a third insulating layer 104 is formed.
  • Step S207 forming a planarization layer 105, and forming at least on the first insulating layer 102, the second insulating layer 103, the third insulating layer 104, and the planarization layer 105 covering the drain 50c of the driving thin film transistor through a via connection process. Through hole.
  • An anode 601 of the organic light emitting device 60 is formed to cover the through holes formed in the first insulating layer 102, the second insulating layer 103, the third insulating layer 104, and the planarization layer 105.
  • the pixel defining layer 106, the organic functional layer 602 of the organic light emitting device 60, and the cathode 603 of the organic light emitting device 60 are formed.
  • a third insulating layer is formed, and a via hole is formed on the third insulating layer by a patterning process. At this time, the fabrication of the array substrate is completed, and if the display is manufactured, the anode of the organic light-emitting device, the pixel defining layer, the organic functional layer of the organic light-emitting device, and the cathode of the organic light-emitting device are continuously formed.
  • the materials used in each layer and the preparation method can refer to the manufacturing method in the first embodiment, which is not mentioned in this embodiment.
  • the drawings of each step are not given for the manufacturing method in the embodiment of the present invention, those skilled in the art can make the steps shown in FIG. 4 and FIG. 5 according to the above steps and FIGS. 4 and 5. structure.
  • the manufacturing method provided by the embodiment of the invention enables the drain of the switching thin film transistor and the gate of the driving thin film transistor to be disposed in the same layer and directly connected without passing through the through hole, thereby simplifying the OLED under the condition that the two are electrically connected.
  • the manufacturing process in the production process of the display can further improve the yield to some extent.

Abstract

一种包含多个相连的薄膜晶体管的电路、阵列基板及制作方法、显示器。所述电路至少包括相连的第一薄膜晶体管（40）和第二薄膜晶体管（50），所述第一薄膜晶体管的漏极（40c）和所述第二薄膜晶体管的栅极（50a）电性连接，且同层设置。上述电路的设计可以简化显示器生产过程中的制作工艺。

Description

一种电路、 阵列基板及制作方法、 显示器 技术领域
本发明涉及显示器制造领域， 尤其涉及一种包含相连的多个薄膜晶体管 的电路、 阵列基板及制作方法、 显示器。 背景技术
OLED ( Organic Light Emitting Diode, 有机发光器件）显示器是新一代 的显示器， 与液晶显示器相比， 具有很多优点如： 自发光、 响应速度快、 宽 视角等， 可以用于柔性显示、 透明显示、 3D ( 3维）显示等。
OLED显示器包括： OLED阵列基板以及有机发光器件； 其中有机发光 器件的结构主要包括： 阳极、 阴极以及有机功能层； 其中有机功能层还可以 进一步细分为： 空穴传输功能层（ Hole Transport Layer, HTL层）、 发光功能 层（ Emitting Layer, EML层）、电子传输功能层（ Electron Transport Layer, ETL 层）等等。 其主要的工作原理是有机功能层在阳极和阴极所形成电场的驱动 下， 通过载流子注入和复合而导致发光。
OLED显示器可以分为有源矩阵 OLED显示器和无源矩阵 OLED显示 器。 目前在大屏、 高分辨率的显示领域， 有源矩阵 OLED显示器应用较为广 泛。 有源矩阵 OLED显示器的阵列基板上形成有阵列形式的多个像素单元， 每个像素单元中都包含有两个薄膜晶体管一一作为像素单元开关的开关薄膜 晶体管以及用于连接电源线驱动 OLED阵列基板上的驱动薄膜晶体管。其中， 现有技术中两个薄膜晶体管都为底栅型结构， 这就使得开关薄膜晶体管的漏 极需要通过通孔和驱动薄膜晶体管的栅极相连。 显然， 这就需要在制作完成 钝化层之后， 在两个薄膜晶体管需要连接的位置制作通孔打穿两层绝缘层， 以使得两薄膜晶体管相连。 但这样的连接工艺比较复杂， 在一定程度上影响 产率。 发明内容
本发明的实施例提供的一种包含相连的多个薄膜晶体管的电路、 阵列基 板及制作方法、 显示器， 用以简化显示器生产过程中的制作工艺。
为达到上述目的， 本发明的实施例釆用如下技术方案：
一种包含相连的多个薄膜晶体管的电路， 至少包括相连的第一薄膜晶体 管和第二薄膜晶体管， 所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的 栅极电性连接， 所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的栅极同 层设置。
一种阵列基板， 包括： 相互垂直的扫描线和数据线， 与数据线平行的电 源线， 以及所述扫描线和数据线所限定的像素单元； 在所述像素单元内至少 形成有第一薄膜晶体管、 第二薄膜晶体管； 其中， 所述第一薄膜晶体管的栅 极和所述扫描线电性连接、 源极和所述数据线电性连接， 漏极和所述第二薄 膜晶体管的栅极电性连接； 所述第二薄膜晶体管的源极和所述电源线电性连 接， 漏极和有机发光器件的阳极电性连接； 并且， 所述第一薄膜晶体管的漏 极和所述第二薄膜晶体管的栅极同层设置。
一种显示器， 包括： 上述的阵列基板以及有机发光器件； 其中， 所述有 机发光器件包括： 阳极、 阴极和有机功能层。
一种阵列基板的制作方法， 包括：
在衬底基板上制作底层导电薄膜， 并通过构图工艺至少形成开关薄膜晶 体管的栅极和扫描线；
制作第一绝缘层；
制作半导体薄膜， 并通过构图工艺形成开关薄膜晶体管的有源层、 驱动 薄膜晶体管的有源层；
制作第二绝缘层， 并通过通孔连接工艺至少在覆盖开关薄膜晶体管有源 层上的第二绝缘层上形成两个通孔， 在覆盖驱动薄膜晶体管有源层上的第二 绝缘层上形成两个通孔；
制作顶层导电薄膜， 覆盖上述第二绝缘层上的通孔， 并通过构图工艺至 少形成开关薄膜晶体管的源、 漏极， 驱动薄膜晶体管的栅极和源、 漏极以及 数据线、 电源线； 其中， 开关薄膜晶体管的源极和数据线直接相连， 驱动薄 膜晶体管的源极和电源线直接相连， 且开关薄膜晶体管的漏极和驱动薄膜晶 体管的栅极直接相连；
制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发光器件的阳极 电性连接的通孔。
一种阵列基板的制作方法， 包括：
在衬底基板上制作底层导电薄膜， 并通过构图工艺至少形成开关薄膜晶 体管的源、 漏极， 驱动薄膜晶体管的栅极和源、 漏极以及数据线、 电源线； 其中， 开关薄膜晶体管的源极和数据线直接相连， 驱动薄膜晶体管的源极和 电源线直接相连， 且开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极直接相 连；
制作第一绝缘层，并通过通孔连接工艺至少在覆盖开关薄膜晶体管源极、 漏极， 驱动薄膜晶体管源极、 漏极的第一绝缘层上分别形成通孔；
制作半导体薄膜， 覆盖上述第一绝缘层上的通孔， 并通过构图工艺形成 开关薄膜晶体管的有源层、 驱动薄膜晶体管的有源层；
制作第二绝缘层；
制作顶层导电薄膜， 并通过构图工艺至少形成开关薄膜晶体管的栅极和 扫描线；
制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发光器件的阳极 电性连接的通孔。
本发明实施例提供的电路、 阵列基板及制作方法、 显示器， 通过将开关 薄膜晶体管的漏极和驱动薄膜晶体管的栅极同层设置， 即两者是同一层导电 薄膜所形成的图案； 这样两者就可以直接相连， 而无需通过通孔， 从而能够 在实现两者电性连接的条件下， 简化显示器生产过程中的制作工艺， 进而能 够在一定程度上提高产率。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1为根据本发明第一实施例提供的一种包含阵列基板的显示器的主要 结构俯视示意图；
图 2为图 1的截面示意图； 图 3A-图 3H分别为图 1、 图 2中阵列基板制作方法的步骤示意图； 图 4为根据本发明第二实施例提供的一种包含阵列基板的显示器的主要 结构俯视示意图；
图 5为图 4的截面示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
众所周知， 薄膜晶体管 （ Thin-Film Transistor , TFT ) 包括： 栅极、 源极 和漏极。 通常来讲对 TFT的源极和漏极做如下区分： 对于 p型 TFT, 电位高 的一端称为源极， 电位低的一端则称为漏极； n型 TFT则相反， 电位低的一 端称为源极， 电位高的一端则称为漏极。 但是， 在 TFT工作时， 两端电位的 高低可能变化， 导致源漏极的称呼随之改变， 这些因素都有可能造成表述不 清或不完整。 故而， 在本发明所有实施例中， 为了对方案进行清楚的描述， 统一按照信号的输入输出走向规定源漏极的称呼：将 TFT的信号输入端称为 源极， 将 TFT的信号输出端称为漏极； 具体地， 在本发明实施例中将开关薄 膜晶体管中与数据线电性连接（即连接数据信号） 的一端称为源极、 与驱动 薄膜晶体管的栅极电性连接的一端称为漏极， 且将驱动薄膜晶体管中与电源 线电性连接（即连接电源信号） 的一端称为源极、 与有机发光器件的阳极电 性连接的一端称为漏极。
本发明实施例提供一种包含相连的多个薄膜晶体管的电路， 至少包括相 连的第一薄膜晶体管和第二薄膜晶体管， 所述第一薄膜晶体管的漏极和所述 第二薄膜晶体管的栅极电性连接， 所述第一薄膜晶体管的漏极和所述第二薄 膜晶体管的栅极同层设置。
进一步地， 同层设置的第一薄膜晶体管的漏极和第二薄膜晶体管的栅极 利用同一次构图工艺形成。
这样包含相连的薄膜晶体管的电路及其制备工艺可以应用在集成电路 中， 比如移位寄存器电路、 驱动电路等。 釆用上述方法， 可以使一个薄膜晶 体管的漏极和另一个薄膜晶体管的栅极同层设置并且电性连接， 而且它们之 间的连接不需要釆用通孔。 如此， 可以简化工艺， 并且可以增加其电性连接 性能。 但本发明不局限于只有两个晶体管的情况， 多个晶体管之间的连接方 式， 也可以釆用上述方法； 例如， 第一个薄膜晶体管的漏极和第二个薄膜晶 体管的栅极相连，第二个薄膜晶体管的漏极和第三个薄膜晶体管的栅极相连， 同样可以釆用本发明所提出的相连的两极同层设置的结构，以简化制作工艺。
上述电路可以应用于显示器中的 GOA ( Gate Driver on Array, 阵列基板 行驱动） 电路中。 具体地， GOA电路包括若干个 GOA单元， 每一 GOA单 元对应一条栅线， 即每一 GOA单元的输出端连接一条栅线； 且一 GOA单元 的输出端连接下一 GOA单元的输入端。 传统的 GOA电路中的每一 GOA单 元都包含有多个 TFT结构，且在同一个 GOA单元中至少有一个 TFT的漏极 需要和另一个 TFT的栅极相连， 这样运用本发明让这两个 TFT需要相连接 的两极同层设置， 就无需通过通孔， 从而简化在显示器生产过程中的制作工 艺
另外，上述电路还可以运用在 OLED显示器各个像素的驱动上。具体地， 在显示器中包括阵列排布的多个像素单元， 且每个像素单元中包含第一、 第 二薄膜晶体管， 其中， 所述第一薄膜晶体管为开关薄膜晶体管， 所述第二薄 膜晶体管为驱动薄膜晶体管； 所述开关薄膜晶体管的栅极连接扫描信号， 源 极连接数据信号， 漏极和所述驱动薄膜晶体管的栅极电性连接； 所述驱动薄 膜晶体管的源极连接电源信号， 漏极和有机发光器件的阳极电性连接； 所述 开关薄膜晶体管的漏极和所述驱动薄膜晶体管的栅极同层设置。
同样， 由于开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极同层设置， 就使得两者可以直接相连， 而无需通过通孔， 从而能够在实现两者电性连接 的条件下， 简化显示器生产过程中的制作工艺。
下面， 将针对在各个像素中运用上述电路的阵列基板及其制造方法、 显 示器， 进行详细阐述。
第一实施例：
本发明第一实施例提供了一种阵列基板， 参考图 1和图 2, 包括： 相互 垂直的扫描线 10和数据线 20,与数据线 20平行的电源线 30,以及所述扫描 线 10和数据线 20所限定的像素单元； 在所述像素单元内至少形成有开关薄 膜晶体管 40、驱动薄膜晶体管 50; 其中，所述开关薄膜晶体管 40的栅极 40a 和所述扫描线 10电性连接， 源极 40b和所述数据线 20电性连接， 漏极 40c 和所述驱动薄膜晶体管 50的栅极 50a电性连接； 所述驱动薄膜晶体管 50的 源极 50b和所述电源线 30电性连接，漏极 50c和有机发光器件 60的阳极 601 电性连接； 并且， 所述开关薄膜晶体管的漏极 40c和所述驱动薄膜晶体管的 栅极 50a同层设置。
当然， 如图 2所示， 阵列基板还可以包括： 起到绝缘作用的第一绝缘层 102、 第二绝缘层 103、 以及覆盖两个薄膜晶体管 40、 50的第三绝缘层 104。 当然， 由于 OLED显示器包括： 阵列基板以及有机发光器件， 所以要制作 OLED显示器的话， 还需要在上述阵列基板上形成有机发光器件 60的阳极 601、 有机发光器件的有机功能层 602、 有机发光器件的阴极 603 , 还可以进 一步在上述阵列基板上形成像素界定层 106。
需要说明的是， 在本发明所有实施例中， 上述扫描线、数据线、 电源线、 以及开关薄膜晶体管的栅极、 源极、 漏极、 驱动薄膜晶体管的栅极、 源极、 漏极分布于两层导电薄膜； 按照制作工艺上沉积导电薄膜的顺序， 将先沉积 的导电薄膜称为底层导电薄膜， 将后沉积的导电薄膜称为顶层导电薄膜。 并 且， 开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极可以均是由顶层导电薄 膜经过构图工艺所形成图案的一部分， 也可以均是底层导电薄膜经过构图工 艺所形成图案的一部分。 其中， 对于图 1、 图 2所示的阵列基板而言， 开关 薄膜晶体管的漏极和驱动薄膜晶体管的栅极可以均是由顶层导电薄膜经过构 图工艺所形成图案的一部分， 对于图 4、 图 5所示的阵列基板而言， 开关薄 膜晶体管的漏极和驱动薄膜晶体管的栅极可以均是由底层导电薄膜经过构图 工艺所形成图案的一部分。 且在图 1、 图 2、 图 4、 图 5中主要画出与阐述本 发明方案相关的部分结构， 对于其他结构只画出部分或直接省略； 但将制造 OLED显示器所必须的有机发光器件的阳极、阴极和有机功能层都标识图中， 并进一步在图中标识出了像素界定层。
由于开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极同层设置， 这样两 者就可以直接相连， 而无需通过通孔， 从而能够在实现两者电性连接的条件 下， 简化显示器生产过程中的制作工艺， 进而能够在一定程度上提高产率。
在本实施例中， 开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极均是由 顶层导电薄膜经过构图工艺所形成图案的一部分； 并且，
优选地，所述开关薄膜晶体管 40的栅极 40a为底层导电薄膜经过构图工 艺所形成图案的一部分； 且所述开关薄膜晶体管的源极 40b、 漏极 40c, 以及 所述驱动薄膜晶体管的栅极 50a和源极 50b、 漏极 50c为顶层导电薄膜经过 构图工艺所形成图案的一部分。
进一步优选地， 所述开关薄膜晶体管的栅极 40a和所述开关薄膜晶体管 的有源层 401之间的绝缘层 (即第一绝缘层 102 ) 的厚度比所述驱动薄膜晶 体管的栅极 50a和所述驱动薄膜晶体管的有源层 501之间的绝缘层 (即第二 绝缘层 103 ) 的厚度大。
由于在薄膜晶体管中， 栅绝缘层的材料和特性（例如： 厚度）可以用于 调节薄膜晶体管的特性。 在本实施例中， 第一绝缘层 102作为开关薄膜晶体 管 40的栅绝缘层， 第二绝缘层 103作为驱动薄膜晶体管 50的栅绝缘层。 而 由于开关晶体管需要较好的电荷保持性能， 可以增加第一绝缘层 102的厚度 来降低栅极的漏电流， 驱动晶体管需要较大的电流以提高有机发光器件的亮 度， 从而可以减薄第二绝缘层 103的厚度来增加开态电流。
另外，对于开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有 源层 501的材料可以是通常使用的非氧化物半导体材料， 例如，硅、非晶硅、 或者多晶硅； 在本发明实施例中， 优选地， 开关薄膜晶体管的有源层 401和 / 或所述驱动薄膜晶体管的有源层 501的材料为氧化物半导体。 更进一步优选 地，开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有源层 501的 材料为含有铟、 镓、 辞中至少一种金属的氧化物半导体。
使用氧化物半导体作为有源层的薄膜晶体管的特性优于使用非氧化物半 导体作为有源层的薄膜晶体管的特性。 例如， 氧化物半导体相对于非晶硅而 言， 会增强薄膜晶体管的如迁移率、 开态电流、 开关特性等特性。 氧化物半 导体相对于多晶硅而言， 均匀性较好， 不需要增加补偿电路， 在掩膜数量和 制作难度上均有优势， 因此， 在制作大尺寸的显示器方面也有优势。 而且氧 化物半导体薄膜釆用溅射等方法就可以制备， 不需增加额外的设备， 具有成 本优势。
本发明实施例还提供了一种显示器， 包括： 上述任一种阵列基板以及有 机发光器件； 其中， 所述有机发光器件包括： 阳极、 阴极和有机功能层。 实 际上， 由于该显示器包含有机发光器件（OLED ) , 故这样的显示器可以一 般称为 OLED显示器。
具体地， 若上述 OLED显示器中的有机发光器件只能发白光， 则包含这 种有机发光器件的 OLED显示器可以还包括一个设置有红、 蓝、 绿三种颜色 像素结构的彩膜基板。 若上述 OLED显示器中的有机发光器件可以发出红、 蓝、 绿中的一种颜色的光， 则包含这种有机发光器件的 OLED显示器可以只 包含上述阵列基板和发光显示器件， 当然还可以包含一透明基板以保护阵列 基板上的层结构以及发光显示器件的结构。
本发明实施例还提供了上述图 1、 图 2中阵列基板的制作方法， 包括： 步骤 S101、 参考图 3A, 在衬底基板 101上制作底层导电薄膜， 并通过 构图工艺至少形成开关薄膜晶体管 40的栅极和扫描线（在图中未标示） 。
其中， 底层导电薄膜的材料可以是钼、 铝、 铜、 铬等任一金属， 也可以 是含有这些金属的合金， 还可以是 ITO ( Indium Tin Oxides, 纳米铟锡金属氧 化物）等的导电化合物。 这些材料可以使用蒸镀的方法制备， 也可以使用溅 射的方法制备， 还可以通过精细电镀的方法制备形成底层导电薄膜。
步骤 S102、 参考图 3B, 制作第一绝缘层 102;
其中， 第一绝缘层 102可以是氧化硅、 氮化硅、 氮氧化硅等薄膜， 也可 以是这些薄膜的叠层结构。这些绝缘薄膜可以釆用 PECVD( Plasma Enhanced Chemical Vapor Deposition, 等离子体增强化学气相沉积）方法制备， 也可以 釆用溅射的方法制备。
步骤 S103、 参考图 3C, 制作半导体薄膜， 并通过构图工艺形成开关薄 膜晶体管的有源层 401、 驱动薄膜晶体管的有源层 501;
其中，开关薄膜晶体管的有源层 40位于开关薄膜晶体管的栅极 40a的上 方区域， 驱动薄膜晶体管的有源层 501位于像素单元中开关薄膜晶体管所在 区域之外的其他区域。
另外，对于开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有 源层 501的材料可以是通常使用的非氧化物半导体材料， 例如，硅、非晶硅、 或者多晶硅； 在本发明实施例中， 优选地， 开关薄膜晶体管的有源层 401和 / 或所述驱动薄膜晶体管的有源层 501的材料为氧化物半导体。 更进一步优选 地，开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有源层 501的 材料为含有铟、 镓、 辞中至少一种金属的氧化物半导体。
并且利用氧化物半导体材料制作半导体薄膜可以釆用溅射方法制备， 也 可以釆用旋涂的方法来制备。
步骤 S104、 参考图 3D, 制作第二绝缘层 103 , 并通过通孔连接工艺至 少在覆盖开关薄膜晶体管 40有源层上的第二绝缘层 103上形成两个通孔,在 覆盖驱动薄膜晶体管 50有源层上的第二绝缘层 103上形成两个通孔；
其中， 图中的 4个通孔使得开关薄膜晶体管的有源层 401、 驱动薄膜晶 体管的有源层 501的部分区域棵露在外。
另外， 第二绝缘层可以是氧化硅、 氮化硅、 氮氧化硅等薄膜， 也可以是 这些薄膜的叠层结构。 上述绝缘薄膜可以釆用 PECVD方法制备， 也可以釆 用溅射的方法制备。 通孔可以通过离子反应刻蚀来形成。
步骤 S105、 参考图 3E, 制作顶层导电薄膜， 覆盖上述第二绝缘层 103 上的通孔， 并通过构图工艺至少形成开关薄膜晶体管的源极 40b、 漏极 40c, 驱动薄膜晶体管的栅极 50a和源极 50b、 漏极 50c以及数据线、 电源线（图 中未标示） ； 其中， 开关薄膜晶体管的源极 40b和数据线直接相连， 驱动薄 膜晶体管的源极 50b和电源线直接相连， 且开关薄膜晶体管的漏极 40c和驱 动薄膜晶体管的栅极 50a直接相连。
并且， 开关薄膜晶体管的源极 40b、 漏极 40c分别通过步骤 S104中的通 孔与开关薄膜晶体管的有源层 401相连； 驱动薄膜晶体管的源极 50b、 漏极 50c分别通过步骤 S104中的通孔与驱动薄膜晶体管的有源层 501相连。
上述顶层导电薄膜的材料可以是钼、 铝、 铜、 铬等中任一种金属， 也可 以是含有这些金属的合金， 还可以是 ITO等的导电化合物， 还可以是上述各 导电材料构成的叠层结构。 这些材料可以使用蒸镀的方法制备， 也可以使用 溅射的方法制备， 还可以通过精细电镀的方法制备形成顶层导电薄膜。
截止至步骤 S105 ,共通过 4次掩模板构图工艺就可以同时形成两个薄膜 晶体管， 并且这两个薄膜晶体管可以具有不同的特性。 第一薄膜晶体管的漏 极和第二薄膜晶体管的栅极同层设置并且电性连接， 而且它们之间的连接不 需要釆用通孔。
下面， 还需要制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发 光器件的阳极电性连接的通孔； 具体有以下两种方式， 其中利用第一种方式 所制造的阵列基板上形成有平坦化层， 利用第二种方式所制造的阵列基板上 不形成平坦化层。
第一种方式： 包括： 步骤 S106-S107;
步骤 S106、 参考图 3F, 制作第三绝缘层 104。
其中， 第三绝缘层 104可以是氧化硅， 也可以是氮化硅， 也可以是氧化 硅与氮化硅的多层结构。 该绝缘薄膜可以釆用 PECVD方法制备， 也可以釆 用溅射的方法制备。
步骤 S107、 参考图 3G, 制作平坦化层 105, 并通过通孔连接工艺至少 在覆盖驱动薄膜晶体管的漏极 50c的第三绝缘层 104和平坦化层 105上形成 通孔。
其中， 平坦化层的材料可以是有机材料， 如聚酰亚胺等， 该平坦化层可 以釆用旋涂的方法制备。
此时已经完成阵列基板的制造， 若制造 OLED显示器， 则继续进行以下 步骤：
参考图 3H, 制作有机发光器件的阳极 601 , 覆盖上述第三绝缘层 104和 平坦化层 105上所形成的通孔。这样就使得有机发光器件 60的阳极 601通过 该通孔和驱动薄膜晶体管的漏极 50c相连。当然，最终形成图 2所示的 OLED 显示器的部分结构， 还需要依次形成像素界定层 106、有机发光器件 60的有 机功能层 602、 以及有机发光器件 60的阴极 603。
第二种方式：
制作第三绝缘层， 并利用一次构图工艺在该第三绝缘层上形成通孔。 此时， 完成阵列基板的制造， 若制造 OLED显示器， 则继续制作有机发 光器件的阳极、 像素界定层、 有机发光器件的有机功能层、 以及有机发光器 件的阴极。
此种方式虽然没有对应图示， 但本领域技术人员可以通过现有技术不经 过创造性劳动， 就可以得到该第二种方式所描述的阵列基板的制造方法。
上述制作方式使得开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极同层 设置且直接相连，而无需通过通孔，从而能够在实现两者电性连接的条件下， 简化显示器生产过程中的制作工艺， 进而能够在一定程度上提高产率。
第二实施例： 本发明实施例提供了一种阵列基板， 参考图 4和图 5 , 包括： 相互垂直 的扫描线 10和数据线 20, 与数据线 20平行的电源线 30, 以及所述扫描线 10和数据线 20所限定的像素单元； 在所述像素单元内至少形成有开关薄膜 晶体管 40、 驱动薄膜晶体管 50; 其中， 所述开关薄膜晶体管 40的栅极 40a 和所述扫描线 10电性连接、 源极 40b和所述数据线 20电性连接， 漏极 40c 和所述驱动薄膜晶体管 50的栅极 50a电性连接； 所述驱动薄膜晶体管 50的 源极 50b和所述电源线 30电性连接、漏极 50c和有机发光器件 60的阳极 601 电性连接； 并且， 所述开关薄膜晶体管的漏极 40c和所述驱动薄膜晶体管的 栅极 50a同层设置。
当然， 如图 4所示， 阵列基板还可以包括： 起到绝缘作用的第一绝缘层
102、 第二绝缘层 103、 以及覆盖两个薄膜晶体管 40、 50的第三绝缘层 104。 当然， 由于 OLED显示器可以包括： 阵列基板以及有机发光器件， 所以要制 作 OLED显示器的话， 还需要在上述阵列基板上形成有机发光器件 60的阳 极 601、 有机发光器件的有机功能层 602、 有机发光器件的阴极 603 , 还可以 进一步在上述阵列基板上形成像素界定层 106。
由于开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极同层设置， 这样两 者就可以直接相连， 而无需通过通孔， 从而能够在实现两者电性连接的条件 下， 简化显示器生产过程中的制作工艺， 进而能够在一定程度上提高产率。
在本实施例中， 开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极均是由 底层导电薄膜经过构图工艺所形成图案的一部分； 并且，
优选地， 所述开关薄膜晶体管的源极 40b、 漏极 40c, 以及所述驱动薄膜 晶体管的栅极 50a和源极 50b、 漏极 50c为底层导电薄膜经过构图工艺所形 成图案的一部分； 所述开关薄膜晶体管的栅极 40a为顶层导电薄膜经过构图 工艺所形成图案的一部分。
进一步优选地， 所述开关薄膜晶体管的栅极 40a和所述开关薄膜晶体管 的有源层 401之间的绝缘层 (即第二绝缘层 103 ) 的厚度比所述驱动薄膜晶 体管的栅极 50a和所述驱动薄膜晶体管的有源层 501之间的绝缘层 (即第一 绝缘层 102 ) 的厚度大。
由于在薄膜晶体管中， 栅绝缘层的材料和特性（例如： 厚度）可以用于 调节薄膜晶体管的特性。 在本实施例中， 第二绝缘层 103作为开关薄膜晶体 管 40的栅绝缘层， 第一绝缘层 102作为驱动薄膜晶体管 50的栅绝缘层。 而 由于开关晶体管需要较好的电荷保持性能， 可以增加第二绝缘层 103的厚度 来降低栅极的漏电流， 驱动晶体管需要较大的电流以提高有机发光器件的亮 度， 从而可以减薄第一绝缘层 102的厚度来增加开态电流。
另外，对于开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有 源层 501的材料可以是通常使用的非氧化物半导体材料， 例如，硅、非晶硅、 或者多晶硅； 在本发明实施例中， 优选地， 开关薄膜晶体管的有源层 401和 / 或所述驱动薄膜晶体管的有源层 501的材料为氧化物半导体。 更进一步优选 地，开关薄膜晶体管的有源层 401和 /或所述驱动薄膜晶体管的有源层 501的 材料为含有铟、 镓、 辞中至少一种金属的氧化物半导体。
使用氧化物半导体作为有源层的薄膜晶体管的特性优于使用非氧化物半 导体作为有源层的薄膜晶体管的特性。 例如， 氧化物半导体相对于非晶硅而 言， 会增强薄膜晶体管的如迁移率、 开态电流、 开关特性等特性。 氧化物半 导体相对于多晶硅而言， 能够其均匀性较好， 不需要增加补偿电路， 在掩膜 数量和制作难度上均有优势， 因此， 在制作大尺寸的显示器方面也有优势。 而且氧化物半导体薄膜釆用溅射等方法就可以制备， 不需增加额外的设备， 具有成本优势。
本发明实施例还提供了一种 OLED显示器， 包括本发明实施例中提供的 上述任一种阵列基板以及有机发光器件； 其中， 所述有机发光器件包括： 阳 极、 阴极和有机功能层。
具体地， 若上述 OLED显示器中的有机发光器件只能发白光， 则包含这 种有机发光器件的 OLED显示器可以还包括一个设置有红、 蓝、 绿三种颜色 像素结构的彩膜基板。 若上述 OLED显示器中的有机发光器件可以发出红、 蓝、 绿中的一种颜色的光， 则包含这种有机发光器件的 OLED显示器可以只 包含上述阵列基板和发光显示器件， 当然还可以包含一透明基板以保护阵列 基板上的层结构以及发光显示器件的结构。
本发明实施例还提供了上述图 4和图 5中阵列基板的制作方法， 包括： 步骤 S201、在衬底基板 101上制作底层导电薄膜， 并通过构图工艺至少 形成开关薄膜晶体管的源极 40b、 漏极 40c, 驱动薄膜晶体管 50的栅极 50a 和源极 50b、 漏极 50c以及数据线 20、 电源线 30; 其中， 开关薄膜晶体管 40 的源极 40b和数据线 20直接相连， 驱动薄膜晶体管的源极 50b和电源线 30 直接相连， 且开关薄膜晶体管的漏极 40c和驱动薄膜晶体管的栅极 50a直接 相连。
步骤 S202、 制作第一绝缘层 102, 并通过通孔连接工艺至少在覆盖开关 薄膜晶体管 40源极 40b、 漏极 40c, 驱动薄膜晶体管源极 50b、 漏极 50c的 第一绝缘层 102上分别形成通孔。
步骤 S203、 制作半导体薄膜， 覆盖上述第一绝缘层 102上的通孔， 并通 过构图工艺形成开关薄膜晶体管的有源层 401、 驱动薄膜晶体管的有源层 501。
步骤 S204、 制作第二绝缘层 103。
步骤 S205、制作顶层导电薄膜， 并通过构图工艺至少形成开关薄膜晶体 管的栅极 40a和扫描线 10。
截止至步骤 S205 ,共通过 4次掩模板构图工艺就可以同时形成两个薄膜 晶体管， 并且这两个薄膜晶体管可以具有不同的特性。 第一薄膜晶体管的漏 极和第二薄膜晶体管的栅极同层设置并且电性连接， 而且它们之间的连接不 需要釆用通孔。
下面， 还需要制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发 光器件的阳极电性连接的通孔； 具体有以下两种方式， 其中利用第一种方式 所制造的阵列基板上形成有平坦化层， 利用第二种方式所制造的阵列基板上 不形成平坦化层。
第一种方式： 包括： 步骤 S206-S207。
步骤 S206、 制作第三绝缘层 104。
步骤 S207、 制作平坦化层 105 , 并通过通孔连接工艺至少在覆盖驱动薄 膜晶体管的漏极 50c的第一绝缘层 102、 第二绝缘层 103、 第三绝缘层 104 和平坦化层 105上形成通孔。
此时已经完成 OLED阵列基板的制造， 若制造 OLED显示器， 则继续进 行以下步骤：
制作有机发光器件 60的阳极 601 , 覆盖上述第一绝缘层 102、 第二绝缘 层 103、 第三绝缘层 104和平坦化层 105上所形成的通孔。
当然， 最终形成图 4和图 5所示的 OLED显示器的部分结构， 还需要依 次形成像素界定层 106、 有机发光器件 60的有机功能层 602、 以及有机发光 器件 60的阴极 603。
第二种方式：
制作第三绝缘层， 并利用一次构图工艺在该第三绝缘层上形成通孔。 此时， 完成阵列基板的制造， 若制造显示器， 则继续制作有机发光器件 的阳极、 像素界定层、 有机发光器件的有机功能层、 以及有机发光器件的阴 极。
此种方式虽然没有对应图示， 但本领域技术人员可以通过现有技术不经 过创造性劳动， 就可以得到该第二种方式所描述的阵列基板的制造方法。
需要说明的是， 本发明实施例提供的阵列基板的制作方法中， 各层所使 用的材料以及制备方法都可以参照第一实施例中的制作方法， 在本实施例中 不再赞述。 另外， 虽然在本发明实施例中的并未针对该制作方法给出每一步 骤的附图， 但本领域技术人员根据上述步骤以及图 4和图 5可以制作出图 4 和图 5所示的结构。
本发明实施例提供的制作方式使得开关薄膜晶体管的漏极和驱动薄膜晶 体管的栅极同层设置且直接相连， 而无需通过通孔， 从而能够在实现两者电 性连接的条件下， 简化 OLED显示器生产过程中的制作工艺， 进而能够在一 定程度上提高产率。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保 护范围应以所述权利要求的保护范围为准。
附图标记：
101-衬底基板， 102-第一绝缘层， 103-第二绝缘层， 104-第三绝缘层， 105- 平坦化层， 106-像素界定层；
10-扫描线， 20-数据线， 30-电源线， 40-开关薄膜晶体管， 40a-开关薄膜 晶体管的栅极， 40b-开关薄膜晶体管的源极， 40c-开关薄膜晶体管的漏极， 401-开关薄膜晶体管的有源层， 50-驱动薄膜晶体管， 50a-驱动薄膜晶体管的 栅极， 50b-驱动薄膜晶体管的源极， 50c-驱动薄膜晶体管的漏极， 501-驱动薄 膜晶体管的有源层； -有机发光器件（OLED ) , 601-有机发光器件的阳极， 602-有机功能3-有机发光器件的阴极。

Claims

权利要求书
1、一种包含相连的多个薄膜晶体管的电路， 包括： 至少包括相连的第一 薄膜晶体管和第二薄膜晶体管， 所述第一薄膜晶体管的漏极和所述第二薄膜 晶体管的栅极电性连接， 所述第一薄膜晶体管的漏极和所述第二薄膜晶体管 的栅极同层设置。
2、根据权利要求 1所述的电路， 其中， 所述第一薄膜晶体管为开关薄膜 晶体管、 所述第二薄膜晶体管为驱动薄膜晶体管； 其中， 所述开关薄膜晶体 管的栅极连接扫描信号， 源极连接数据信号， 漏极和所述驱动薄膜晶体管的 栅极电性连接； 所述驱动薄膜晶体管的源极连接电源信号， 漏极和有机发光 器件的阳极电性连接； 所述开关薄膜晶体管的漏极和所述驱动薄膜晶体管的 栅极同层设置， 且利用同一次构图工艺形成。
3、一种阵列基板， 包括： 相互垂直的扫描线和数据线， 与数据线平行的 电源线， 以及所述扫描线和数据线所限定的像素单元； 在所述像素单元内至 少形成有第一薄膜晶体管、 第二薄膜晶体管； 其中， 所述第一薄膜晶体管的 栅极和所述扫描线电性连接， 源极和所述数据线电性连接， 漏极和所述第二 薄膜晶体管的栅极电性连接； 所述第二薄膜晶体管的源极和所述电源线电性 连接， 漏极和有机发光器件的阳极电性连接； 其特征在于， 所述第一薄膜晶 体管的漏极和所述第二薄膜晶体管的栅极同层设置。
4、 根据权利要求 3所述的阵列基板， 其中，
所述第一薄膜晶体管为开关薄膜晶体管、 所述第二薄膜晶体管为驱动薄 膜晶体管；
所述开关薄膜晶体管的栅极为底层导电薄膜经过构图工艺所形成图案的 一部分；
所述开关薄膜晶体管的源、漏极，以及所述驱动薄膜晶体管的栅极和源、 漏极为顶层导电薄膜经过构图工艺所形成图案的一部分。
5、 根据权利要求 3所述的阵列基板， 其中，
所述第一薄膜晶体管为开关薄膜晶体管、 所述第二薄膜晶体管为驱动薄 膜晶体管；
所述开关薄膜晶体管的源、漏极，以及所述驱动薄膜晶体管的栅极和源、 漏极为底层导电薄膜经过构图工艺所形成图案的一部分；
所述开关薄膜晶体管的栅极为顶层导电薄膜经过构图工艺所形成图案的 一部分。
6、根据权利要求 4或 5所述的阵列基板， 其中， 所述开关薄膜晶体管的 栅极和所述开关薄膜晶体管的有源层之间的绝缘层的厚度比所述驱动薄膜晶 体管的栅极和所述驱动薄膜晶体管的有源层之间的绝缘层的厚度大。
7、 根据权利要求 3-5任一项所述的阵列基板， 其中， 所述开关薄膜晶体 管的有源层和 /或所述驱动薄膜晶体管的有源层的材料为氧化物半导体。
8、根据权利要求 7所述的阵列基板， 其中， 所述开关薄膜晶体管的有源 层和 /或所述驱动薄膜晶体管的有源层的材料为含有铟、镓、辞中至少一种金 属的氧化物半导体。
9、 一种显示器， 包括： 权利要求 3-8任一项所述的阵列基板以及有机发 光器件； 其中， 所述有机发光器件包括： 阳极、 阴极和有机功能层。
10、 一种权利要求 4所述的阵列基板的制作方法， 包括：
在衬底基板上制作底层导电薄膜， 并通过构图工艺至少形成开关薄膜晶 体管的栅极和扫描线；
制作第一绝缘层；
制作半导体薄膜， 并通过构图工艺形成开关薄膜晶体管的有源层、 驱动 薄膜晶体管的有源层；
制作第二绝缘层， 并通过通孔连接工艺至少在覆盖开关薄膜晶体管有源 层上的第二绝缘层上形成两个通孔， 在覆盖驱动薄膜晶体管有源层上的第二 绝缘层上形成两个通孔；
制作顶层导电薄膜， 覆盖上述第二绝缘层上的通孔， 并通过构图工艺至 少形成开关薄膜晶体管的源、 漏极， 驱动薄膜晶体管的栅极和源、 漏极以及 数据线、 电源线； 其中， 开关薄膜晶体管的源极和数据线直接相连， 驱动薄 膜晶体管的源极和电源线直接相连， 且开关薄膜晶体管的漏极和驱动薄膜晶 体管的栅极直接相连；
制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发光器件的阳极 电性连接的通孔。
11、 一种权利要求 5所述的阵列基板的制作方法， 包括： 在衬底基板上制作底层导电薄膜， 并通过构图工艺至少形成开关薄膜晶 体管的源、 漏极， 驱动薄膜晶体管的栅极和源、 漏极以及数据线、 电源线； 其中， 开关薄膜晶体管的源极和数据线直接相连， 驱动薄膜晶体管的源极和 电源线直接相连， 且开关薄膜晶体管的漏极和驱动薄膜晶体管的栅极直接相 连；
制作第一绝缘层，并通过通孔连接工艺至少在覆盖开关薄膜晶体管源极、 漏极， 驱动薄膜晶体管源极、 漏极的第一绝缘层上分别形成通孔；
制作半导体薄膜， 覆盖上述第一绝缘层上的通孔， 并通过构图工艺形成 开关薄膜晶体管的有源层、 驱动薄膜晶体管的有源层；
制作第二绝缘层；
制作顶层导电薄膜， 并通过构图工艺至少形成开关薄膜晶体管的栅极和 扫描线；
制作第三绝缘层， 并在该第三绝缘层上形成用于与有机发光器件的阳极 电性连接的通孔。
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