CN1528016A - 电子组件制造方法 - Google Patents

电子组件制造方法 Download PDF

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CN1528016A
CN1528016A CNA018155650A CN01815565A CN1528016A CN 1528016 A CN1528016 A CN 1528016A CN A018155650 A CNA018155650 A CN A018155650A CN 01815565 A CN01815565 A CN 01815565A CN 1528016 A CN1528016 A CN 1528016A
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CN1302532C (zh
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M��K��������
M·K·贾伦杰
游元金
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Rohm and Haas Electronic Materials LLC
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Abstract

本发明公开制造电子组件，特别是集成电路的方法。这些方法包括使用通过用可移除的孔原物(porogen)材料制成的低介电常数材料。

Description

电子组件制造方法
发明背景
本发明一般性涉及电子组件制造领域。特别地，本发明系有关含有低介电常数材料的集成电路的制造。
随着电子组件变得愈小，电子工业对于增加电子组件中的电路密度具有持续性的需求，例如，对于集成电路、电路板、多芯片模块、芯片检测装置等，且不会降低电性能，如串讯(crosstalk)或电容偶合；且也要增加这些组件中的讯号传递速度。藉由减低组件所用层间，或金属间的绝缘材料所具介电常数完成这些目标。一种减低这些层间，或金属间绝缘材料所具介电常数的方法为在绝缘膜片内掺入非常小，均匀分散的孔洞或空隙。
于电子组件制造技艺中，特别是对集成电路，已知有多种有机和无机介电材料。适当的无机介电材料包括二氧化硅和有机聚氧化硅。适当的有机介电性材料包括热固性材料例如聚酰亚胺、聚芳烯醚、聚芳烯、聚三聚氰酸酯、聚苯并唑类、聚并环丁烯类等。
一般而言，多孔型介电材料系通过先在B-阶段介电材料中掺入可移除性孔原物(porogen)，将含有孔原物的B-阶段介电材料配置到基板上，将B-阶段介电材料固化然后移除掉该聚合物而形成多孔型介电材料。例如，美国专利第5,895,263号(Carter et al.)揭示一种形成含有多孔型有机聚氧化硅介电性材料的集成电路的方法。美国专利第6,093,636号(Carter et al.)揭示一种形成含有多孔型热固性介电材料的集成电路的方法。于这两专利中所述方法都需要在任何后续加工步骤之前形成多孔型介电材料之步骤。
多孔型介电材料相对于不含孔洞的相同介电材料具有减低的，且可能实质减低的介电常数。不过，于某些情况中，这些孔洞的存在会有问题。例如，经蚀刻到这些多孔型介电材料内的锐孔会因为介电材料中的孔洞或空隙而使其侧壁变得粗糙。此种侧壁粗糙性会增加沉积后续金属层例如障壁层或种层(Seed layer)的困难处。该障壁层或种层典型地系经化学或物理气相沈积成视线型式。因此，锐孔侧壁中的粗糙性倾向于会在障壁层及/或种层内造成不连续性。这些不连续性可能在电子组件的制造中对后续加工步骤及其性能有不利的影响。
因此需要有一种制造包括具有实质连续锐孔的障壁层及/或种层之多孔性介电材料的电子组件的方法。
发明概述
令人惊讶地发现本发明方法可在经蚀刻之多孔型介电材料中的锐孔中提供具有实质连续性(优选地为连续性金属层及优选地为障壁层及/或种层)的电子组件。
一方面，本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电基质组合物，该组合物包括一或多种介电性基质材料及可移除的孔原物；b)未实质移除该孔原物的条件下固化该B-阶段介电基质组合物，形成介电性基质材料；c)将该介电性基质材料图样化(patterning)；d)在该介电性材料的表面上沉积一金属层；及e)以至少可部份移除掉该孔原物形成一多孔型介电材料层而不会实质地降解该介电材料的条件处理该介电性基质材料。
另一方面，本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除的孔原物；b)未实质移除该孔原物的条件下固化该B-阶段介电性基质组合物，形成介电性基质材料；c)将该介电性基质材料图样化；d)在该介电性材料的表面上沉积至少一障壁层或种层；e)沈积一锐孔填充金属层；f)将该锐孔填充金属层平面化；及g)以至少部份移除掉该孔原物形成多孔型介电材料层而不会实质地降解该介电性材料的条件处理该介电基质材料。
另一方面，本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除的孔原物；b)未实质移除该孔原物的条件下，固化该B-阶段介电性基质组合物，形成介电性基质材料；c)将该介电性基质材料图样化；d)在该介电性材料的表面上沉积一金属层；e)以至少部份移除该孔原物形成一多孔型介电材料层而不会实质地降解该介电材料的条件处理该介电基质材料；及(f)对该多孔型介电层施加后续加工步骤，其中所述的多孔型介电层不含加盖层。
又另一方面，本发明提出一种包括不含加盖层的多孔型介电层的电子组件。
附图说明
图1表示出现有技术电子组件，其包括以常规方式制得经配置在基板上具有孔洞或空隙的介电性材料，该图未按比例示出。
图2表示出一种现有技术电子组件，其包括多孔型介电性材料，该图未按比例示出。
图3表示出一种现有技术电子组件，其具有施涂于多孔型介电材料的不连续障壁层，该图未按比例示出。
图4表示出一种电子组件其包括经配置在含有金属钉的基板上面含有可移除孔原物的介电材料，该图未按比例示出。
图5表示出一种电子组件，其包括经配置在一含有可移除性聚合物的介电材料上的光阻层，该图未按比例示出。
图6表示出一种电子组件，其在介电材料内具有直侧壁的锐孔，该图未按比例示出。
图7表示出一种电子组件，其在含有可移除性孔原物的介电材料上具有经配置的实质连续性障壁层。
图8表示出在平面处理后的电子组件，其包括多孔型介电材料、实质连续性障壁层及经金属处理的锐孔，该图未按比例示出。
发明的详细说明
如在本说明书整体所用者，除非文中另外有清楚指示，下列缩写具有下列意义：℃＝摄氏度；UV＝紫外；且nm＝奈米。“锐孔”指的是任何凹陷条件，例如，通孔(vias)和沟漕(trenches)。
“烷基”一词包括直链型、支链型和环状烷基。“孔原物”一词指的是孔洞形成性材料或部份体，例如，但不限于可与介电性材料共聚合形成嵌段共聚物的化合物，或分散于介电性材料中可在产生孔洞、空隙或自由容积后可移除的聚合材料或粒子。因此，“可移除性孔原物”、“可移除性聚合物”及“可移除性粒子”诸词在本说明书内可互换使用。“孔洞”、“空隙”及“自由容积”诸词在本说明书内可互换使用。“交联剂”及“交联性试剂”在本说明书内可互换使用。“聚合物”指的是聚合物和低聚物，且也包括均聚物和共聚物。“低聚物”和“低聚物型”两词指的是二聚物、三聚物、四聚物等。“单体”指的是能够聚合的任何乙烯型或乙炔型未饱和化合物，或能够通过缩合聚合的其它化合物。这些单体可含有一或多个双键或参键或能够缩合以形成聚合物的基。
“B-阶段”一词指的是未经固化的介电性基质材料。“未经固化”意指可经聚合或固化形成较高分子量材料，例如涂料或膜，之任何介电性材料。这些B-阶段材料可为单体型、低聚物型或其混合物。B-阶段材料复包括聚合物型材料与单体，低聚物或单体/低聚物混合物的混合物。
除非另外指明，否则所有量都是重量百分比且所有比例都是重量比。所有数值范围都是内含且可组合者。
在常用的制备电子组件例如具有多孔型介电材料层的集成电路的方法中，首先是在一基板上配置含有可移除性聚合物之B-阶段介电材料。然后在设有实质地移除或降解该聚合物之下固化该B-阶段介电性材料而在该基板上形成含有可移除性聚合物的介电材料层、涂层或膜。接着以实质地移除该聚合物并在基板上形成多孔型介电材料的条件处理该介电性材料。这些介电材料与不含孔洞的这些材料相比，典型地具有较为低的介电常数。在形成该孔洞型介电材料之后，才对该基板施以后续加工步骤，例如，平版刻法、蚀刻、障壁层/种层沉积、金属化及平面化处理。这些传统方法会导致具有实质侧壁粗糙性的锐孔，其可能对后续加工步骤和组件性能有不利的影响。
图1表示一种包括在具有金属钉12的基板10上面配置经传统方式制成具有孔洞或空隙16之介电材料15的电子组件。于一典型方法中，视情况会在该多孔型介电层的表面上施涂抗反射涂层。然后在该抗反射涂层或多孔型介电层的表面上施涂一光阻层，并将该光阻层曝光以使该介电性多孔层图样化。于图样化之后，将该多孔型介电层蚀刻以设置锐孔，再移除掉光阻层。图2表示出在光阻层蚀刻和移除后的经传统方式制备的多孔型介电性材料15。在该多孔型介电材料15中的锐孔20具有不平或粗糙的侧壁30(为清晰起见予以放大)。这些不平坦侧壁系为该介电性材料15中含有孔洞16所致。于锐孔20的形成过程中，会许多孔洞会被蚀刻穿破，导致这些锐孔侧壁含有某些孔洞的一部份25(为清晰起见予以放大)。第3图表示出这些传统方法的后续步骤，其中对该介电材料15施涂一障壁层35。该粗糙侧壁30导致障壁层中的不连续开口或裂痕27。这些不连续性在后续金属化中会有问题，因为在金属层中空隙及障壁层中的不连续性可能使铜渗移到介电层内。
这些问题可由本发明予以减低或避免。本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；b)未实质移除该孔原物的条件下固化该B-阶段介电性基质组合物，而形成介电性基质材料；c)将该介电性基质材料图样化；d)在该介电性材料的表面上沉积一金属层；及e)以至少部份移除该孔原物形成多孔型介电材料层而没有实质地降解该介电性材料的条件处理该介电基质材料。
任何能够形成多孔型介电材料的B-阶段介电材料都可用于本发明中。适当的B-阶段介电材料包括，但不限于无机材料例如有机聚氧化硅、硅、硼或铝的碳化物、氧化物、氮化物及氧氟化物；及有机基质材料例如苯并环丁烯、聚(芳基酯类)、聚(醚酮)类、聚碳酸酯、聚(芳烯醚)、聚芳烃例如聚、聚喏、聚(全氟化烃)例如聚(四氟乙烯)、聚酰亚胺、聚苯并噁唑和聚环烯烃例如聚原冰片烯。这些B-阶段介电性材料通常为市面上可取得者或可用文献中已知的方法制备者。
可用于本发明中的特别适当B-阶段有机聚氧化硅(或有机硅氧烷)介电性材料为包括硅、碳、氧和氢原子且具有下式者之任何化合物：
((RR1SiO)n(R2SiO1.5)b(R3SiO1.5)c(SiO2)d)n其中R、R1、R2和R3彼此独立地为选自：氢、(C1-C6)烷基、芳基和经取代芳基；a、b、c和d彼此独立地为0至1的数；n为约3至约10,000的整数；但其限制条件为a+b+c+d＝1；且R、R1和R2中至少有一者不为氢。“经取代芳基”指的是其氢原子中有一或多个被另一取代基所置换，例如氰基、羟基、氢硫基、卤素、(C1-C6)烷基、(C1-C6)烷氧基等。于上述的式子中，a、b和c表每一种成分的莫耳比例。这些莫耳比例可在0与约1之间改变。以a为0至约0.8为佳。优选地b为约0.2至约1。更优选者c为0至约0.8。又更优选者d为0至约0.8。于上述的式子中，n指B-阶段材料中的重复单位数目。优选地，n为约3至约1000的整数。应了解，在任何固化步骤之前，该B-阶段有机聚氧化硅介电性基质材料可包括一或多个羟基或烷氧基封端或侧链官能基。这些封端或侧链官能基皆为谙于此技者所知悉。
适当的有机聚氧化硅介电性基质材料包括，但不限于，硅倍半氧烷，经部份缩合的卤硅烷或烷氧基硅烷例如通过控制水解具有约500至约20,000数量平均分子量之四乙氧硅烷而部份缩合；具有组成RSiO3或R2SiO2其中R为有机取代基且经有机改质硅酸酯；及具有Si(OR)4作为单体单位的部份缩合正硅酸酯。硅倍半氧烷为RSiO1.5型其中R为有机取代基的聚合物型硅酸酯材料。适当的硅倍半氧烷为烷基硅倍半氧烷类例如甲基硅倍半氧烷、乙基硅倍半氧烷、丙基硅倍半氧烷、丁基硅倍半氧烷等；芳基硅倍半氧烷类例如苯基硅倍半氧烷和甲苯基硅倍半氧烷；烷基/芳基硅倍半氧烷混合物例如甲基硅倍半氧烷和苯基硅倍半氧烷的混合物；以及烷基硅倍半氧烷类例如甲基硅倍半氧烷和乙基硅倍半氧烷的混合物。该有机聚氧化硅以包括甲基硅倍半氧烷为佳。B-阶段硅倍半氧烷材料包括硅倍半氧烷均聚物、硅倍半氧烷共聚物或其混合物。典型地，可用于本发明的硅倍半氧烷系作为具有约3至约10,000重复单位的低聚物型材料。
可用于本发明中适当的B-阶段有机介电性材料包括聚芳烯、聚芳烯醚类和苯并环丁烯类等揭示于WO 00/31183(Bruza et al.)，及揭示于美国专利第6,093,636号(Carter et al.)和第5,969,088号(Ezzellet al.)之中的聚酰亚胺类，这些全部并于本文就其对这些有机介电性材料的制备和用途上作为参考。其它适当的B-阶段有机介电性材料包括聚环烯烃例如聚原冰片烯均聚物和共聚物及聚二环戊二烯均聚物和共聚物。
可以理解可以使用介电性材料的混合物，例如两种或多种有机型，两种或多种无机型或一或多种有机型与一或多种无机型介电性材料之混合物。例如，可以使用烷基/芳基硅倍半氧烷的混合物、氢基/烷基硅倍半氧烷混合物、二或多种聚芳烯醚、二或多种聚酰亚胺等。特别适当的介电材料混合物包括无机-有机混成物，例如欧洲专利申请第EP997 497(Ioka et al.)中所揭示烷氧基硅烷/有机介电性材料，将此专利申请案所揭示这些混合材料的制备方面系于本文作为参考。
用于本发明中的孔原物为任何可在所选介电材料内移除以提供空隙、孔洞或自由容积且可减低这些材料的介电常数，特别是对于具有低介电常数(“k”)的介电材料者。低-k介电材料为任何具有低于约4的介电常数的材料。
可用于本发明中的可移除型孔原物在固化该B-阶段介电材料或将介电材料图样化所用的条件下不会实质移除。本发明的孔原物在不会实质降解或以其它方式不利地影响该介电材料的条件下移除。
有多种可移除性孔原物可用于本发明。该可移除性孔原物可为聚合物例如聚合物型粒子，或为能够与介电性单体共聚合形成具有不安定性(可移除性)成分的嵌段共聚物的单体或聚合物。于另一具体实例中，可将孔原物与介电性单体预聚合形成可为单体型，低聚物型或聚合物型之B-阶段介电材料。然后将这些预聚合B-阶段材料固化形成介电层。
优选地，该可移除型孔原物在该B-阶段介电材料中系实质地不聚集或不黏聚者。这些不聚集或不黏聚作用可减低或避免在介电性基质中发生阻断孔洞(killer pore)或信道形成之问题。该可移除型孔原物以孔原物粒子或可与介电性单体共聚合者为佳，优选地为孔原物粒子。该孔原物粒子系与该B-阶段介电性基质材料实质兼容者为更优选。“实质兼容”意指该B-阶段介电性材料的组合物与孔原物系稍微浑浊或稍微不透明者。优选地，“实质兼容”意指下列之中至少一者系稍微浑浊或稍微不透明者：B-阶段介电材料和孔原物的溶液、包括B-阶段介电材料组合物和孔原物之膜或层、包括具有孔原物分散在其中的介电性基质材料的组合物及在移除掉孔原物后所得的多孔型介电性材料。要成为兼容者，该孔原物必须可溶或可混溶于该B-阶段介电性材料中、可溶或可混溶于溶解该B-阶段介电材料所用的溶剂之中或两者中。适当的兼容孔原物揭露于共同申请的美国专利申请案序号第09/460,326(Allen et al.)之中。其它适当的可移除性粒子揭露于美国专利第5,700,844号中。
经实质地兼容的孔原物，典型地具有分子量范围为10,000至1,000,000，优选地20,000至500,000，且更优选者20,000至100,000。这些材料的多分散率(polydispersity)为1至20，优选地为1.001至15，且更优选者为1.001至10的范围内。这些经实质兼容的孔原物系以经交联者为佳。典型地，其交联性试剂含量为以孔原物重量为基准的至少约1重量％。高达且包括以孔原物重量为基准之100％的交联性试剂可以有效地用于本发明的粒子中。该交联剂用量以约1％至约80％为佳，且优选地为约1％至约60％。
作为可移除性孔原物且具有不安定性成分的适当嵌段共聚物揭露于美国专利第5,776,990号和第6,093,636号中。这些嵌段共聚物可通过，例如使用作为孔洞形成性材料的高度分枝型脂肪族酯类制备成，这些酯类具有官能基可进一步用恰当的反应性基官能化使得经官能化的脂肪族酯可掺入(亦即，共聚合到)玻化中的聚合物基质内。这些嵌段共聚物适合用来形成多孔型有机介电性材料，例如苯并环丁烯、聚(芳基酯)、聚(醚酮)、聚碳酸酯、聚原冰片烯、聚(芳烯醚)、聚芳烃例如聚萘、聚喹喏啉、聚(全氟化烃)例如聚(四氟乙烯)、聚酰亚胺、聚苯并噁唑及聚环烯烃。
要成为用来形成多孔型介电材料，本发明孔原物必须在不会对介电性基质材料产生不利地影响的条件下为至少部份可移除者，优选地为实质可移除者，且更优选者完全可移除者。“可移除”一词意指该孔原物可解聚或其它方式地分解成挥发性成分或片段，然后从介电材料移除掉，或渗移出，而产生孔洞或空隙。可以至少部份移除该孔原物而不会对介电性基质材料产生不利地影响的任何程序或条件都可以使用。以实质移除该孔原物为佳。典型的移除方法包括，但不限于：曝露于热、压力、真空或辐射，例如，但不限于：光化辐射、IR、微波、UV、x-射线、γ-射线、α粒子、中子束或电子束。需了解，可以使用一种以上的方法移除孔原物或聚合物，例如热和光化辐射的组合。以曝露该基质材料于热或UV光来移除该孔原物为佳。谙于此技者也应了解，可以采用其它方法移除孔原物，例如用原子抽除法(atomabstraction)。
本发明孔原物可以在真空、氮气、氩气、氮气和氢气的混合物，例如成形性气体(forming gas)，或其它惰性或还原性气氛之下经热移除。本发明孔原物可在高于该介电性基质材料所具热固化温度与低于其热分解温度之任何温度下移除。典型地，本发明孔原物可在150°至450℃范围内且优选地在250°至425℃的范围内之温度下移除。典型地，本发明孔原物系在加热时间1至120分钟范围内移除。在从介电性基质材料移除之后，于该多孔型介电材料中典型地会残留0至20重量％的孔原物。
于一具体实例中，当本发明孔原物通过曝露到辐射而移除时，该孔原物聚合物典型地系在惰性气氛例如氮气下曝露于辐射源，例如，但不限于，可视光或紫外光。于不欲受理论所拘束之下，相信会通过例如自由基分解而形成孔原物片段，且在惰性气流之下从基质材料移除。该辐射能量的适量必须足够至少部份地移除该孔原物粒子。
可移除性孔原物在本发明B-阶段介电性材料中典型的添加量为足以提供所需的低介电常数。例如，该孔原物在B-阶段介电性材料中的添加量以该B-阶段介电性材料重量为基准可为约1至约90重量％，优选地为10至80重量％，又优选地为15至60重量％，更优选者为20至30重量％。
当可移除性孔原物不是嵌段共聚物的成分时，可用技术领域中已知的任何方法与B-阶段介电性材料组合。典型地，系先将B-阶段材料溶解在适当的高沸点溶剂内，例如溶于甲基异丁基酮、二异丁基酮、2-庚酮、γ-丁内酯、γ-己内酯、乳酸乙酯、丙二醇-甲基醚乙酸酯、丙二醇-甲基醚、二苯基醚、甲氧苯、乙酸正戊酯、乙酸正丁酯、环己酮、N-甲基-2-吡咯烷酮、N，N’-二甲基伸丙基脲、1，3，5-三甲苯、二甲苯、或其混合物形成之溶液。然后将孔原物分散或溶解在该溶液内。之后将所得组合物(如，分散液、悬浮液或溶液)以技术领域中已知的方法沉积在基板上，例如用旋转涂布、喷洒涂布或用刮刀成型，而形成薄膜或层。
适当的基板包括，但不限于：硅，在绝缘体上的硅、硅锗、二氧化硅、玻璃、氮化硅、陶瓷、铝、铜、砷化镓、塑料，例如聚碳酸酯、电路板，例如FR-4和聚酰亚胺、及混合电路基板，例如氮化铝-氧化铝。这些基板复包括沉积其上面的薄膜，这些薄膜包括，但不限于：金属氮化物、金属碳化物、金属硅化物、金属氧化物、和其混合物。于多层集成电路组件中，具有绝缘、平面化电路线的底下层也可以作为基板。
在沉积于基板上面之后，可将该B-阶段介电性材料至少部份地固化，且优选地予以实质地固化，而形成刚硬，经交联且未实质地移除该孔原物的介电性基质材料。这些经固化的介电性基质材料典型地为一涂层或膜。介电性材料的固化可为技术领域中已知的任何手段包括，但不限于，加热以诱发缩合反应或用e-束照射以促成低聚物或单体单位的自由基偶合。典型地，该B-阶段材料系通过在高温加热予以固化，例如，直接地或以逐步方式地，如在200℃下历时2小时后以5℃/分的速率，跳升到300℃并保持在此温度下2小时。熟悉该项技艺者，可依所选用的特别B-阶段介电性材料而得知此种固化条件。
图4显示出经配置在含有金属钉12的基板10上含可移除孔原物17的介电性材料15。该可移除孔原物17并未按比例示出且以实质球体形式显示。应了解可用于本发明方法中的可移除性孔原物可为任何适当形状，优选地为实质球体且更优选者为球体者。
介电材料再经图样化及蚀刻以产生锐孔。典型地，这些图样化包括(i)用正型或负型光阻剂，例如为Shipley Company(Marlborough，MA)所销售者，涂覆于该介电性材料层；(ii)透过光罩成像曝光，将该光阻层曝光于辐射，例如恰当波长的光或e-束；(iii)将阻剂中的影像显现出，如用适当的显像剂；及(iv)用适当的转移技术例如反应性离子蚀刻，将影像透过介电层转移到基板。这些蚀刻可在介电性材料中造成锐孔。视情况地，在光阻层与介电性基质材料之间配置一抗反射涂层。此种平版印刷图样化技术系为熟悉该项技艺者所熟知。
图5显示出配置在含有可移除孔原物17的介电材料15上的光阻层40。参看第6图，显示出在介电材料15中的锐孔20。该锐孔20具有直侧壁30。这些直侧壁系源自穿过仍含有可移除孔原物的蚀刻操作。
根据本发明方法，直到第一金属层沉积之前，均未从介电性材料移除该孔原物。这些金属层典型地系在锐孔蚀刻之后沉积。这些金属层可包括一或多层障壁层、种层及金属涂敷层。如在本说明书整体中所用者，“金属涂敷层”指的是实质地或完全地填充该锐孔的金属层，亦即锐孔填充层。典型地，第一金属层为障壁层或种层。当要用铜填充锐孔时，典型地为施涂一障壁层，例如用化学气相沉积(“CVD”)或物理气相沉积(“PVD”)。障壁层典型地系使用铜来阻止铜渗移到介电材料内且相对于金属涂敷层而言典型地系薄者。这些障壁层可为传导性者，半-传导性者或非-传导性者。适当的障壁层包括，但不限于下列中的一或多者：钽、氮化钽、氮化硅化钽、钛、氮化钛、钨、氮化钨及氮化硅化钨。可以使用一种以上的障壁层，例如用钛接着用氮化钛且视情况接着用氮化硅化钛。这些障壁层可为不连续层或为渐进式者，例如从底部的钛通过次化学计算氮化钛到化学计算氮化钛上层。优选地为含有一障壁层者。第7图显示出根据本发明在含有可移除性孔原物17的介电材料15上沉积的障壁层35。该锐孔的直侧壁30提供一实质连续性，且优选地为连续性的障壁层35。
当用到时，可将种层施涂至介电材料上作为第一金属层，或施涂至事先沉积好的障壁层之上。适当的种层包括铜或铜合金。于没有障壁层即使用种层时，优选地该种层不是铜。这些种层也可以用CVD或PVD予以沉积且相较于金属涂敷层而言系较薄者。另外，可用无电方式施涂种层。因而，种层包括供无电式电镀所用的触媒。
在沉积好这些障壁层及/或种层之后，可将锐孔用，例如铜或铜合金予以金属涂敷或填充。此种金属涂敷可为任何手段，不过优选地至少为部份电解式，且更优选者为电解式者。金属涂敷这些锐孔的方法系为熟悉该项技艺者所熟知。例如可以使用可得自ShipleyCompany(Marlborough，Massachusetts)，的ULTRAFILL TM2001印铜沉积化学来进行锐孔的电解式铜金属涂敷。
另外，可以将锐孔以无电方式金属涂敷或填充而不需要障壁层或种层。若用铜以无电方式将锐孔金属涂敷时，优选地要有障壁层。
沉积好的金属层典型地要平面化处理过。虽然每一沉积好的金属层均可接受平面化处理，不过从加工容易性看来优选地为将锐孔填充金属层予以平面化处理。熟悉该项技艺者皆了解该孔原物需要保留在该介电层内直到第一金属层，典型者为障壁层或种层均沉积好为止。考虑孔原物成分从介电性基质移除的容易性，在沉积该第一金属层之后，即可移除孔原物。在平面化处理之后，优选地在锐孔填充金属层的平面化处理之后才移除孔原物。
在沉积好至少一金属层之后，以至少部份移除掉孔原物而不会实质地降解该介电材料，亦即，只失去低于5重量％该介电性材料的条件处理该介电性材料。典型地，这些处理条件包括将该膜曝露于热及/或辐射。优选地为将该基质材料曝露于热或光以移除该孔原物。要以热方式移除孔原物时，可通过烘箱加热或微波加热来加热该介电基质材料。在典型的热移除条件之下，系将经聚合的介电性基质材料加热到约350℃至400℃。热悉该项技艺者都了解一种热不安定性孔原物的特别移除温度系根据孔原物的组成而变异。于移除后，孔原物会解聚或以其它方式分解成挥发性成分或片段而从介电性基质材料移除，或渗移出，产生孔洞或空隙，这些可能由程序中所用的载气予以填充。如此，得到具有孔隙的多孔型介电材料，其中的空隙大小优选地系与孔原物的粒度实质地相同。如此所得到具有空隙的介电性材料相较于没有这些空隙的材料具有较低的介电常数。一般而言，可得到最高达约1,000奈米的孔洞尺寸，例如具有约0.5至约1000奈米范围内的平均粒子尺寸者。该平均孔洞尺寸系在约0.5至约200奈料为佳，优选地约0.5至约50奈米，且更优选者约1奈米至约20奈米的范围内。
移除该孔原物，系以金属层经平面化处理之后为佳，优选地系在该金属涂敷层经平面化处理之后。因此，本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；b)不实质地移除该孔原物的条件下，固化该B-阶段介电性基质组合物形成介电性基质材料；c)将该介电性基质材料图样化；d)在该介电性材料的表面上沉积至少一障壁层或种层；e)沈积一锐孔填充金属层；f)平面化处理该锐孔填充金属层；及g)以至少部份地移除该孔原物形成多孔型介电材料层而不实质地降解该介电材料的条件处理该介电基质材料。
图8表示出在平面化处理后的电子组件，包括含有孔洞16的介电性材料15、实质连续的障壁层35和经金属涂敷的锐孔45。
本发明在电子组件制造上提供数项优点：线条边缘或锐孔侧壁粗糙性得以减少或消除、由于障壁层系沉积在更平滑的锐孔侧壁表面上因而达到改良的障壁层性能、铜锐孔填充具有改良的电传导性以及减少整体加工的步骤和时间。
多孔型介电材料的传统加工中需要用到盖层(cap layer)。根据本发明，在平面化处理步骤之后才移除孔原物可减少或消除掉对于盖层的需要，其可降低整体的介电常数。根据本发明，由于该介电材料具有更优选的尺寸稳定性，更优选的机械强度及对于来自任何平面化处理浆液或洗液的污染较不敏感，因此不需要这些盖层。本发明提出一种制造电子组件的方法，其包括下列步骤：a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；b)在未实质地移除该孔原物的条件下，固化该B-阶段介电性基质组合物形成介电性基质材料；c)将该介电性基质材料图样化；d)在该介电性材料的表面上沉积一金属层；e)以至少部份移除掉该孔原物形成多孔型介电材料层而不会实质地降解该介电性材料的条件处理该介电性基质材料；及f)对该多孔型介电层进行后续加工步骤，其中所述的多孔型介电层不含加盖层。优选地，步骤f)包括在多孔型介电材料层上配置一B-阶段介电性基质组合物，这些B-阶段介电性基质组合物可与步骤a)中所用者相同，或可为不同者。优选地，步骤f)中所用的B-阶段介电性基质组合物系与步骤a)中所用者相同。优选地，于步骤d)中的金属层为一种锐孔填充层。此外，该方法复包括下述步骤为较佳：在移除该孔原物之前将沉积的金属层平面化处理。因此，本发明也提出一种电子组件其包括一不含加盖层的多孔型介电层。不具加盖层可具有减低介电层整体介电常数之优点。应了解，这些电子组件可以含有一或多个多孔型介电层，其中至少一层不含加盖层，且优选地为每一多孔型介电材料层都不含加盖层。
再者，免除加盖层可提供具有粗糙表面的多孔型介电材料层。此种粗糙表面系源自于在平面化处理后位于表面处的孔原物之移除。于不欲受理论所拘束之下，相信多孔型介电材料层的粗糙表面可提供对于后续施涂的介电材料透过该介电层的机械交锁所增加的黏着性。因此，本发明也提出一种改良介电材料对多孔型介电材料层的黏着性的方法，其包括下列步骤：a)在平面化处理步骤之后从固化的介电性基质材料移除孔原物以形成多孔型介电材料层；b)在该多孔型介电性材料层上配置一B-阶段介电性基质组合物；c)固化该B-阶段介电性基质组合物形成一介电性基质材料。此种在介电层之间改良的黏着性可减少个别层脱层问题。
虽然本发明系针对集成电路制造而说明，不过，应了解其它的电子组件也可根据本发明来制备。

Claims (14)

1.一种制造电子组件的方法，其包括下列步骤：
a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；
b)在不实质地移除该孔原物的条件下固化该B-阶段介电性基质组合物，形成介电性基质材料；
c)将该介电性基质材料图样化；
d)在该介电性材料的表面上沉积一金属层；及
e)以至少部份移除该孔原物而形成一多孔型介电材料层且不实质地降解该介电材料的条件处理该介电性基质材料。
2.根据权利要求1所述的方法，其中所述的B-阶段介电材料选自下列中之一或多项：有机聚氧化硅；硅、硼或铝的碳化物、氧化物、氮化物和氧氟化物；苯并环丁烯类；聚(芳基酯)类；聚(醚酮)类；聚碳酸酯类；聚(芳烯醚)类；聚芳族烃类；聚(全氟烃类)；聚酰亚胺类；聚苯并噁唑类和聚环烯烃类。
3.根据权利要求1所述的方法，其中所述的B-阶段介电性材料选自烷基硅倍半氧烷；芳基硅倍半氧烷；烷基/芳基硅倍半氧烷混合物；及烷基硅倍半氧烷混合物。
4.根据权利要求1所述的方法，其中所述的金属层为一或多层障壁层、种层或锐孔填充金属层。
5.根据权利要求1所述的方法，其中所述的可移除性孔原物系与该B-阶段介电材料基本上兼容的。
6.根据权利要求1所述的方法，该方法还包括下述步骤：在至少部份移除该孔原物之前将该金属层平面化处理。
7.一种制造电子组件的方法，其包括下述步骤：
a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；
b)在不实质地移除该孔原物的条件下固化该B-阶段介电性基质组合物，形成介电性基质材料；
c)将该介电性基质材料图样化；
d)在该介电性材料的表面上沉积至少一障壁层或种层；
e)沉积锐孔填充金属层；
f)将该锐孔填充金属层平面化处理；及
g)以至少部份移除该孔原物而形成一多孔型介电材料层且不实质地降解该介电材料的条件处理该介电性基质材料。
8.根据权利要求7所述的方法，其中所述的B-阶段介电材料系选自下列中之一或多项：有机聚氧化硅；硅、硼或铝的碳化物、氧化物、氮化物和氧氟化物；苯并环丁烯类；聚(芳基酯)类；聚(醚酮)类；聚碳酸酯类；聚(芳烯醚)类；聚芳族烃类；聚(全氟烃类)；聚酰亚胺类；聚苯并噁唑类和聚环烯烃类。
9.根据权利要求7所述的方法，其中所述的锐孔填充金属层包括铜或铜合金。
10.根据权利要求7所述的方法，其中所述的可移除性孔原物可与该B-阶段介电材料基本上兼容。
11.一种制造电子组件的方法，其包括下列步骤：
a)在一基板表面上配置一B-阶段介电性基质组合物，该组合物包括一或多种介电性基质材料及可移除性孔原物；
b)在不实质地移除该孔原物的条件下固化该B-阶段介电性基质组合物，形成介电性基质材料；
c)将该介电性基质材料图样化；
d)在该介电性材料的表面上沉积一金属层；
e)以至少部份移除该孔原物而形成一多孔型介电材料层且不实质地降解该介电材料的条件处理该介电性基质材料；及
f)对该多孔型介电层进行后续加工步骤；
其中所述的多孔型介电层不含附加盖层。
12.一种电子组件，其包括不含附加盖层的多孔型介电层。
13.根据权利要求12所述的组件，其中所述的多孔型介电层选自下列中之一或多项：有机聚氧化硅；硅、硼或铝的碳化物、氧化物、氮化物和氧氟化物；苯并环丁烯类；聚(芳基酯)类；聚(醚酮)类；聚碳酸酯类；聚(芳烯醚)类；聚芳族烃类；聚(全氟烃类)；聚酰亚胺类；聚苯并噁唑类和聚环烯烃类。
14.一种改良介电性材料对多孔型介电材料层的黏着性的方法，其包括下列步骤：a)在平面化处理步骤之后从固化的介电性基质材料移除该孔原物而形成多孔型介电材料层；b)在该多孔型介电材料层上配置一B-阶段介电性基质组合物；及c)固化该B-阶段介电性基质组合物，形成一介电性基质材料。
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