WO2006064416A1

WO2006064416A1 - A semiconductor device having a recess with non-porous walls in a porous dielectric and a method of manufacturing such a semiconductor device

Info

Publication number: WO2006064416A1
Application number: PCT/IB2005/054101
Authority: WO
Inventors: Yukiko Furukawa; John Macneil
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-12-16
Filing date: 2005-12-07
Publication date: 2006-06-22
Also published as: TW200636913A

Abstract

This invention relates to a semiconductor device and a method of manufacturing such a device. An embodiment of the semiconductor device (1) according to the invention comprises a substrate (10), a dielectric layer (21) applied to the substrate (10), the dielectric layer (21) having a recess (50), the recess (50) having walls defined by the dielectric layer (21), the recess (50) being filled with a conductor (90), the conductor (90) being embedded by a barrier layer (85) at least on sidewalls of the conductor (90), while the dielectric layer (21) comprises non-porous regions (75) adjacent to the walls of the recess (50) and porous regions (25) away from the recess (50). The conductor (90) is provided with a capping layer (95). It is an important aspect of the invention that the width W of the non- porous regions (75) is smaller than 40 nanometer. The smaller the width of the modified regions the lower the effective k- value. A further important aspect of the invention is that the modified layers 75 are substantially free of silicon oxide like material.

Description

A SEMICONDUCTOR DEVICE HAVING A RECESS WITH NON-POROUS WALLS IN A POROUS DIELECTRIC AND A METHOD OF MANUFACTURING SUCH A SEMICONDUCTOR DEVICE

The invention relates to a semiconductor device comprising a substrate, a dielectric layer applied to the substrate, the dielectric layer having a recess, the recess having walls defined by the dielectric layer, the recess being provided with a conductor embedded by a barrier layer present at least on sidewalls of the recess, while the dielectric layer comprises non-porous regions adjacent to the walls of the recess and porous regions away from the walls of the recess.

The invention also relates to a method of manufacturing such a semiconductor device.

Such a semiconductor device is known from European patent application no. EPl, 195, 801 A2. The known semiconductor device comprises a semiconductor substrate comprising a low-k dielectric layer, the low-k dielectric layer further being covered with a hard-mask layer, the low-k dielectric layer having an opening extending through the hard- mask layer and the low-k dielectric layer, the sidewalls of the opening being covered with a protective layer, the protective layer being obtained by using a resist stripping chemistry comprising oxygen and nitrogen, the opening further being provided with a conductive material, the conductive material at least partially being encapsulated by a diffusion barrier layer. A drawback of the known semiconductor device is that the protective layer deteriorates the electrical performance of the semiconductor device.

It is therefore an object of the invention to provide a semiconductor device, which has an improved electrical performance.

According to the invention this object is achieved in that the width of the non- porous regions, the width being measured in a direction parallel to the substrate and perpendicular to the walls of the recess, is smaller than 40 nanometer. The non-porous regions comprise material having modified characteristics. One of these characteristics being relevant to the electrical performance of the device is the dielectric constant of the material. Especially for low-k dielectric materials (e.g. k- value below 3.0), the dielectric constant of the non-porous regions may be significantly higher than the dielectric constant of the porous regions. Thus in the case where the dielectric constant (from now on the term k-value will be used in this description, and will refer to the relative dielectric constant) of said non-porous regions is higher than the k-value of the porous regions, it is advantageous to keep the first regions thin. The influence of the first regions on an effective k-value is then reduced, which also leads to a lower parasitic capacitance of the conductor. The effective k-value is defined as the k-value "seen" by the conductor. This will be explained in more detail later in this description. In general it can be stated that the lower the effective k-value the lower the parasitic capacitance of the conductor, which will improve the electrical performance of the semiconductor device.

In an embodiment of the semiconductor device according to the invention the k-value of the non-porous regions is lower than 3.9. It is very advantageous to use materials for the non-porous regions that have a k-value lower than 3.9. The lower the k-value of said non-porous regions, the lower the effective k-value "seen" by the conductor. One way to fulfill this requirement is to keep the quantity of silicon-oxide-like material in the non-porous regions as low as possible and preferably to have no silicon-oxide-like material in the non- porous regions at all. In another embodiment of the semiconductor device according to the invention the barrier layer is thinner than or equal to 5 nanometer. This measure has several advantages. First of all, the conductor can be made thicker, which leads to a lower resistance of the conductor, because in general the barrier layer has a higher resistance than the conductor. Second, a thinner barrier layer leads to a lower contact/via resistance. In another embodiment of the semiconductor device according to the invention the thickness of the barrier layer is substantially uniform within the recess. This measure is advantageous because the resistance of the conductor is then better defined.

In another embodiment of the semiconductor device according to the invention the k-value of the porous regions is lower than 3.0. The main advantage of this measure is that the effective k-value seen by the conductor is kept low.

A method of manufacturing a semiconductor device is known from US6,528,409Bl. The known method comprises the following steps: forming a low-k precursor material that is not completely cured; forming a layer of hard-mask material on the precursor material; forming an interconnect opening through the precursor material; filling the interconnect opening with diffusion barrier material; filling the interconnect opening with copper conductive material; polishing to expose the diffusion barrier material and the copper conductive fill within the opening; forming an activation layer on exposed surface of diffusion barrier material and the conductive fill; selectively forming a capping material comprising amorphous alloy or microcrystalline alloy having stuffed grain boundaries in an electroless deposition process. A drawback of the known method is that the resulting semiconductor devices are not reliable, due to possible diffusion of the barrier material (and consequently the conductive fill material) into the porous low-k material where chemical reactions might occur. This effect severely deteriorates the reliability of the semiconductor device.

It is therefore object of the invention to provide a method, which results in more reliable semiconductor devices.

According to the invention this object is achieved in that the method of manufacturing a semiconductor device comprises the steps of: providing a semiconductor structure comprising a substrate, a low-k precursor material layer applied thereto whereby the precursor material is non-cured or partially-cured, the semiconductor structure being covered by a patterned photoresist layer, the semiconductor structure further comprising a recess extending through the photoresist layer at least into the low-k precursor material layer, the recess having walls defined by the low-k precursor material layer; stripping the photoresist layer by means of a stripping chemistry, the stripping chemistry converting the low-k precursor material adjacent to the walls of the recess into a non-curable material; and curing the low-k precursor material layer, whereby the low-k precursor material layer is converted into a low-k material layer.

After having applied the second step of this method, the non-curable material near the walls of the recess can no longer be converted into porous material. Thus this method prevents the formation of pores in the dielectric material near the recess during the curing step, which counteracts diffusion of material from the recess to the low-k dielectric material. As a result a semiconductor device with a higher reliability is obtained. In an embodiment of the method according to the invention the stripping chemistry is substantially oxygen and fluorine and chlorine and bromine free. This measure has several advantages being: no or little formation of silicon oxide like material (which keeps the k- value low) in the low-k precursor material; and no isotropic etching of the low-k precursor material during stripping, preserving the k- value of the low-k material.

In an embodiment of the method according to the invention the stripping chemistry comprises hydrogen. The use of hydrogen is advantageous because of multiple reasons. First of all, hydrogen reacts with the low-k precursor material forming polymers. Thus during stripping of the photoresist, formation of polymers on the walls of the recess is enhanced. These polymers form a sealing layer and protect the walls of the recess against attacked by other chemicals. Second, the polymers comprise hydride bonds and have a lower k-value than for example silicon oxide. This will reduce the effective k-value (when compared with the situation where silicon oxide is formed) of a conductor being at least partially embedded by these polymers.

In a further embodiment of the method according to the invention the stripping chemistry comprises nitrogen. The use of nitrogen is advantageous, because it will especially react with organic compound of the low-k precursor material forming CN-bonds. This effect is referred to by the term of "networking". It is important to stress that the walls of the recess will be modified such that they can no longer be cured (turned into non-porous dielectric). The CN-bonds in the modified walls have a lower k-value than for example silicon oxide like material. This will reduce the effective k-value (when compared with the situation where silicon oxide like material is formed) of a conductor being at least partially embedded by these modified walls. Another positive effect of using nitrogen in the stripping chemistry is that it contributes to ion bombardment (sputtering), which is beneficial for the stripping resist and polymer residues.

In a further embodiment of the method according to the invention the stripping chemistry comprises an inert gas. The use of inert gas is advantageous because of its contribution to the ion bombardment (sputtering) as well as its contribution to acceleration of the chemical reaction between the stripping chemistry and the low-k precursor material (also referred to as catalyst function). Preferably the inert gas comprises one or more of helium, neon and argon. Heavier ions will result in a stronger ion bombardment effect and a stronger catalyst function, but will also increase the risk of inflicting damage on other parts of the device being manufactured.

In another embodiment of the method according to the invention a semiconductor structure is provided with a recess extending completely through the low-k precursor material layer. The advantage of this embodiment is that this method allows to create an electric contact of conductive material inside the recess with layers below the low-k precursor material layer. This is very beneficial when manufacturing a contact or a via for making contact between metallization layers.

In an embodiment of the method according to the invention the semiconductor structure is provided with a hard mask layer in between the low-k precursor material layer and the photoresist layer. The hard mask layer has the advantage that it gives enough etch selectivity and prevents reaction between photoresist and low-k materials and it acts as an anti-reflection layer during manufacturing of the semiconductor device. The anti-reflection layer protects the photoresist layer for reflections of light (preferably UV- light) from lower layers in the semiconductor device being manufactured. Reflected light may interfere with light coming from a light source resulting in a deterioration of patterns in the photoresist layer.

In an embodiment of the method according to the invention the method further comprises a step of applying a barrier layer at least on the sidewalls of the recess of the semiconductor structure. The advantage of this measure is that it enables encapsulation of conductive materials, which should not diffuse into regions where circuitry has been implemented. Especially for example copper severely deteriorates the performance and reliability of a semiconductor device.

In a further improvement of the last embodiment the method further comprises a step of providing a conductor in the recess. This embodiment is advantageous, because it enables the manufacturing of conductive lines, vias and contacts.

In a further improvement of the last embodiment the method further comprises a step of forming a capping layer at least on the conductor. This measure is especially beneficial when no contact has to be made with a top surface of the conductor. For example in case of manufacturing a conductor line.

These and other aspects of invention will be further elucidated and described with reference to the drawings, in which: Figs. 1-9 illustrate a semiconductor device in different stages of the method according to the invention;

Fig. 10 illustrates a first embodiment of the semiconductor device according to the invention; Fig. 11 illustrates a second embodiment of the semiconductor device according to the invention.

In relation to the appended drawings the present invention is described in detail later on. However, it is apparent that a person skilled in the art can imagine several other equivalent embodiments (or combine the embodiments explicitly given in this specification) or other ways of executing the present invention, the spirit and scope of the present invention being limited only by the terms of the appended claims. All drawings are intended to illustrate some aspects and embodiments of the present invention. Most aspects are presented in a simplified way for reason of clarity. Not all alternatives and options are shown and therefore the invention is not limited to the content of the given drawings.

Fig. 1 illustrates a semiconductor device in a stage of the method according to the invention. In this stage the semiconductor device comprises a substrate 10, while the substrate 10 is covered with a low-k precursor material layer 20. With the word "low-k" is meant k- values preferably below 3.0. It is these kinds of dielectric materials often being porous and therefore suffering from the problems as defined in the introduction of this specification. The low-k precursor material layer 20 is covered with a hard mask layer 30. The substrate 10 may comprise a wafer with active devices (e.g. transistors, diodes, etc), but also other dielectric layers, which in their turn may comprise conductor structures (e.g. interconnections, contacts and vias). The wafer may comprise silicon, germanium, strained- silicon, buried oxide layers and the like. The low-k precursor material layer 20 may comprise CVD low-k materials and spin-on low-k materials. It is an essential part of the invention that the low-k precursor material 20 is non-cured or just partially cured. Non-cured (or partially cured) low-k precursor material still comprises organic material, which is needed in a later stage in the method. The hard mask layer 30 may comprise materials such as silicon nitride (Si₃N₄), silicon carbide (SiC), silicon oxide (SiO₂) and/or different low-k materials.

Fig. 2 illustrates a semiconductor device in another stage of the method according to the invention. In this stage a patterned photoresist layer 40 is applied on top of the hard mask layer 30 of the semiconductor device. The hard mask layer 30 is generally needed to get etch selectivity and as an anti-reflection layer for the photoresist layer 40, but also to prevent chemical reaction between the photoresist layer 40 and the low-k precursor material layer 20. The anti-reflection layer protects the photoresist layer for reflections of light (preferably UV-light) from lower layers in the semiconductor device being manufactured. Reflected light may interfere with light coming from a light source resulting in a deterioration of patterns in the photoresist layer.

Fig. 3 illustrates a semiconductor device in another stage of the method according to the invention. In this stage a recess 50 is formed using the patterned photoresist layer 40, the recess 50 extending through the hard mask layer 30 into the low-k precursor material layer 20. The recess 50 may be formed by means of chemical etching, for instance using a plasma 100 in a tool. The plasma 100 may comprise chemistries like Ar / C_xH_yF_z / O₂ (whereby x,y,z >= 0) , but other chemistries are also possible. During the formation of the recess 50 polymer residues 60 are deposited on sidewalls of the recess 50. It is known to the person skilled in the art that the formation of these residues 60 can be used for making sidewall slopes of the recess 50 substantially perpendicular to the substrate 10. The polymer residues 60 protect the low-k precursor material layer 20 against attack by the etching chemistries 100. More information on this aspect can be found in ["Dry etching for VLSI" by AJ. van Roosmalen, J.A.G. Baggerman, S.J.H. Brader, Plenum press, New York(1991) ISBN 0-306-43835-6, pp. 99-110]. Although, the names of the corresponding gases have been mentioned in this description, these gases refer to the plasma being made of these gases.

Figs. 4a and 4b illustrate a semiconductor device in another stage of the method according to the invention. In this stage of the method the photoresist layer 40 is stripped. In the prior art, stripping is also referred to by the term of "ashing". Stripping maybe done with a plasma comprising stripping chemistry 110. During stripping of the photoresist layer 40 also the polymer residues 60 are removed. In more detail, it can be stated that this stage of the invention comprises two sub-steps. In a first sub-step (Fig. 4a) the polymer residues 60 in the recess 50 are removed, exposing the low-k precursor material of the dielectric layer 20. And in a second sub-step (Fig. 4b) the material in the sidewalls of the recess 50 is converted into a non-curable layer 75. It is an important aspect of the invention that the stripping chemistry 110 is chosen such that the low-k precursor material 20, facing walls of the recess 50, is converted into a non-curable layer 75 (also being referred to as sidewall modification). The result of this measure is that the non-porous non-cured low-k precursor material (or partially cured low-k precursor material, which is slightly porous) will not be converted into (more) porous material at a later stage in the method. In this particular embodiment nitrogen (N₂) is used in the stripping chemistry 110. As a consequence of this, nitrogen will react with the low-k precursor material 20 forming networks of CN-bonds at the places near the sidewalls 70 of the recess 50 where organic material is located. Especially these regions 70 would otherwise be converted into pores after a curing step. Thus the regions facing the recess 75 are converted into non-curable material.

Other embodiments of the invention use other stripping chemistries 110 like for instance hydrogen (H₂)- In that case no networks of CN-bonds will be formed, but instead polymerization during stripping will be enhanced. As a consequence of this, less low-k material will be modified during stripping, because the low-k material 20 is protected by the polymers being formed by the H2-chemistry 110.

It is advantageous to use stripping chemistry 110, which is substantially oxygen and chlorine and fluorine and bromine-free. When using oxygen in the chemistry, oxygen will react with the low-k precursor material forming silicon oxide like material. Silicon oxide has a high k- value (around 4.0), which will increase the effective k- value of a conductor being at least partially embedded in the silicon oxide. When using fluorine or chlorine or bromine in the stripping chemistry, those chemicals will also react with silicon forming silicon fluoride and/or silicon chloride and/or silicon bromide. Some of these silicon compounds are volatile. As a consequence of this, the recess will undergo an isotropic etch, which is highly unwanted in a stripping process.

Thus using a stripping chemistry 110, which is substantially oxygen and fluorine and chlorine and bromine-free, has several advantages which are: no or little formation of silicon-oxide-like material (which keeps the k- value low) in the low-k precursor material; and - no isotropic etching of the low-k precursor material during stripping preserving the k- value of the low-k material.

Another important aspect of the invention is that the stripping chemistry 110 is chosen such that the converted layers 75 are as thin as possible. A stripping chemistry 110 comprising nitrogen and hydrogen (N2/H2) or a stripping chemistry comprising helium and hydrogen (He/H2) achieve the best result in this respect. Measurements have shown that the thickness of the modified layer 75 is below 30nm in case of He/H2 chemistry.

Fig. 5 illustrates a semiconductor device in another stage of the method according to the invention. In this stage the semiconductor device is cured. In the prior art various curing methods are known. One class of methods uses heat treatment and another class of methods uses plasma treatment. Typical process conditions for each class are: 1. heat treatment : 400-500⁰C, N₂ atmosphere (30mTorr-20Torr) or O₂-free atmosphere, duration = 5-60mins. 2. plasma treatment : H₂-HoW = 1000 seem, pressure = 4Torr, RF power = IkW,

RF frequency = 1356MHz, platen temperature = 400⁰C, duration = 5-60mins.

More details on curing techniques and required process conditions can be found in US patent 6,653,247 B2.

It is also possible to cure at different stages of the method (e.g. after barrier deposition and after chemical-mechanical-polishing). During curing, organic materials in the low-k precursor material layer 20 evaporate. This will create pores 80 in the low-k precursor material layer 20 turning it into a porous (low-k) dielectric layer 21. It is important to realize that in this specification the word "porous" means that it is permeable to gases and fluids. Although in the drawings isolated pores 80 have been drawn, the pores may be connected to each other via small channels (not drawn). Thus it is an important aspect of the invention that not only pores 80 are filled/converted, but also the channels between the pores 80.

Fig. 6 illustrates a semiconductor device in another stage of the method according to the invention. In this stage a barrier layer 85 is applied at least into the recess 50. The barrier material 85 may comprise materials such as tantalum (Ta) which is applied by means of PVD techniques. An alternative material is tungsten carbon nitride (WCN) which is applied by means of ALD techniques. However, the barrier material layer 85 may also comprise a layer stack like a layer of tantalum nitride with a layer of tantalum (both layers may also be applied using PVD techniques). It is an important advantage of the invention that due to the modification of the sidewalls of the recess a thinner barrier layer 85 can be applied. The barrier layer 85 may typically be thinner than or equal to 5 nanometer. Thus the barrier layer 85 can now be deposited using atomic layer deposition (ALD) techniques. Without the modification of the sidewalls a thicker barrier layer 85 is required. Another important advantage of the invention is that the barrier layer can be applied in a more uniform manner within the recess. After the barrier layer 85 has been applied (Fig. 7) a conductor 90 is applied at least to the recess 50. The conductor 90 may for instance comprise materials like copper or aluminum. The main function of the barrier material is to encapsulate conductive materials, which should not diffuse into circuitry of the semiconductor device, because they would harm the reliability of the semiconductor device. A known example of such a material is copper. In case other materials are used, like for instance aluminum, the barrier layer 85 might be left out.

Fig. 8 illustrates a semiconductor device in another stage of the method according to the invention. In this stage the semiconductor device is planarized using for example a chemical-mechanical-polishing step (also known as CMP). In this particular example the CMP process stops at the hard mask layer 30. However, it is optional to remove the hard mask layer 30 as well.

Fig. 9 illustrates a semiconductor device in another stage of the method according to the invention. In this stage a capping layer 95 is provided on the semiconductor structure. This may be a capping layer 95 covering large areas or a patterned capping layer only covering those areas where a conductor 90 is located. The capping layer 95 is needed for completing the encapsulation by the barrier layer 85. In case a contact is needed with the conductor 90 from the top, the capping layer can be patterned exposing the conductor 90 for enabling electrical contact from the top. The capping layer may comprise silicon nitride (Si₃N₄) and silicon carbide (SiC), but other materials are also possible.

It must further be noted that, although in this particular example the conductor 90 resembles a conducting line (the recess being a trench) running perpendicular to the cross- section in Fig. 9, it may also be a contact or via. In that case the recess 50 must be a hole in the low-k precursor material layer 20 (Fig. 5). Furthermore, it is also possible to perform the method such that a conducting line and a contact are formed at the same time. This can be achieved in various ways. One way is to perform the step of forming the recess in the low-k precursor material 20 in two different steps (e.g. after having formed two dielectric layers) using different masks, while keeping the rest of the method the same. A person skilled in the art may easily come up with alterations in the order in which the steps are performed.

After the stage illustrated in Fig. 9 the semiconductor device is ready for further processing, like forming subsequent metallization and/or contact/via layers, packaging, etc. All these steps are known to a person skilled in the art.

Fig. 10 illustrates a first embodiment of the semiconductor device according to the invention. This semiconductor device 1 comprises a substrate 10, a dielectric layer 21 applied to the substrate 10, the dielectric layer 21 having a recess 50, the recess 50 having walls defined by the dielectric layer 21, the recess 50 being filled with a conductor 90, the conductor 90 being embedded by a barrier layer 85 at least on sidewalls of the conductor 90, while the dielectric layer 21 comprises non-porous regions 75 adjacent to the walls of the recess 50 and porous regions 25 away from the recess 50. The semiconductor device 1 in this embodiment further comprises hard mask layers 30. However, in other embodiments these hard mask layers 30 may be absent. In this particular example the conductor 90 (e.g. a copper line) is provided with a capping layer 95. In some embodiments this capping layer 95 may be absent or partially removed (e.g. to allow a contact to be in electrical contact with a line).

It is an important aspect of the invention that the width W of the non-porous regions 75 (also referred to as modified regions), the width W being measured in a direction parallel to the substrate 10 and perpendicular to the recess 50, is smaller than 40 nanometer. The smaller the width of the modified regions, the less the effective k- value of the dielectric layer 21 deviates from the k- value porous regions 25 and thus the lower the effective k- value. A further important aspect of the invention is that the modified layers 75 are preferably substantially free of silicon oxide-like material. Silicon oxide and silicon oxide-like material has a high k- value (around 4.0) and would therefore increase the effective k- value of the dielectric layer 21, which would result in an increased parasitic capacitance of the conductor 90. The effective k- value of the conductor 90 is defined as the k- value, which is "seen" by the conductor 90.

The wider the modified regions 75 (generally having a higher k-value than the porous regions 25), the higher the effective k-value may be. In the situation where the modified region 75 covers the complete dielectric layer 21, the effective k-value is the same as the k-value of the modified region 75. The opposite scenario is that the modified regions 75 have a negligible width W, such that the effective k-value is the same as the k-value of the porous regions 25.

In this particular example layers 15, 35 do not comprise conductors, however in other embodiments this is very well possible. Fig. 11 illustrates a second embodiment of the semiconductor device according to the invention. The semiconductor device 2 comprises all elements from the first embodiment of the semiconductor device 1, whereby the dielectric layer 21 further comprises a further recess 50' at a distance from the recess 50, the further recess 50' having further walls defined by the dielectric layer 21, the further recess 50' being filled with a further conductor 90', the further conductor 90' being embedded in a further barrier layer 85' at least on sidewalls of the further conductor 90', while the dielectric layer 21 comprises further non- porous regions 75' adjacent to the further walls of the further recess 50'.

In this specific embodiment the effective k-value can be more easily be defined as the k-value between the conductor 90 and the further conductor 90'. For illustration purposes, assuming that the non-porous regions 75, 75' touch each other (meaning that they have a large width W, W), the effective k-value is the same as the k- value of the non-porous (modified) layers, which would lead to a high effective k-value and thus a high parasitic mutual capacitance between said conductors 90, 90'. On the other hand, small widths W, W will lead to lower effective k-values and thus lower parasitic mutual capacitances between the conductors 90, 90'.

Please note that the description is meant to support the claims rather than limit them. Many variations to the shown illustrations are possible, but have been left out of the discussion in order to keep the invention clear and concise. The non-porous regions prevent direct contact between the porous low-k material and the barrier material. This prevents diffusion of material (barrier material and/or conductive material) into the dielectric layer, which results in increased reliability of the semiconductor device.

Further scaling of semiconductor technology feature sizes will result in a further reduction of the dielectric constant (k-value) of the dielectric material required in these technologies. Mostly a lower dielectric constant means higher porosity of the dielectric material. A higher porosity will ease the diffusion of barrier material into the dielectric material. Thus in future it will be even more important to seal sidewalls of a recess. This invention provides a method, which allows proper sealing of those large pores, whereas state of the art methods are not capable of doing so.

Claims

CLAIMS:

1. A semiconductor device (1,2) comprising a substrate (10), a dielectric layer (21) applied to the substrate (10), the dielectric layer (21) having a recess (50), the recess (50) having walls defined by the dielectric layer (21), the recess (50) being provided with a conductor (90) embedded by a barrier layer (85) present at least on sidewalls of the recess (50), while the dielectric layer (21) comprises non-porous regions (75) adjacent to the walls of the recess (50) and porous regions (25) away from the walls of the recess (50), characterized in that the width (W) of the non-porous regions (75), the width (W) being measured in a direction parallel to the substrate (10) and perpendicular to the walls of the recess (50), is smaller than 40 nanometer.

2. A semiconductor device (1,2) according to claim 1, characterized in that the k- value of the non-porous regions (75) is lower than 3.9.

3. A semiconductor device (1,2) according to claim 1, characterized in that the barrier layer (85) is thinner than or equal to 5 nanometer.

4. A semiconductor device (1,2) according to claim 1, characterized in that the thickness of the barrier layer (85) is substantially uniform within the recess (50).

5. A semiconductor device (1,2) according to claim 1, characterized in that the k- value of the porous regions (25) is lower than 3.0.

6. A method of manufacturing a semiconductor device (1,2) comprising the steps of: - providing a semiconductor structure that comprises a substrate (10), a low-k precursor material layer (20) applied thereto while the precursor material is non-cured or partially-cured, the semiconductor structure being covered by a patterned photoresist layer (40), the semiconductor structure further comprising a recess (50) extending through the photoresist layer (40) at least into the low-k precursor material layer (20), the recess (50) having walls defined by the low-k precursor material layer (20); stripping the photoresist layer (40) by means of a stripping chemistry (110), the stripping chemistry (110) converting the low-k precursor material adjacent to the walls of the recess (50) into a non-curable material (75); and - curing the low-k precursor material layer (20), while the low-k precursor material layer (20) is converted into a low-k material layer (21).

7. A method according to claim 6, characterized in that the stripping chemistry (110) is substantially oxygen and fluorine and chlorine and bromine free.

8. A method according to claim 7, characterized in that the stripping chemistry (110) comprises hydrogen.

9. A method according to claim 7 or 8, characterized in that the stripping chemistry (110) comprises nitrogen.

10. A method according to claim 8 or 9, characterized in that the stripping chemistry (110) comprises an inert gas.

11. A method according to claim 10, characterized in that the inert gas comprises one or more of helium, neon and argon.

12. A method according to claim 6, characterized in that a semiconductor structure is provided with a recess (50) extending completely through the low-k precursor material layer (20).

13. A method according to claim 6, characterized in that the semiconductor structure is provided with a hard mask layer (30) in between the low-k precursor material layer (20) and the photoresist layer (40).

14. A method according to claim 6, characterized in that the method further comprises a step of applying a barrier layer (85) at least on the sidewalls of the recess (50) of the semiconductor structure.

15. A method according to claim 6, characterized in that the method further comprises a step of providing a conductor (90) in the recess (50).

16. A method according to claim 15, characterized in that the method further comprises a step of forming a capping layer (95) at least on the conductor (90).