CN1500288A - 形成绝缘体上的应变硅(ssoi)的方法及其形成的结构 - Google Patents
形成绝缘体上的应变硅(ssoi)的方法及其形成的结构 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 96
- 239000010703 silicon Substances 0.000 title claims abstract description 96
- 239000012212 insulator Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 230000004888 barrier function Effects 0.000 claims description 38
- 238000005516 engineering process Methods 0.000 claims description 37
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 23
- 238000010276 construction Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 18
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000004411 aluminium Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000001939 inductive effect Effects 0.000 abstract 3
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000010458 rotten stone Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种SOI(绝缘体上硅)结构与其制造方法,其中应变硅层(12)直接位于绝缘体层(14)上。该方法需要在应变诱发层(22)上形成硅层(12),其中应变诱发层(22)具有与硅不相同的晶格常数,使得由于与应变诱发层(22)之晶格失配而硅层(12)会有应变。由此形成的多层结构(18)接合到基底(24)上,使得绝缘层(14)在应变硅层(12)与基底(24)之间,而且使得应变硅层(12)直接接触到绝缘层(14)。然后去除掉应变诱发层(22),而产生应变的SOI之结构(10),该结构包括直接位于绝缘层(14)上的应变硅层(12),其中硅层(12)内的应变由SOI结构(10)保持。
Description
技术领域
本发明是有关于包括一应变半导体层的集成电路(IC)的结构以及方法。更特别的是,本发明是有关于直接位于绝缘体上的应变硅层,从而产生一绝缘体上的应变硅(strained silicon-on-insulator,SSOI)结构,该结构对于制造IC器件,比如互补金属氧化物半导体(CMOS)晶体管以及其它金属氧化物半导体场效晶体管(MOSFET)的应用,是很有用的。
背景技术
应变硅CMOS基本上是指在基底上制造的CMOS器件,该基底在松弛SiGe层上具有薄的应变硅(应变Si)层。应变Si层内的电子与空穴迁移率已经显示出比体硅层还要高出很多,而且具有应变Si沟道的MOSFET已经由实验证实,与在传统(无应变)硅基底上制造的器件相比,具有更强的器件性能。潜在的性能改进包括增加器件驱动电流与互导率,以及增加调整电压、而不用牺牲掉电路速度来降低功率消耗的能力。
应变Si层是在基底上生长出来的硅所诱发出来之双轴拉伸应力的结果,该基底是用晶格常数大于硅的材料来形成。锗的晶格常数大于硅约百分之4.2,而硅-锗合金的晶格常数相对于锗的浓度是成线性的。结果,包含五十原子百分比之锗的SiGe合金,其晶格常数是硅之晶格常数的大约1.02倍。在这种SiGe基底上外延生成出硅是会产生拉伸应变下的硅层,具有底下基本上是没有应变或″松弛″的SiGe基底。用于MOSFET的,实现了应变Si沟道结构之优点的结构与方法在授予Chu等人的共同转让的美国专利6,059,895中有教导,该专利揭示出一种技术,用于形成在SiGe层上具有应变Si沟道的CMOS器件,且都是在绝缘基底上。
完全实现应变硅CMOS技术的困难是有松弛的SiGe层在应变Si层底下出现。该SiGe层会与各种处理步骤,比如热氧化、自对准硅化(salicide)之形成与退火,相互作用,使得在CMOS制造期间很难保持住材料的完整性,而且最后可能会限制器件性能的增强以及能达到的器件生产率。另一缺点是,SiGe层会增加MOSFET本体区的总厚度。增加的厚度对于绝缘体上硅(SOI)的FET结构来说特别的不合人意,因为它会阻碍形成非常薄SOI器件的能力,而非常薄SOI器件作为用于非常短沟道长度之MOSFET结构的优点已经有详细的文献说明。因此,可以利用不包括应变诱发层但是具有直接位于另一层比如绝缘层上之应变Si层以产生应变Si结构的应变Si结构,来实现显著的优点。然而,传统的技术是,SiGe层必须一直出现,以维持硅层内的应变,因为在随后处理时暴露到升高的温度中,会产生除掉未支撑之应变Si层内的应变的效果。
发明内容
本发明提供一种SOI结构以及制造该结构的方法,其中应变硅层是直接位于绝缘层上。如此,本发明能克服现有技术中要求在绝缘基底上的应变Si结构必须包括应变Si层与绝缘层之间的应变诱发(比如SiGe)层的缺点。本发明的方法一般是指在应变诱发层上形成硅层,以便形成多层结构,其中应变诱发层具有与硅不相同的晶格常数,使得应变诱发层会因晶格失配的结果而诱发出硅层内的应变。然后将多层结构接合到基底上,使得绝缘层位于应变硅层与基底之间,而且应变硅层会直接接触到绝缘层。为此,绝缘层可以提供在基底上或是在与应变诱发层相反侧的应变硅层表面上。然后去除掉应变诱发层,产生绝缘体上应变硅(SSOI)结构,该结构包括绝缘层上的应变硅层,而绝缘层是位于基底与应变硅层之间。结果是,最后的SSOI结构并不包括额外的应变诱发层。而是,本发明所依据的决定是,对已经在硅层内被诱发出来的应变,在本质上可以用不具有诱发应变的与硅的晶格失配之基底来保持住。SSOI结构中,绝缘层(单独或是结合基底一起)在某些方面能以物理的方式阻碍应变硅层的松弛。
依据本发明,最后的SSOI结构是特别的适用于IC器件的半导体基底。为此,源极区与漏极区是在应变硅层的表面内形成的,而硅层定义源极区与漏极区之间的沟道。作为制造SSOI结构之方法的结果是,应变Si沟道会直接接触到绝缘层。通过去除掉应变Si沟道底下的应变诱发层,本发明使得应变Si之CMOS技术的优点更加完全地实现。例如,去除掉应变诱发层(比如SiGe)会减少MOSFET器件的总厚度,并避免与不同的处理步骤发生相互作用,使得材料整体性在CMOS制程中能保持住。
本发明的其它目的与优点将从以下的详细说明中变得更能被了解。
附图说明
图1表示依据本发明形成绝缘体上应变硅(SSOI)结构的几个不同技术。
图2与3显出二种利用图1的SSOI结构的MOSFET应用。
具体实施方式
图1表示出本发明范围内的工艺,其中多层结构16可以形成,在该结构中应变硅(应变Si)层12是直接位于绝缘体层14上,使得结构16能被进一步的处理,产生绝缘体上应变硅(SSOI)结构10,该SSOI结构适合制造MOSFET或其它IC器件,比如图2所示的。图1显示出四种不同技术(“不同技术”(A)、(B)、(C)与(D)),用于图1所示第一处理步骤。在图1所示的每个方法中,多层结构会被接合到基底上,使得绝缘体14是位于应变Si层12与基底之间,而且应变Si层12是直接接触到绝缘体14。尽管以下将显示并讨论四种技术,但是可以预见的是,可以设计并使用其它技术,来产生图1的中间多层结构16,而且这种修改是在本发明的范围内。此外,尽管图1与2显示出包括有限层数的多层结构,熟知该技术的人士会了解到,额外的不同材料层是可以加到结构中,而在本质上不改变本发明。重要的是,图1所示的每种技术都会产生应变Si层12,该应变Si层12是被原来在Si层12内诱发出应变的层以外的层(比如14/24)所支撑。因此,额外的层是可以包括在结构16内,只要满足本发明的这种基本特性即可。这四种技术主要是在相接合的材料上不相同,比如硅对绝缘体(技术(A)),绝缘体对绝缘体(技术(B)),绝缘体对半导体(技术(C))或半导体对半导体(技术(D))。
图1的技术(A)表示多层结构16是将一对结构18与20接合在一起所制造出来的。第一结构18包括应变Si层12,其位于松弛SiGe基底22上。基底22的功能是要诱发出双轴拉伸应力,该应力在硅层12内产生所需的应变程度,并因此能用具有与硅不相同之晶格常数的另一材料来形成。因为锗浓度与晶格常数的关系对于SiGe合金来说是线性的,所以在应变Si层12内所诱发出来的应变量是可以用SiGe合金内的锗含量来做调整。锗具有大于硅约4个百分比的晶格常数,该值因此是应变Si层12与SiGe基底22之间晶格失配的上限。据信,较佳的晶格失配是约0.2至约2个百分比,用包含有约5至约50个原子百分比之锗的SiGe合金来达成,虽然可以预见的是,可以用比较低与比较高的晶格失配。此外,大于4个百分比的晶格失配对于是用SiGe合金以外的材料来形成的基底22是可能的。
依据该领域中的已知技术,基底22最好是单晶材料,而且应变Si层12是外延生长在SiGe基底22上。SiGe基底22可以用如外延生长以及直拉(Czhochralski)生长法等的已知方法来形成,虽然其它方法是可预见的。因为SiGe基底22具有比硅更大的晶格常数,所以应变Si层12是在双轴拉伸下,而底下的SiGe基底22在本质上仍是未应变的或″松弛的″。应变Si层12的适当厚度达到约500埃,而SiGe基底的适当厚度约1000至约50000埃。
图1技术(A)的第二结构20包括基底24上的绝缘体14,该基底24至少在一开始是用作绝缘体14的操作晶片(handle wafer)。如同从以下说明中会变得明显的,可以预见的是,一个或多个不同材料的层是可以包括在绝缘体14与基底24之间,或是在基底24的背面(与绝缘体14相反)。用于绝缘体14的适当材料包括氧化硅(硅土,SiO2)、氮化硅(SiN)以及氧化铝(矾土,Al2O3),虽然可以使用其它电气绝缘(″高k值″)材料,包括氧氮化硅、氧化铪(铪土,HfO2)、氧化锆(锆土,ZrO2)以及掺杂的氧化铝。高达约一个微米的厚度据信是很适合绝缘体14的。适合基底24的材料是与该基底24在最后的SSOI结构10中发挥的作用--如果有的话--有关。如同以下将做更详细说明的,基底24后来是可以当作MOSFET器件的栅极用,使得基底24的较佳材料包括单晶硅、多晶硅、诸如钨等金属。其它用于基底24的适当材料一般是包括SOI、SiGe、GaAs与其它III-V族半导体。尽管绝缘体14与基底24的个别厚度一般对于本发明并不是很关键的,但是仍要支撑住应变Si层12(包括图1的绝缘体14与基底24)之结构的总厚度必须足够在应变Si层12内保持所需的应变程度。
图1技术(A)中,结构18与20是将应变Si层12与绝缘体14安置成相互接触,而接合在一起,然后进行该领域中已知任何适当的晶片接合技术。晶片接合技术的结果是图1所示的多层结构16,其中应变Si层12是在绝缘体14与SiGe基底22之间,使得绝缘体14有效地成为结构16内的掩埋层。然后完全去除掉SiGe基底22,最好是用如化学机械抛光(CMP)、晶片切割(wafercleaving)(比如可以从LETI取得的SmartCut处理)、对硅具有选择性的化学蚀刻处理、或结合这些技术的方法。完全去除掉SiGe基底22的较佳方法是利用选择性化学蚀刻处理,比如会优先蚀刻掉SiGe基底22的HHA(过氧化氢、氢氟酸、醋酸)蚀刻。如果是使用SmartCut处理,则可以在图1所示三个处理步骤中的不同点上,进行该处理所需的氢离子注入步骤。去除掉SiGe基底22的结果是图1所示的SSOI结构10,该结构是显示成只包括应变Si层12、绝缘体14与基底24,但是如上所述的是,在绝缘体14与基底24之间或是在基底24的背面(与绝缘体14相反侧)可以出现一个或多个额外的层。
图1技术(B)、(C)与(D)可以使用与技术(A)相同的材料。技术(B)与技术(A)的不同点是在于绝缘体14是由应变Si层12与基底24上形成的两个别层14a与14b构成。应变Si层12上形成的层14a是可以用已知方法而热成长或沉积出来。技术(B)中,接合步骤是绝缘体对绝缘体(14a对14b)。再一次,在绝缘层14b与基底24之间或是在基底24的背面(与绝缘层14b相反侧)可以出现一个或多个额外的层。
图1技术(C)的不同点是在于,绝缘体14是完全直接在应变Si层12上生长或沉积出来的,而不是在基底24上。如此,基底24(可以包括多层的不同材料)可以是结构20的单独组成部分。技术(C)一般是代表利用绝缘体对半导体(14对24)接合操作所形成的多层结构16。
类似于技术(C),技术(D)所提供的是,绝缘体14是完全直接在应变Si层12上生长或沉积出来的,而不是在基底24上。技术(D)进一步的不同点是使用两个别层24a与24b来形成基底24,其中层24a是沉积在绝缘体14上。晶片接合操作涉及要配合层24a与24b(后者是显示成结构20的单独组成部分)使得这些层24a与24b在晶片接合后会形成基底24。层24a与24b可以用相同的材料构成,比如上述用于基底24的材料其中之一,虽然有些应用是,层24a与24b最好用不同材料来形成,比如二种或更多种的上述用于基底24的材料。如果层24a与24b是用硅来形成,则结构18与20可以用已知的硅直接接合技术而接合在一起。层24a可以利用诸如化学气相沉积(CVD)等已知方法,而沉积在绝缘体14上。
在图1所示的每个技术中,所产生的多层结构16被进一步处理,以去除掉SiGe基底22,而留下SSOI结构10。最要注意的是,本发明去除掉原来在硅层12内诱发出所需拉伸应力的基底22。依据本发明,应变Si层12内的拉伸应力是用SOI结构10保持住,更特别地说,是被绝缘体14以及可能地被基底24所保持住。基底24对保持住应变Si层12的贡献程度,是取决于绝缘体14的特点。例如,如果绝缘体14很薄,则基底24很可能会具有影响力。重要的是要注意,已经在硅层内被诱发出来的应变会被不具有诱发应变的与硅之晶格失配的基底所保持住,这种能力是不为人所知的,直到为导致了本发明的研究所确定为止。
图2与3表示本发明使其变得可能的两个SSOI MOSFET结构。图2中,SSOIMOSFET 40是通过适当地掺杂应变Si层12而定义源极区与漏极区26与28而形成的,该源极区与漏极区26与28是被源极区与漏极区26与28之间应变Si层12区域所定义之沟道30分隔开的。源极区与漏极区26与28可以用传统的n+或p+掺杂之掺杂方法来形成。然后藉沉积或生长出栅极氧化物32,紧接着形成栅极34,而形成沟道30的栅极结构,其中栅极34可以是金属、多晶硅、硅或其它适当的导体或半导体材料。形成栅极氧化物32与栅极34的适当方法在领域中是众所周知的,因此这里不做详细的说明。图2的器件中,基底24主要是当作操作晶片。相对的,图3的器件是双栅极MOSFET 50,其中基底24被构图,而形成被绝缘体14与沟道30绝缘开的第二栅极36。为承担此功能,基底24必须是用适当的如钨或另一金属之导电材料,或如硅、多晶硅等之半导体材料来形成。如图2的MOSFET 40一样,图3的双栅极MOSFET 50是可以使用已知的MOSFET工艺来制造。因为沟道30内电子与空穴会因应变Si层12而有较大的迁移率,所以与类似结构的传统MOSFET器件比较起来,图2与3中的每个器件40与50都会具有加强的性能。预期的性能改善包括增加器件的驱动电流与互导率,以及增加调整电压、而不需牺牲掉电路速度来达到减少功率消耗的能力。
本发明已经用较佳实施例的方式做了说明,但是很明显的,熟知该技术领域的人士也可以采用其它的形式。例如,可以使用不同的工艺与工艺参数,除了已显示出的以外,开始、中间与最后的多层结构都可以包含其它半导电性的及/或绝缘性的层,而且可以用适当的材料来取代所述的材料。因此,本发明的范围只受限于以下的权利要求。
Claims (27)
1.一种绝缘体上硅结构(10),包括直接在绝缘层(14)上的应变硅层(12)。
2.如权利要求1之绝缘体上硅结构(10),其中应变硅层(12)是在拉伸应变下。
3.如权利要求1之绝缘体上硅结构(10),其中绝缘层(14)是由选自二氧化硅、氮化硅、氧氮化硅、氧化铪、氧化锆、氧化铝或掺杂氧化铝的一种材料构成。
4.如权利要求1之绝缘体上硅结构(10),其中绝缘层(14)是掩埋氧化物层,该层位于应变硅层(12)与第三层(24)之间。
5.如权利要求1之绝缘体上硅结构(10),进一步包括应变硅层(12)中的源极区与漏极区(26、28),该应变硅层(12)定义了位于源极区(26、28)与漏极区(26、28)之间的沟道(30),因而定义了场效晶体管器件(40、50),该沟道(30)是直接接触到绝缘层(14)。
6.如权利要求5之绝缘体上硅结构(10),进一步包括栅极(36),该栅极(36)通过绝缘层(14)而与该沟道(30)分隔开。
7.如权利要求5之绝缘体上硅结构(10),进一步包括被沟道(30)分隔开的一对栅极(34、36)。
8.如权利要求7之绝缘体上硅结构(10),其中第一栅极(36)通过绝缘层(14)而与沟道(30)分隔开。
9.如权利要求8之绝缘体上硅结构(10),其中第二栅极(34)通过第二绝缘层(32)而与沟道(30)分隔开。
10.如权利要求1之绝缘体上硅结构(10),进一步包括半导体层(24),该半导体层(24)接触到绝缘层(14),并通过绝缘层(14)而与应变硅层(12)分隔开。
11.如权利要求1之绝缘体上硅结构(10),其中所述应变硅层(12)不与具有与硅不同之晶格常数的一应变诱发层(22)接触。
12.一种形成绝缘体上应变硅结构(10)的方法,该方法包括的步骤有:
在应变诱发层(22)上形成硅层(12),以便形成多层结构(18),应变诱发层(22)具有与硅不相同的晶格常数,使得硅层(12)会因与应变诱发层(22)之间的晶格失配而具有应变;
将多层结构(18)接合到基底(24),使得一绝缘层(14)位于应变硅层(12)与基底(24)之间,应变硅层(12)直接接触到绝缘层(14);以及接着
去除掉应变诱发层(22),将应变硅层(12)的一表面暴露出来而产生绝缘体上应变硅结构(10),该结构包括基底(24)、基底(24)上的绝缘层(14)、以及绝缘层(14)上的应变硅层(12)。
13.如权利要求12之方法,其中基底(24)是由半导体材料形成的。
14.如权利要求12之方法,其中应变诱发层(22)是由SiGe合金来形成,而应变硅层(12)是在拉伸应变之下。
15.如权利要求12之方法,其中SiGe合金具有与硅的晶格常数相比大出约0.2至约2个百分比的晶格常数。
16.如权利要求12之方法,其中应变硅层(12)是通过外延生长法而在应变诱发层(22)上形成的。
17.如权利要求12之方法,其中绝缘层(14)系在基底(24)上,而接合步骤包括将基底(24)的绝缘层(14)接合到多层结构(18)的应变硅层(12)上。
18.如权利要求12之方法,其中绝缘层(14b)系在基底(24)上,多层结构(16)包括应变诱发层(22)、在应变诱发层(22)上并接触到应变诱发层(22)的应变硅层(12)、以及在应变硅层(12)上的第二绝缘层(14a),而接合步骤包括将基底(24)的绝缘层(14b)接合到多层结构(18)第二绝缘层(14a)上。
19.如权利要求12之方法,其中多层结构(18)包括应变诱发层(22)、在应变诱发层(22)上并接触到应变诱发层(22)的应变硅层(12)、以及在应变硅层(12)上的绝缘层(14),而接合步骤包括将多层结构(18)的绝缘层(14)接合到基底上(24)。
20.如权利要求12之方法,其中多层结构(18)包括应变诱发层(22),在应变诱发层(22)上并接触到应变诱发层(22)的应变硅层(12),应变硅层(12)上的绝缘层(14),以及绝缘层(14)上的半导体层(24a),而接合步骤包括将多层结构(18)的半导体层(24a)接合到基底(24b)上。
21.如权利要求20之方法,其中基底(24、24a、24b)是由半导体材料形成的。
22.如权利要求12之方法,其中去除步骤包括选取自化学机械抛光、晶片切割或对硅具有选择性之化学蚀刻中之一个或多个技术。
23.如权利要求12之方法,进一步包括在应变硅层(12)的表面内形成集成电路器件(40、50)之步骤。
24.如权利要求23之方法,其中形成集成电路器件(40、50)之步骤包括在应变硅层(12)表面内形成源极区与漏极区(26、28)之步骤,使得应变硅层(12)定义出位于源极区(26、28)与漏极区(26、28)之间之沟道(30),该沟道(30)直接接触到绝缘层(14)。
25.如权利要求24之方法,进一步包括使用半导体层(24)形成栅极(36),该栅极(36)通过绝缘层(14)而与沟道(30)分隔开。
26.如权利要求24之方法,进一步包括在应变硅层(12)表面上形成栅极氧化物(32)、并在该栅极氧化物(32)上形成栅极(34)之步骤。
27.如权利要求24之方法,进一步包括以下步骤:
使用半导体层(24)形成第一栅极(36),该第一栅极(36)通过绝缘层(14)而与沟道(30)分隔开;
在应变硅层(12)的表面上形成栅极氧化物(32);以及
在栅极氧化物(32)上形成第二栅极(34);
其中该方法会产生双栅极MOSFET(50)。
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CN102893373B (zh) * | 2010-05-19 | 2016-07-20 | 皇家飞利浦电子股份有限公司 | 用于生长半导体装置的复合生长衬底 |
CN102903739A (zh) * | 2012-10-19 | 2013-01-30 | 清华大学 | 具有稀土氧化物的半导体结构 |
CN102903739B (zh) * | 2012-10-19 | 2016-01-20 | 清华大学 | 具有稀土氧化物的半导体结构 |
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Publication number | Publication date |
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WO2002080241A1 (en) | 2002-10-10 |
US20020140031A1 (en) | 2002-10-03 |
JP4318093B2 (ja) | 2009-08-19 |
TWI222098B (en) | 2004-10-11 |
US6603156B2 (en) | 2003-08-05 |
CA2501580C (en) | 2008-05-13 |
KR100650418B1 (ko) | 2006-11-28 |
JP2005510039A (ja) | 2005-04-14 |
CA2501580A1 (en) | 2002-10-10 |
CN1254849C (zh) | 2006-05-03 |
EP1410428A1 (en) | 2004-04-21 |
KR20040058108A (ko) | 2004-07-03 |
MY134036A (en) | 2007-11-30 |
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