WO2007000690A1

WO2007000690A1 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

Info

Publication number: WO2007000690A1
Application number: PCT/IB2006/052013
Authority: WO
Inventors: Jan Sonsky; Philippe Meunier-Beillard; Rob Van Dalen; Marnix B. Willemsen
Original assignee: Nxp B.V.
Priority date: 2005-06-27
Filing date: 2006-06-21
Publication date: 2007-01-04
Also published as: EP1900037A1; CN101208804A; TW200705517A; JP2008544563A

Abstract

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method. The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which is provided with at least one semiconductor element, wherein in the semiconductor body (12) a semiconductor region (1) of a material comprising a mixed crystal of silicon and another group IV element is formed which semiconductor region (1,111) is buried by a silicon layer (2). According to the invention on a surface of the semiconductor body (12) a mask (3) comprising an opening (4) is provided, the semiconductor region (1,111) of the material comprising a mixed crystal of silicon and another group IV element is selectively deposited in the opening (4,44), the mask (3,33) is at least partly removed, and subsequently the silicon layer (2) is deposited uniformly on the surface of the semiconductor body (12). In this way various high-quality devices can be obtained. The semiconductor region (1,111) preferably comprises SiGe and may form part of the device (10) or may be sacrificed in order to form an insulating or conducting region in the device (10).

Description

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body of silicon which is provided with at least one semiconductor element, wherein in the semiconductor body a semiconductor region of a material comprising a mixed crystal of silicon and another group IV element is formed, which semiconductor region is buried by deposition of a silicon layer. The invention also relates to a semiconductor device obtained with such a method.

Such a method is very suitable for making semiconductor devices like a MOSFET (= Metal Oxide Semiconductor Field Effect Transistor) device or an IC (= Integrated Circuit) comprising such a transistor. However, other devices are obtainable as well by such a method.

A method as mentioned in the opening paragraph is known from the publication entitled "A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors" by Kyoung Hwan Yeo et al. that has been published in IEEE Electron Device Letters, vol. 25 no. 6, June 2004. In this publication a SiGe layer is deposited epitaxially on a semiconductor substrate and on said layer a silicon layer is deposited. A mask is provided on the silicon layer, which is provided with an opening. In the opening both the silicon layer and the SiGe layer are removed by etching. Subsequently, after removal of the mask, a further silicon layer is provided in the etched opening in the silicon and SiGe layer. In this way, a SiGe region buried by a silicon layer is obtained. The SiGe region is then removed by selective etching and replaced by an insulating material, e.g. a silicon dioxide. A transistor is then formed above two of such regions in which the SiGe has been replaced by silicon dioxide and which are separated by a silicon region. In this way a partially insulated FET is obtained and the method thus forms an attractive alternative for other SOI (Silicon on Insulator) methods and devices.

A drawback of such a method is that the device obtained often contains defects. It is therefore an object of the present invention to avoid the above drawback and to provide a method, which results in devices with low numbers of defects and which is moreover simply to apply. To achieve this, a method of the type described in the opening paragraph is characterized by the following steps: on a surface of the semiconductor body a mask comprising an opening is provided; a semiconductor region of a material comprising a mixed crystal of silicon and another group IV element is selectively deposited in the opening; the mask is at least partly removed; and subsequently a silicon layer is deposited uniformly on the surface of the semiconductor body. The present invention is based on the recognition that the defects mentioned, are caused by epitaxy of the silicon layer into an etched structure. Etching the structure results in surface irregularities and surface roughness, which results in the creation of defects during subsequent epitaxial growth on such a surface. By using a mask, e.g. of silicon dioxide, with an opening, which mask is deposited on the surface of the semiconductor body and by selectively depositing silicon into the opening, etching of the semiconductor body is avoided. The mask can very easily be removed, e.g. by etching, which can be done easily and selectively towards the semiconductor body. Thus in this etching step the creation of surface irregularities and surface roughness is largely avoided. After the removal of the mask, the semiconductor region is covered by a silicon layer by uniformly depositing such a layer, e.g. by epitaxy. Since such a deposition is on a very smooth and defect free surface, the deposition does not result in the creation of defects. Removal of the semiconductor region as a sacrificial layer and replacement thereof by e.g. silicon dioxide may further easily be accomplished.

Preferably the resulting structure comprising the semiconductor region buried by a silicon layer is planarized. In this way, conventional further processing of the structure is more easily accomplished. The advantage of the planarizing step is larger if the thickness of the semiconductor region is relatively large.

In a preferred modification, after selective deposition of the semiconductor region, a silicon region is selectively deposited in the opening of the mask. In this way the semiconductor region is protected by a silicon region during subsequent processing. In addition such a silicon layer favors the subsequent selective deposition in the opening of the mask of a further semiconductor region comprising for example SiGe.

In a preferred embodiment of the method according to the latter modification a further semiconductor region of a material comprising a mixed crystal of silicon and another group IV element buried by silicon is formed, at a higher level than the semiconductor region and in a similar way as the semiconductor region has been formed. In this way, the method according to the invention allows for the realization of 3-d structures in which overlying semiconductor regions can be used as sacrificial region in the making of 3-d device structures.

Making the further semiconductor region in a similar way as the semiconductor region can be accomplished in two different ways. Firstly, the further semiconductor region(s) - preferably separated from each other by silicon layers - are all deposited, preferably within one single deposition process, within the opening of the mask. Thus, in that case all semiconductor regions are viewed in projection coincide each other. However, in a further preferred modification, the further semiconductor region(s) are formed in separate deposition processes/steps. This has the important advantage that the semiconductor regions do not need to coincide but may be positioned quite differently viewed in projection. Preferably the semiconductor regions are positioned such that they at most partly overlap each other. In this way many different 3-d device structures are easily obtainable.

In growing such a stack of semiconductor regions, the growth of each semiconductor region is preferably followed by the uniform growth of a silicon layer, which buries the semiconductor region in question. The planarization step may be accomplished after each set of depositions comprising deposition of a semiconductor region and deposition of a burying silicon layer, however, the planarization step is preferably performed only once at the end of the total growth/deposition process. The further semiconductor region advantageously also is a SiGe region.

In a favorable embodiment in the surface of the semiconductor body a hole is formed that reaches the semiconductor region and the material comprising the mixed crystal of silicon and the other group IV element is removed by selective etching resulting in a cavity at the location of the semiconductor region. This sacrificial use of the buried semiconductor region of e.g. SiGe offers interesting possibilities for device structuring.

In a first modification the hole and the cavity are filled with an electrically insulating material. This allows for several device structures.

In a first structure the semiconductor element is formed in a silicon part of the semiconductor body, which is surrounded by the filled hole and is situated above the filled cavity. In this way the semiconductor element is completely electrically isolated from the remainder of the semiconductor body. A preferred semiconductor element in such a structure is a high- voltage field effect transistor for which such an isolation structure is very beneficial.

Other structures are those in which one or more filled cavities are positioned below the gate of a field effect transistor. In this way, partially or iully depleted SOI-CMOS devices are obtainable.

Also in 3-d stacks of one ore more semiconductor elements, the use of a cavity filled with insulating material can be useful, e.g. to isolate semiconductor elements or parts thereof in the stack from each other.

In a second modification the cavity is filled with an electrically conducting material. This again offers interesting device possibilities, like the use of such a cavity as the gate electrode in a field effect transistor or in a stack of field effect transistors positioned on top of each other. Also a single field effect transistor may be provided advantageously in this manner with two gate electrodes.

From the above it will be clear that also combining the use of a cavity filled with an insulating material and the use of a cavity filled with a conducting material is possible. These possibilities stem from the fact that all semiconductor regions of e.g. SiGe can be reached by separately made holes in the surface of the semiconductor body, the e.g. SiGe material thereof can be removed in separate etching steps and the resulting cavities can be filled in separate deposition steps. In another attractive embodiment, the e.g. SiGe regions are not used as sacrificial layers but as part of the device structure more in particular as parts of the semiconductor element. In such a device, the SiGe regions are preferably made in the form of coupled quantum wells. In this way, an infrared detector can be obtained comprising the coupled quantum wells that are contacted separately by semiconducting regions sunken in the surface of the semiconductor body.

From the above it is clear that preferably the silicon layer(s) and the semiconductor region(s) of the material comprising the mixed crystal of silicon and another group IV element are formed by epitaxy. Although the preferred other group IV element is Germanium, other elements are feasible. E.g. SiC could be used as the material of one ore more of the (further) semiconductor regions.

In the case of SiGe region(s) the thickness of the semiconductor region(s) is preferably chosen between 5 and 50 nm and the Germanium content thereof is preferably chosen between 20 and 40 at. %. In this way, selective etching is most easily obtained on the one hand and on the other hand avoiding the creation of defects by the strain induced by the lattice mismatch, is still possible.

A preferred material for the mask is silicon dioxide. In this way, a selective deposition process is more easily realized. Parts of the mask may be left after formation of the SiGe region and a protecting silicon layer on top thereof, e.g. to offer the possibility of holes in the surface of the semiconductor body and towards the semiconductor region by selective etching of such a remaining mask part. However, preferably the mask is removed completely.

In order to have epitaxial layers with optimal quality, preferably after removal of the mask and before the deposition of the silicon layer, the device is subjected to a thermal treatment in a hydrogen atmosphere, preferably at a temperature above 850°C. In this way, the presence of oxygen atoms at the growth interface is avoided as good as possible.

Finally, it is to be noted that the invention also comprises a semiconductor device obtained by a method according to the invention.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter, to be read in conjunction with the drawing, in which Figs. IA through 1OC are views of a first semiconductor device at various stages in its manufacture by means of a first embodiment of a method in accordance with the invention, wherein the A Figure is a top view, the B Figure is a sectional view along the line B-B in the A Figure and the C Figure is a sectional view along the line C-C in the A Figure, Figs. 1 IA through 16B are sectional views of a second semiconductor device at various stages in its manufacture by means of a second embodiment of a method in accordance with the invention, wherein the A Figure is a top view and the B Figure is a sectional view along the line B-B in the A Figure,

Figs. 17 through 25 are sectional views of a third semiconductor device at various stages in its manufacture by means of a third embodiment of a method in accordance with the invention,

Figs. 26 through 30 are sectional views of a fourth semiconductor device at various stages in its manufacture by means of a fourth embodiment of a method in accordance with the invention, and Figs. 31 A through 33B are views of a fifth semiconductor device at various stages in its manufacture by means of a fifth embodiment of a method in accordance with the invention, Figs. 3 IA-H and 33 A-B being sectional views and Fig. 32 being a 3-d top view.

The Figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various Figures. Figs. IA through 1OC are views of a first semiconductor device at various stages in its manufacture by means of a first embodiment of a method in accordance with the invention, wherein the A Figure is a top view, the B Figure is a sectional view along the line B-B in the A Figure and the C Figure is a sectional view along the line C-C in the A Figure. The semiconductor device manufactured in this example is a field effect transistor with a dual gate structure. In a first step of the manufacture of device 10 (see Figs. IA, IB and 1C) a substrate 11, here of silicon, is provided with a mask 3 provided with an opening 4. The mask 3 in this example is made of silicon dioxide and is formed by depositing a uniform layer by means of CVD (= Chemical Vapor Deposition), which subsequently is patterned using photolithography and etching. Next (see Figs. 2A, 2B and 2C) a semiconductor region 1 is formed by means of selective epitaxy, which region 1 in this example is made of SiGe with a thickness of 20 nm and a Germanium content of 20 at.%. In the same way, a silicon region 5 is formed and provided with, for example, a thickness of 10 nm and on top of this region 5 a further semiconductor region 6 of SiGe is formed with preferably the same properties as the semiconductor region 1.

Subsequently (see Figs. 3A, 3B and 3C), the mask 3 is removed by selective etching, e.g. in a diluted HF solution. The device 10 is then subjected to a thermal treatment, e.g. at 900 ⁰C and in a hydrogen ambient.

Then (see Figs. 4 A, 4B and 4C) a uniform silicon layer 2 is deposited over the selectively grown structure followed by a planarization step, e.g. using CMP (= Chemical Mechanical Polishing). The latter is done in this example such that the further SiGe region 6 is sunken in the silicon layer 2.

Next (see Figs. 5 A, 5B and 5C) a pad oxide layer 13 of a thermal oxide and a silicon nitride layer 14 are deposited on the device 10, the latter using CVD and with a thickness of, for example, 10 nm and 115 nm respectively. Therein, a pattern is formed by means of photolithography and etching in order to form a trench region 15 which is etched selective towards SiGe but will laterally surround both the lower and upper SiGe regions 1, 6 as well as the intermediate silicon region 5. Then the trench region 15 is filled with an isolating material, e.g. with silicon dioxide which is deposited uniformly by CVD followed by a planarization step and in this way STI (= Shallow Trench Isolation) region 15 is formed.

Subsequently (see Figs. 6A, 6B and 6C) a contact opening 16 is formed in the device by means of photolithography and etching. The contact opening 16 reaches as far as the lower SiGe region 1 of the SiGe/Si/SiGe stack 1, 5, 6.

Hereinafter (see Figs. 7 A, 7B and 7C) the SiGe of the SiGe regions 1, 6 is removed by means of selective isotropic etching using an etchant comprising CF₄ and O₂. This results in the formation of two cavities 8, 9 at the locations of the semiconductor regions 1, 6. Next (see Figs. 8 A, 8B and 8C) the walls of the cavities 8, 9 are provided with gate oxide layers 8 A, 9 A that are formed by means of a thermal oxidation in an oxygen ambient. Also another insulating material (such as high-k) can be deposited by sufficiently conformal techniques such as Atomic Layer CVD (ALCVD).

Hereinafter (see Fig. 9) the cavities 8, 9 are filled with a conducting material, in this example polycrystalline silicon formed by CVD. On the surface of the device 10 a polycrystalline silicon contact region 17 is formed by means of photolithography and etching.

Then (see Figs. 1OA, 1OB and 10C) the hard mask comprising layers 13, 14 are removed and source and drain regions 20, 21 are formed by means of implantation. In this way, a FET (=Field Effect Transistor) as the semiconductor element in the device 10 is obtained, having a dual gate structure 8B, 9B with a common electrical connection, which gates 8B, 9B are separated through gate oxides 8A, 9A from a channel region 22. In forming the source and drain regions 20, 21 it is avoided that the channel region 22 is contaminated by the required implantation in that a surface part of the semiconductor body 12 at the locations of the source and drain regions 20, 21 is removed by etching. This however is not shown in the drawing.

Figs. 1 IA through 16B are sectional views of a second semiconductor device at various stages in its manufacture by means of a second embodiment of a method in accordance with the invention, wherein the A Figure is a top view and the B Figure is a sectional view along the line B-B in the A Figure. The semiconductor device manufactured in this example is stack of three field effect transistors.

In a first set of steps of the manufacture of device 10 (see Figs. 1 IA and 1 IB) a semiconductor body 12 is provided with 6 SiGe regions 31, 31, 32, 33, 34, 35, 36 each of these regions being comparable with respect to thickness and composition with the SiGe regions 1, 6 of the previous example. Each of these regions 31-36 is formed in a separate growth process using a silicon dioxide mask as in the previous example provided with an opening in which opening the SiGe region in question is deposited. Each time a silicon cover region is formed in the same process on top of the SiGe region in question which is comparable with silicon region 5 of the previous example. To be accurate, the silicon region deposited on top of SiGe region 34 should be thicker (approximately two times) in comparison with the silicon region deposited on top of the SiGe region 31. The reason for this is to make sure that the thin silicon region between e.g. SiGe regions 31 and 35 is completely replaced with oxide during oxidation of a later formed cavity in region 35, while the silicon region between e.g. SiGe regions 34 and 31 is sufficiently thick, so that there is sufficient layer of silicon left to form the transistor channel even after oxidizing the cavity of region 34. The masks used for forming the SiGe regions 31-36 are chosen such that these form gate regions 31, 32, 33 and isolation plane regions 34, 35, 36, each viewed in projection overlapping each other. The isolation plane regions 34-36 lying mainly outside the gate regions 31 -33, the latter having contact regions 3 IA, 32A, 33 A being positioned at different locations. After each growth process the mask used is removed and a new mask is formed and patterned for the next growth process. In this example the burying silicon layer 2 is formed after each growth process, however it is possible and more simple to grow one single burying silicon layer 2 after formation of the last gate region 33, followed by one single planarization step.

Next (see Figs. 12A and 12B) holes 40 are etched reaching through the isolation plane regions 34-36 followed by removal of the corresponding SiGe regions by means of selective isotropic etching as in the previous example.

Subsequently (see Figs. 13A and 13B) the isolation plane regions 34-36 are filled with an insulating material 41 in this example by using a thermal oxidation in oxygen containing atmosphere.

Next (see Figs. 14A and 14B) contact holes 3 IB, 32B, 33B are formed in the contact regions 31A-33A of the gate regions 31-33 followed by (see Figs. 15A and 15B) selective isotropic SiGe etching by which cavities are formed at the locations of the gate regions 31-33. The walls of these cavities are provided with a gate dielectric in this example, as in the previous one, formed by a thin thermal oxide and are then filled with a conducting material as in the previous example comprising poly-Si.

Finally (see Figs. 16A and 16B) source and drain regions 20, 21 are shown of the individual transistor that may be formed e.g. by implantation. It is to be noted that these regions 20, 21 already have been formed at an earlier stage of the manufacturing, i.e. by implantations after growth of each layer 31, 32, 33. In an alternative favorable method these heavily doped regions, are made by a growth process, e.g. after growing region 31, the following overgrowing (thin) silicon region could be heavily doped with P++ or N++, the part above region 31 being removed afterwards by means of a planarization step.

Figs. 17 through 25 are sectional views of a third semiconductor device at various stages in its manufacture by means of a third embodiment of a method in accordance with the invention. The semiconductor device manufactured in this example is a high voltage field effect transistor with complete dielectric isolation. In a first step of the manufacture of device 10 (see Fig. 17) a substrate 11, here of silicon, is provided with a mask 3 provided with an opening 4. The mask 3 in this example is made of silicon dioxide and is formed by depositing a uniform layer by means of CVD, which is subsequently patterned using photolithography and etching.

Next (see Fig. 18) a semiconductor region 1 is formed by means of selective epitaxy, which region 1 is made of SiGe in this example with a thickness of 20 nm and a Germanium content of 20 at.%.

Subsequently (see Fig. 19), the mask 3 is removed by selective etching, e.g. in a diluted HF solution. The device 10 is then subjected to a thermal treatment, e.g. at 900 ⁰C in a hydrogen ambient. Then (see Fig. 20) a uniform silicon layer 2 is deposited over the selectively grown structure followed by a planarization step, e.g. using CMP.

Next (see Fig. 21) a pad oxide layer 13 of a thermal oxide and a silicon nitride layer 14 are deposited on the device 10, the latter using CVD and for example with a thickness of 10 nm and 115 nm respectively. Therein, a pattern is formed by means of photolithography and etching in order to form trench regions 15 which are formed by means of etching of silicon selectively with respect to SiGe, for example using an etchant comprising HBr. The trench regions 15 run all perpendicular to the plane of the drawing. Then (see Fig. 22) the SiGe region 1 is removed by selective etching, using the same selective and isotropic etchant as in the previous examples and resulting in a cavity IA at the location of the SiGe region 1.

Subsequently (see Fig. 23) the cavity IA is filled with an insulating material like silicon dioxide e.g. by means of thermal oxidation as in the previous examples. At this stage other trenches may be etched similar to the trenches 15 but now running parallel to the plane of the drawing.

Then (see Fig. 24) the last mentioned trenches - not shown in the drawing - and the trenches 15 are filled with an isolating material, e.g. with silicon dioxide which is deposited uniformly by CVD followed by a planarization step and in this way STI (= Shallow Trench Isolation) regions 15A are formed that surround islands of the silicon layer 2 on top of the buried insulating region IA.

Finally (see Fig. 25) the hard mask comprising layers 13, 14 are removed and the semiconductor element - not shown in the drawing - and in this example comprising a high- voltage FET is formed in one or more of the islands 2 of silicon. The manufacture of the semiconductor element in this merely comprises conventional steps and therefore is not further elucidated. Source and drain regions 20, 21 are formed by means of implantation. In this way, a device 10 with high- voltage FETs is obtained which are fully electrically isolated from adjacent and subjacent parts of the semiconductor body 12. Figs. 26 through 30 are sectional views of a fourth semiconductor device at various stages in its manufacture by means of a fourth embodiment of a method in accordance with the invention. The device 10 of this example comprises a fully depleted MOSFET as the semiconductor element.

In first stage (see Fig. 26) of the manufacturing discussed here, the device 10 already comprises the SiGe region 1 as in the previous examples and which is formed e.g. as discussed in the previous example with the aid of Figs. 17-21. The same reference numerals are used here as in that example.

Next (see Fig. 27) a cavity IA is formed by forming a hole in the semiconductor body 12 followed by selective etching of the SiGe region 1. Subsequently (see Fig. 28) the cavity IA is filled by an oxide layer by a thermal oxidation followed by (see Fig. 29) filling of the trenches 15 with silicon dioxide forming STI regions 15A followed by planarization and removal of the nitride layer 14. Finally (see Fig. 30) the field effect transistor F is formed with in itself usual steps. The deep source and drain regions 20, 21 are formed in the silicon region between the STI regions 15A and the buried isolation region IA.

Figs. 31 A through 33B are views of a fifth semiconductor device at various stages in its manufacture by means of a fifth embodiment of a method in accordance with the invention, Fig. 32 being a 3-d top view and Figs. 3 IA-H, 33 A and 33B being sectional views. The device here comprises an infrared detector diode comprising a number of coupled SiGe quantum-wells.

In the first steps (see Figs. 3 IA-D) a first buried semiconductor region 1 of SiGe is formed in a semiconductor body of silicon. In this device the silicon is N type doped with about 5el5 cm^"3 and the SiGe is P+ typed doped with Iel8 cm^"3, the Ge content here is about 20% and thickness about 10 nm. The thickness of the silicon layers is between 5-10 nm, as discussed in previous examples using a mask 3 with opening 4. Next (see Figs. 31D- G) further SiGe regions 111 are formed in a similar way using masks 33 with opening 44. Finally (see Fig. 31H) sunken p-type doped regions 50, 51 are formed in a conventional manner contacting the two overlapping SiGe regions 1, 111.

In a modification (see Fig. 32) with four SiGe quantum wells 1, 111, 1', 111' four contact regions 50, 51, 52, 53 are formed as sunken p-type regions 50-53. Cross-sections of this modification along the lines AA and BB are shown in Fig. 33 A and Fig. 33B respectively. Showing the 4 quantum- wells 1, 111, 1', 111' and their contact regions 50, 51, 52, 53.

It will be obvious that the invention is not limited to the examples described herein, and that within the scope of the invention many variations and modifications are possible to those skilled in the art. For example it is to be noted that the dual-gate electrodes of a MOSFET as in the first example may also be provided with separate electrical connections, also in a case in which they are still formed at the same time by small modifications in the processing.

It is further to be noted that for the insulating gate dielectric, a high-k layer can be used that is deposited through atomic layer CVD. The conductive polysilicon can be replaced with metals also deposited by atomic layer CVD etc.

The buried dielectric in the fourth embodiment maybe other dielectric than oxide, e.g. nitride and it could be also a combination of a thin oxide and semi- insulating material like SIPOS to create extra stress in the silicon channel above etc. Furthermore it is noted that in case the cavity formed at the location of the semiconductor region is filled with a conducting material, a conducting compound and in particular a metal form attractive choices. In case the cavity is filled with an electrically insulating material, also a high-k material may advantageously be selected.

Claims

CLAIMS:

1. Method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon, which is provided with at least one semiconductor element, wherein in the semiconductor body (12) a semiconductor region (1) of a material comprising a mixed crystal of silicon and another group IV element is formed, which semiconductor region (1) is buried by a silicon layer (2), the method being characterized by the following steps of: providing a mask (3) comprising an opening (4) on a surface of the semiconductor body (12), forming the semiconductor region (1) of a material comprising a mixed crystal of silicon and another group IV element by selective deposition in the opening (4), removing the mask (3) at least partly, and depositing a silicon layer (2) on the surface of the semiconductor body (12).

2. Method according to claim 1, characterized in that the resulting structure is planarized.

3. Method according to claim 1, characterized in that after selective deposition of the semiconductor region (1) a silicon region (5) is selectively deposited in the opening (4) of the mask (3).

4. Method according to claim 1, characterized in that in the semiconductor body (12) a further semiconductor region (6) of a material comprising a mixed crystal of silicon and another group IV element buried by silicon is formed above the semiconductor region

(1).

5. Method according to claim 4, characterized in that the semiconductor region and the further semiconductor region viewed in projection at most partly overlap each other.

6. Method according to claim 1 , characterized in that in the surface of the semiconductor body a hole is formed that reaches the semiconductor region and the material comprising the mixed crystal of silicon and the other group IV element is removed by selective etching resulting in a cavity at the location of the semiconductor region.

7. Method according to claim 6, characterized in that the hole and the cavity are filled with an electrically insulating material.

8. Method according to claim 7, characterized in that the semiconductor element is formed in a silicon part of the semiconductor body which is surrounded by the filled hole and is situated above the filled cavity.

9. Method according to claim 6, characterized in that the cavity is filled with an electrically conducting material.

10. Method according to claim 9, wherein the semiconductor element is a field effect transistor, characterized in that the filled cavity forms a gate electrode of the field effect transistor.

11. Method according to claim 10, characterized in that the field effect transistor is provided with a further gate electrode which is formed at a higher level than the gate electrode and is formed in the same way as the gate electrode.

12. Method according to claim 6, characterized in that a stack of field effect transistors is formed by a stack of semiconductor regions and further semiconductor regions of which alternating one is replaced by an insulating material and the other is replaced by a conducting material.

13. Method according to claims 4 or 5, characterized in that the semiconductor region and the further semiconductor regions are made in the form of coupled quantum wells.

14. Method according to claim 13, characterized in that the semiconductor element is formed as an infra-red detector comprising the coupled quantum wells that are contacted separately by semiconducting regions sunken in the surface of the semiconductor body.

15. Method according to claim 7, wherein the semiconductor element is a field effect transistor, characterized in that the filled cavity forms an insulating region that separates the channel region of the transistor from the substrate.

16. Method according to claim 1, characterized in that the silicon layer(s) and the semiconductor region(s) of the material comprising the mixed crystal of silicon and another group IV element are formed by epitaxy.

17. Method according claim 1, characterized in that for another group IV element Germanium is chosen.

18. Method according to claim 16, characterized in that the thickness of the semiconductor region(s) is chosen between 5 and 50 nm and the Germanium content thereof is chosen between 20 and 40 at. %.

19. Method according to claim 1, characterized in that the mask is formed of silicon dioxide.

20. Method according to claim 1, characterized in that the mask is removed completely.

21. Method according to claim 1 , characterized in that after removal of the mask and before the deposition of the silicon layer, the device is subjected to a thermal treatment in a hydrogen atmosphere, preferably at a temperature above 850°C.

22. Semiconductor device obtained by a method according to any one of the preceding claims.