CN101208804A - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method - Google Patents

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method Download PDF

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CN101208804A
CN101208804A CNA2006800231851A CN200680023185A CN101208804A CN 101208804 A CN101208804 A CN 101208804A CN A2006800231851 A CNA2006800231851 A CN A2006800231851A CN 200680023185 A CN200680023185 A CN 200680023185A CN 101208804 A CN101208804 A CN 101208804A
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semiconductor
silicon
semiconductor regions
regions
mask
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简·雄斯基
菲利浦·默尼耶-贝拉德
罗布·范达伦
马尼克斯·B·威廉森
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/1812—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only AIVBIV alloys, e.g. SiGe

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  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method. The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which is provided with at least one semiconductor element, wherein in the semiconductor body (12) a semiconductor region (1) of a material comprising a mixed crystal of silicon and another group IV element is formed which semiconductor region (1,111) is buried by a silicon layer (2). According to the invention on a surface of the semiconductor body (12) a mask (3) comprising an opening (4) is provided, the semiconductor region (1,111) of the material comprising a mixed crystal of silicon and another group IV element is selectively deposited in the opening (4,44), the mask (3,33) is at least partly removed, and subsequently the silicon layer (2) is deposited uniformly on the surface of the semiconductor body (12). In this way various high-quality devices can be obtained. The semiconductor region (1,111) preferably comprises SiGe and may form part of the device (10) or may be sacrificed in order to form an insulating or conducting region in the device (10).

Description

Make the method for semiconductor device and the semiconductor device that obtains with this method
Technical field
The present invention relates to the method that a kind of manufacturing has the semiconductor device of substrate and silicon semiconductor body, at least one semiconductor element is set in the silicon semiconductor body, wherein in semiconductor body, form the semiconductor regions of the material of the mixed crystal that comprises silicon and another IV family element, come buried semiconductor region by the deposition silicon layer.The invention still further relates to the semiconductor device that obtains with this method.
Described method is fit to the semiconductor device of manufacturing MOSFET (being mos field effect transistor) device and so on or comprises the IC (being integrated circuit) of this transistorlike very much.Yet other devices also can obtain in this way.
Background technology
Method that beginning is mentioned in the paragraph can be disclosed from the 25th the 6th phase of volume of IEEE Electron DeviceLetters in June, 2004, people's such as Kyoung Hwan Yeo title knows for the open file of " APartially Insulated Field-Effect Transistor (PiFET) ".In the disclosure file, the epitaxial deposition of SiGe layer is on Semiconductor substrate, and silicon-containing layer deposition is on described layer.Mask with opening is set on silicon layer.In opening, remove silicon layer and SiGe layer by etching.Then, after removing mask, the etching openings place in silicon and SiGe layer is provided with another silicon layer.Thus, obtained the SiGe zone of being buried by silicon layer.Then, for example silicon dioxide replacement of material is removed and is insulated in this SiGe zone by selective etch.Then, therein SiGe replaced by silicon dioxide and two this zones of being separated by silicon area on form transistor.Therefore can obtain the FET of SI semi-insulation thus, and this method becomes the attractive alternative of other SOI (silicon-on-insulator) method and device.
The shortcoming of this method is that the device that is obtained usually comprises defective.
Summary of the invention
Therefore, the objective of the invention is to avoid above-mentioned shortcoming and a kind of device of the defective that causes smaller amounts and the method for easier application are provided.
In order to achieve this end, those class methods of describing in the beginning paragraph are characterised in that following steps: the mask that comprises opening is set on the surface at semiconductor body; Selective deposition comprises the semiconductor regions of material of the mixed crystal of silicon and another IV family element in opening; Remove described mask to small part; Then on described semiconductor body surface, deposit silicon layer equably.The present invention is based on following understanding: described defective is produced by silicon epitaxial layers in etched structure.This structure of etching causes the coarse of surperficial scrambling and surface, and causes producing defective during described lip-deep epitaxial growth subsequently.Have the mask of for example silicon dioxide composition of opening by use, and by selective deposition silicon in opening, can avoid the etching semiconductor body, described mask is deposited on the surface of semiconductor body.This mask for example can be easy to remove by etching, and this can be easily, semiconductor body is optionally realized.Therefore in this etched step, avoid producing the coarse of surperficial scrambling and surface significantly.After removing mask,, for example, make this silicon layer evenly cover this semiconductor regions by extension by the uniform deposition silicon layer.Because this being deposited on the very level and smooth flawless surface be not so can cause generation of defects.Further, can easily realize removing as the semiconductor regions of sacrifice layer and by for example silicon dioxide replacement.
Preferably, comprise that the structure that is obtained of the semiconductor regions of being buried by silicon layer is flattened.Thus, easier realization is to the further processing of the routine of this structure.If the thickness of this semiconductor regions is bigger, then the advantage of planarization steps is bigger.
In preferred the modification, behind the selective deposition semiconductor regions, selective deposition silicon area in the opening of mask.Thus, during with reprocessing, protect this semiconductor regions by silicon area.In addition, this silicon layer helps optionally depositing another semiconductor regions subsequently in the opening of mask, and described another semiconductor regions comprises for example SiGe.
In preferred embodiment according to the method for latter modification, in the aspect higher than described semiconductor regions, and according to the similar method of established semiconductor regions, form another semiconductor regions of the material of the mixed crystal that comprises silicon and another IV family element of burying by silicon.Thus, the method according to this invention allows to realize the 3-d structure, wherein is positioned at top semiconductor regions can be used as sacrifice when making the device of 3-d structure zone.
Can realize according to making another semiconductor regions according to two kinds of diverse ways with the similar mode of described semiconductor regions.At first, preferably, in single deposition step, all other semiconductor regions (or a plurality of semiconductor regions) of deposition in the opening of mask, preferentially, other semiconductor regions is separated each other by silicon layer.Therefore, under described situation, all semiconductor regions are seen along projecting direction and are overlapped (coincide) each other.Yet, in another is preferably revised, independently forming a described other semiconductor regions (or a plurality of semiconductor regions) in the deposition processes/steps.The important advantage that this has: see that along projecting direction described semiconductor regions need not overlap, but may be positioned at very different positions.Preferably, the position of described semiconductor regions makes them overlap each other at the most.Obtain a lot of different 3-d device architectures thus easily.
When the lamination of this semiconductor regions of growth, the silicon layer of preferably behind each semiconductor regions of growth, then growing, this silicon layer is buried the semiconductor regions of being discussed.Can comprise that deposited semiconductor zone and deposition realize described planarization steps after burying the deposition of silicon layer at every group, yet, preferably, carry out only once described planarization steps at last in all growth/deposition process.Described another semiconductor regions advantageously also is the SiGe zone.
In advantageous embodiments, in the surface of semiconductor body, form the hole and extend to described semiconductor regions, and remove the material of the mixed crystal that comprises silicon and another IV family element, thereby produce cavity in the position of described semiconductor regions by selective etch.Sacrifice for example uses, and the buried semiconductor region of SiGe composition provides interested possibility as device architectureization.
In first revises, adopt electrical insulating material to fill described hole and cavity.This allows several device architectures.
In first structure, form semiconductor element in the silicon part of surrounding by the hole of having filled and be arranged in the semiconductor body on the cavity of having filled.Thus, the remainder of semiconductor element and semiconductor body electricity isolation fully.Preferred semiconductor element in this structure is a high voltage field effect transistor, and for high voltage field effect transistor, this isolation structure is very useful.
Other structures are that one of them or more cavitys of having filled are positioned at the structure below the grid of field-effect transistor.The SOI-CMOS device that thus, can obtain partially or completely to exhaust.
In the 3-d of one or more semiconductor elements lamination, use that the cavity of fill insulant also is very useful, for example the semiconductor element in the lamination or its part are isolated from each other.
In second revises, adopt electric conducting material to fill described cavity.This provides interested device possibility once more, as uses this cavity as in the field-effect transistor or be arranged in the gate electrode of lamination of the field-effect transistor of top of each other.In this way, single field-effect transistor also can advantageously dispose two gate electrodes.
Can be clear from foregoing: it be possible being used in combination the cavity of being filled by electric conducting material by the cavity and the use of filling insulating material.These possibilities come from the following fact: the hole of making respectively in the surface of described semiconductor body may extend to for example all semiconductor regions of SiGe composition, therefore independently can remove for example SiGe material in the etching step, and independently fill the cavity that is obtained in the deposition step.
In another attractive embodiment, for example the SiGe zone is not used as the part of described device architecture as sacrifice layer, especially is used as the part of described semiconductor element.In this device, preferably make the SiGe zone according to the form of the quantum well that is coupled.Thus, can obtain to comprise the pyroscan of the quantum well of coupling, contact quantum well respectively by semiconductor regions recessed in the semiconductor body surface.
Can be clear from foregoing: preferably, form a silicon layer (or a plurality of silicon layer) and comprise silicon and a semiconductor regions (or a plurality of semiconductor regions) of the material of the mixed crystal of another IV family element by extension.Though preferably another IV family element is a germanium, other elements also are feasible.For example SiC can be used as the material of one or more semiconductor regions (or other semiconductor regions).
Under the situation in a SiGe zone (or a plurality of SiGe zone), the thickness of preferably selecting a semiconductor regions (or a plurality of semiconductor regions) and preferably selects its Ge content between 20at.% to 40at.% between 5 to 50 nanometers.Thus, the easiest realization selective etch of one side, and the strain that still may avoid on the other hand being caused by the lattice misfit produces defective.
Described mask preferable material is a silicon dioxide.Thus, the step of easier realization selective deposition.Form the SiGe zone and after its top protectiveness silicon layer the reserve part mask so that for example by this residue mask part of selective etch, provide to be arranged in the semiconductor body surface and towards the possibility in the hole of semiconductor regions.Yet, preferably, remove mask fully.
In order to obtain the epitaxial loayer of optimum quality, preferably after removing mask and before the deposition silicon layer, this device in nitrogen atmosphere preferably in the temperature more than 850 ℃ through heat-treated.Thus, avoid oxygen atom to appear on the growth interface as far as possible well.
At last, should be noted that: the present invention also comprises the semiconductor device that obtains by the method according to this invention.
Description of drawings
From the embodiment hereinafter described that will read in conjunction with the accompanying drawings, these and other aspect of the present invention will be apparent, and will set forth these and other aspect of the present invention with reference to these embodiment, wherein
Figure 1A to 10C is by first embodiment according to method of the present invention, the view of each stage first semiconductor device in the mill, and wherein scheming A is top view, figure B is the profile along figure A center line B-B, and figure C is the profile along figure A center line C-C;
Figure 11 A to 16B is by second embodiment according to method of the present invention, the profile of each stage second semiconductor device in the mill, and wherein scheming A is top view, figure B is the profile along figure A center line B-B,
Figure 17 to 25 is by the 3rd embodiment according to method of the present invention, the profile of each stage the 3rd semiconductor device in the mill,
Figure 26 to 30 is by the 4th embodiment according to method of the present invention, the profile of each stage the 4th semiconductor device in the mill, and
Figure 31 A to 33B is by the 5th embodiment according to method of the present invention, and the view of each stage the 5th semiconductor device in the mill, Figure 31 A-H and Figure 33 A-B are that profile and Figure 32 are the 3-d top view.
Embodiment
Accompanying drawing is a schematic diagram, does not draw in proportion, for clearer and size on the exaggerative especially thickness direction.In different accompanying drawings, corresponding part is provided identical reference symbol and identical hatching usually.Figure 1A to 10C is by first embodiment according to method of the present invention, the view of each stage first semiconductor device in the mill, and wherein scheming A is top view, figure B is the profile along figure A center line B-B, and figure C is the profile along figure A center line C-C.The semiconductor device of making in this example is the field-effect transistor with double-gate structure.
In making the first step of device 10 (referring to Figure 1A, 1B and 1C), provide the mask 3 that contains opening 4 to the substrate 11 for silicon herein.Mask 3 in this example is made of silicon dioxide, and by utilizing CVD (being chemical vapour deposition (CVD)) deposition conforming layer to form, adopts photoetching and etched patternization subsequently.
Next (referring to Fig. 2 A, 2B and 2C) forms semiconductor regions 1 by selective epitaxial, should zone 1 in this example be that 20 nanometers, Ge content are that the SiGe of 20at.% constitutes by thickness.By identical mode, for example form that thickness is the silicon area 5 of 10 nanometers, and form another SiGe semiconductor regions 6 at these 5 tops, zone, preferably, another SiGe semiconductor regions 6 has the character identical with semiconductor regions 1.
(referring to Fig. 3 A, 3B and 3C) subsequently, by for example the dilution HF solution in selective etch remove mask 3.Then, device 10 in nitrogen atmosphere for example at 900 ℃ through heat-treated.
(referring to Fig. 4 A, 4B and 4C) then, next the uniform silicon layer 2 of deposition is the planarization steps of for example using CMP (chemico-mechanical polishing) on the selective growth structure.In this example, carry out planarization steps so that another SiGe zone 6 is recessed in silicon layer 2.
Next (referring to Fig. 5 A, 5B and 5C), for example pad oxide layer (the pad oxide layer) 13 and the silicon nitride layer 14 of deposition thermal oxide on device 10, deposited silicon nitride layer 14 adopts CVD, and thickness is respectively 10 nanometers and 115 nanometers.Wherein, form pattern by photoetching and etching, so that form trench region 15, the etching of this trench region 15 is selective to SiGe, but will laterally surround the SiGe zone 6 and the middle silicon area 5 on the SiGe zone 1 and the upper strata of lower floor simultaneously.
For example adopt the silicon dioxide insulator material to fill described trench region 15 then,, and form STI (shallow trench isolation from) zone 15 thus by this insulating material of CVD uniform deposition and next carry out planarization steps.
(referring to Fig. 6 A, 6B and 6C) subsequently is by photoetching be etched in the described device and form contact openings 16.The lower floor SiGe zone 1 that contact openings 16 extends until the lamination 1,5,6 of SiGe/Si/SiGe.
(referring to Fig. 7 A, 7B and 7C) comprises CF by use hereinafter 4And O 2Etchant carry out the SiGe that the selectivity isotropic etching is removed SiGe zone 1,6.This just forms two cavitys 8,9 on the position of semiconductor regions 1,6.
Next (referring to Fig. 8 A, 8B and 8C) provides gate oxide 8A, the 9A that forms by the thermal oxidation in oxygen atmosphere to the wall of cavity 8,9.Equally, by abundant conformal technique, can deposit another insulating material (for example high k) such as atomic layer CVD (ALCVD).
(referring to Fig. 9) hereinafter adopts electric conducting material cavity filling 8,9, is the polysilicon that forms by CVD in this example.On the surface of described device 10, form polysilicon contact area 17 by photoetching and etching.
(referring to Figure 10 A, 10B and 10C) then removes the hard mask that comprises layer 13,14 and passes through to inject formation source and drain region 20,21.Thus, obtain the FET (being field-effect transistor) as the semiconductor element in the device 10, this FET has double-grid structure 8B, the 9B that common electrical connects, and grid 8B, 9B separate by gate oxide 8A, 9A and channel region 22.Formation source and drain region, can avoid channel region 22 to be polluted, at 20,21 o'clock because removed the surface portion that semiconductor body 12 is positioned at source and drain region 20,21 places by etching by required injection.Yet this is not shown in figures.
Figure 11 A to 16B is by second embodiment according to method of the present invention, the profile of each stage second semiconductor device in the mill, and wherein scheming A is top view, figure B is the profile along figure A center line B-B.The semiconductor device of making in this example is the lamination of three field-effect transistors.
In first group of step (referring to Figure 11 A and 11B) of making device 10, semiconductor body 12 disposes 6 SiGe zones 31,32,33,34,35 and 36, and each zone in these zones is all suitable with the SiGe zone 1,6 in foregoing example aspect thickness and composition.Use as the aforementioned such silicon dioxide mask that disposes opening in the example, in growth step independently, form among these regional 31-36 each, in opening, deposit the SiGe zone of being discussed.Each when forming the silicon overlay area at the top, SiGe zone of being discussed in same step, this SiGe that discusses zone is suitable with silicon area 5 in foregoing example.Say exactly, should be at the silicon area of the top in SiGe zone 34 deposition than silicon area thicker (approximately twice) in the top in SiGe zone 31 deposition.Its reason is in order to ensure to the cavity in the zone 35 that forms after a while between the heat of oxidation, replace for example thin silicon zone between the SiGe zone 31 and 35 fully by oxide, for example the silicon area between SiGe zone 34 and 31 is enough thick simultaneously, so that there are enough silicon layers to stay to form transistor channel after the cavity oxidation to zone 34.Selection is used to form the mask of described SiGe zone 31-36, so that form gate region 31,32,33 and isolation plane regions 34,35,36, each is seen all along projecting direction and overlaps each other.Described isolation plane regions 34-36 mainly is positioned at the outside of described gate region 31-33, and the latter has contact area 3A, 32A, the 33A that is placed in diverse location.After each growth step, remove used mask, and be that ensuing growth step forms and the new mask of patterning.In this example, after each growth step, form and bury silicon layer 2, bury silicon layer 2 yet may grow one after in the end gate region 33 forms, and easier, carry out a planarization steps subsequently.
Next (referring to Figure 12 A and 12B), etch-hole 40 passes described isolation plane regions 34-36, subsequently as in the foregoing example, removes corresponding SiGe zone by the selectivity isotropic etching.
(referring to Figure 13 A and 13B) subsequently by using the thermal oxidation in the aerobic environment, fills described isolation plane regions 34-36 with insulating material 41 in this example.
Next (referring to Figure 14 A and 14B), in the contact area 31A-33A of gate region 31-33, form contact hole 31B, 32B, 33B, (referring to Figure 15 A and 15B) carries out selectivity isotropism SiGe etching subsequently, forms cavity thus on gate region 31-33 position.In this example,, adopt example as the aforementioned to comprise the electric conducting material filling of polysilicon like that then to the gate-dielectric that the wall of these cavitys provides example as the aforementioned to be formed by thin thermal oxide like that.
(referring to Figure 16 A and 16B) at last, showing for example can be by injecting the source and the drain region 20,21 of the single transistor that forms.It should be noted that: just formed these zones 20,21 in the earlier stage of making, just by after each layer 31,32,33 growth, injecting.In the favorable method that substitutes, make these heavily doped regions by growth step, for example after growth district 31, adopt (approaching) silicon area of P++ or N++ heavy doping undue growth subsequently, remove the part of regional 31 tops then by planarization steps.
Figure 17 to 25 is by the 3rd embodiment according to method of the present invention, the profile of each stage the 3rd semiconductor device in the mill.The semiconductor device of making in this example is the high voltage field effect transistor with complete dielectric isolation.
In the first step (referring to Figure 17) of making device 10, has the mask 3 of opening 4 here for substrate 11 configurations of silicon.In this example, mask 3 is made up of silicon dioxide, and by the CVD deposition uniformly layer form, use photoetching and etching subsequently and this mask 3 of patterning.
Next (referring to Figure 18) forms semiconductor regions 1 by selective epitaxial, should zone 1 in this example be that 20 nanometers and Ge content are that the SiGe of 20at.% forms by thickness.
(referring to Figure 19) subsequently for example removes described mask 3 by selective etch in the HF solution of dilution.Make then device 10 for example in 900 ℃ nitrogen atmosphere through heat-treated.
(referring to Figure 20) then deposits uniform silicon layer 2 on the structure of selective growth, for example use the planarization steps of CMP subsequently.
Next (referring to Figure 21), the pad oxide layer 13 and the silicon nitride layer 14 of deposition thermal oxide on device 10, the latter uses CVD, and for example thickness is respectively 10 nanometers and 115 nanometers.Wherein, form pattern,,, for example use the etchant that comprises HBr, form this trench region 15 by with respect to SiGe selective etch silicon so that form trench region 15 by photoetching and etching.Described trench region 15 fully vertically extends with the plane of accompanying drawing.
(referring to Figure 22) then, use with foregoing example in identical selectivity and isotropic etchant, remove described SiGe zone 1 by selective etch, and at the position in described SiGe zone 1 generation cavity 1A.
(referring to Figure 23) subsequently for example by such thermal oxidation in the example as described above, adopts the described cavity 1A of filling insulating material of silicon dioxide and so on.In this stage, be similar to described groove 15, other grooves of etching, but extend on the plane that is parallel to accompanying drawing now.
(referring to Figure 24) then, adopt last-mentioned groove (not shown) of filling insulating material and groove 15, for example adopt silicon dioxide by the CVD uniform deposition, carry out planarization steps subsequently, form to surround STI (be shallow trench isolation from) the district 15A of the silicon layer 2 of the island on the 1A top, buried insulation zone thus.
(referring to Figure 25) at last removes the hard mask that comprises layer 13,14, and the one or more middle semiconductor element (not shown) that forms in silicon island 2, comprises high pressure FET in this example.Make semiconductor element herein and only comprise traditional step, therefore do not further specify.By injecting formation source and drain region 20,21.Thus, obtained to have the device 10 of high pressure FET, electricity is isolated between the following adjacent part (subjacent parts) of described device and adjacent semiconductor body 12 and semiconductor body 12.
Figure 26 to 30 is by a fourth embodiment in accordance with the invention, at the sectional view of different phase the 4th semiconductor device of its manufacturing.The device 10 of this example comprises the MOSFET that exhausts fully as semiconductor element.
Herein the manufacturing phase I (referring to Figure 26) of Tao Luning, device 10 has comprised as the SiGe zone 1 in the aforesaid example, and SiGe zone 1 is for example as forming by means of Figure 17-21 discussion in the foregoing example.Used the reference symbol identical herein with foregoing example.
Next (referring to Figure 27), by form the hole in semiconductor body 12, selective etch SiGe zone 1 forms cavity 1A subsequently.
(referring to Figure 28) subsequently, by oxide layer cavity filling 1A, (referring to Figure 29) subsequently adopts silica-filled groove 15 by thermal oxidation, forms sti region 15A, carries out complanation subsequently and removes nitride layer 14.
(referring to Figure 30) at last adopts its step commonly used to form field-effect transistor F.Form deep focus and drain region 20,21 in the silicon area between sti region 15A and the area of isolation 1A that buries.
Figure 31 A to 33B is by according to a fifth embodiment of the invention, and at the view of different phase the 5th semiconductor device of its manufacturing, Figure 32 is the 3-d top view, and Figure 31 A-H, 33A and 33B are sectional views.Herein, device comprises the pyroscan diode, comprises the SiGe quantum well of a plurality of couplings.
In first step (referring to Figure 31 A-D), in silicon semiconductor body, form SiGe first buried semiconductor region 1.In this device, silicon is doped to about 5e10cm by the N type -3, and SiGe is doped to 1e18cm by the P+ type -3, Ge content is about 20%, thickness is about 10 nanometers.The thickness of silicon layer is between the 5-10 nanometer, and example is used the mask 3 with opening 4 like that as described above.Next (referring to Figure 31 D-G) uses the mask 33 with opening 44, forms other SiGe zone 111 in a comparable manner.(referring to Figure 31 H) at last forms recessed p type doped region 50,51 in the conventional mode, contacts two overlapping SiGe zones 1,111.
In adopting four SiGe quantum well 1,111,1 ', 111 ' modification (referring to Figure 32), forms four contact areas 50,51,52,53 as the regional 50-53 of recessed p type.In Figure 33 A and Figure 33 B, show the sectional view of this modification of AA along the line and line BB respectively.Show 4 quantum well 1,111,1 ', 111 ' and their contact area 50,51,52,53.
Obviously, the invention is not restricted to example described herein, and those skilled in the art may carry out many changes and modification within the scope of the invention.
For example, should be noted that: the double grid electrode of the MOSFET as in first example also can provide independently and be electrically connected, and still forms simultaneously equally in this case to be electrically connected, and has carried out little modification in processing.
Further should be noted that:, can use high-k layer by atomic layer CVD deposition for the insulated gate dielectric.Can adopt same metal to replace the polysilicon of conduction by depositions such as atomic layer CVD.
The dielectric of burying among the 4th embodiment can be a dielectric outside the oxide, nitride for example, and can be the combination of thin-oxide and semi insulating material also, as SIPOS, so as in the silicon raceway groove above wait and produce extra stress.
And, should be noted that the compound of conduction especially metal has constituted attractive selection under the situation of the cavity that forms in the position of adopting electric conducting material filling semiconductor zone.Under the situation that adopts the electrical insulating material cavity filling, also can advantageously select high k material.

Claims (22)

1. a manufacturing has the method for the semiconductor device (10) of substrate (11) and silicon semiconductor body (12), this silicon semiconductor body is provided with at least one semiconductor element in (12), wherein in semiconductor body (12), form the semiconductor regions (1) of the material of the mixed crystal that comprises silicon and another IV family element, this semiconductor regions (1) is buried by silicon layer (2), the method is characterized in that following steps:
The mask that comprises opening (4) (3) is provided on the surface of semiconductor body (12),
By selective deposition in opening (4), form the semiconductor regions (1) of the material of the mixed crystal that comprises silicon and another IV family element,
To small part removal mask (3), and
Deposition silicon layer (2) on semiconductor body (12) surface.
2. according to the method for claim 1, be characterised in that the structure that is obtained is flattened.
3. according to the method for claim 1, be characterised in that after the selective deposition of semiconductor regions (1) selective deposition silicon area (5) in the opening (4) of mask (3).
4. according to the method for claim 1, be characterised in that in semiconductor body (12), form another semiconductor regions (6) of the material of mixed crystal that bury by silicon, that comprise silicon and another IV family element in semiconductor regions (1) top.
5. according to the method for claim 4, be characterised in that along projecting direction and see that described semiconductor regions and described another semiconductor regions are overlapped at the most each other.
6. according to the method for claim 1, be characterised in that and in the surface of semiconductor body, form a hole that extends to semiconductor regions, and, remove the material of the mixed crystal that comprises silicon and another IV family element by selective etch, thereby produce cavity in the position of this semiconductor regions.
7. according to the method for claim 6, be characterised in that and adopt electrical insulating material to fill described hole and cavity.
8. according to the method for claim 7, be characterised in that in semiconductor body the silicon part of being surrounded by the hole of having filled and being arranged in above the cavity of having filled forms semiconductor element.
9. according to the method for claim 6, be characterised in that and adopt electric conducting material to fill described cavity.
10. according to the method for claim 9, wherein semiconductor element is a field-effect transistor, is characterised in that the cavity of having filled forms the gate electrode of field-effect transistor.
11., be characterised in that field-effect transistor is provided with at another gate electrode that forms than described gate electrode higher level place and form according to the mode identical with described gate electrode according to the method for claim 10.
12. method according to claim 6, be characterised in that the lamination that forms field-effect transistor by the lamination of semiconductor regions and other semiconductor regions, wherein alternately a semiconductor region is insulated that material replaces and another semiconductor region is replaced by electric conducting material.
13., be characterised in that described semiconductor regions and described other semiconductor regions form according to the form of the quantum well of coupling according to the method for claim 4 or 5.
14. according to the method for claim 13, be characterised in that this semiconductor element forms the pyroscan of the quantum well that comprises coupling, described quantum well contacts independently by semiconductor regions recessed in the semiconductor body surface.
15. according to the method for claim 7, wherein said semiconductor element is a field-effect transistor, is characterised in that the cavity of having filled forms insulating regions, this insulating regions separates transistorized channel region and substrate.
16., be characterised in that by extension to form silicon layer and comprise silicon and the semiconductor regions of the material of the mixed crystal of another IV family element according to the method for claim 1.
17., be characterised in that and select germanium as another IV family element according to the method for claim 1.
18., be characterised in that the thickness of selecting semiconductor regions between 5 to 50 nanometers, and select its Ge content between 20at.% to 40at.% according to the method for claim 16.
19., be characterised in that mask is formed by silicon dioxide according to the method for claim 1.
20., be characterised in that and remove mask fully according to the method for claim 1.
21. according to the method for claim 1, be characterised in that after removing mask and before the deposition silicon layer, described device in nitrogen atmosphere preferably in the temperature more than 850 ℃ through heat-treated.
22. by the semiconductor device that obtains according to the described method of any one claim of front.
CNA2006800231851A 2005-06-27 2006-06-21 Method of manufacturing a semiconductor device and semiconductor device obtained with such a method Pending CN101208804A (en)

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