CN1499457A - 具有优良特性的显示器件 - Google Patents

具有优良特性的显示器件 Download PDF

Info

Publication number
CN1499457A
CN1499457A CNA2003101029780A CN200310102978A CN1499457A CN 1499457 A CN1499457 A CN 1499457A CN A2003101029780 A CNA2003101029780 A CN A2003101029780A CN 200310102978 A CN200310102978 A CN 200310102978A CN 1499457 A CN1499457 A CN 1499457A
Authority
CN
China
Prior art keywords
display device
tft
crystal grain
grain boundary
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2003101029780A
Other languages
English (en)
Other versions
CN1249650C (zh
Inventor
ֱ
金沃炳
李基龙
朴志容
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung SDI Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
Publication of CN1499457A publication Critical patent/CN1499457A/zh
Application granted granted Critical
Publication of CN1249650C publication Critical patent/CN1249650C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本发明公开了一种具有优良特性的显示器件,其具有多晶硅衬底,使得Vth和迁移率特性以及亮度特性更均匀。该显示器件包括:一显示区;位于显示区中的多个第一薄膜晶体管;和位于显示区的多晶硅衬底中的主晶粒边界;其中主晶粒边界以-30°~30°的角度向自多个第一薄膜晶体管的每一个的源极流向漏极的第一电流方向倾斜。

Description

具有优良特性的显示器件
本中请要求享有2002年11月5日提交的韩国专利申请Kr2002-68232的优先权,该申请的内容在此全部引为参考。
技术领域
本发明涉及一种显示器件,尤其涉及一种具有优良的驱动特性和亮度特性的显示器件。
背景技术
在利用多晶硅制造薄膜晶体管(TFT)期间,成键缺陷,例如存在于包含在有源沟道区中的多晶硅的晶粒边界上的悬挂键,公知起着捕获电荷载流子的作用。
因此,晶粒的大小、大小均匀性、数量、位置和方向不仅对TFT特性如阈值电压(Vth)、阈下斜率、电荷载流子迁移率、漏电流以及器件的稳定性有着至关重要的直接或间接影响,而且依据在利用TFTs制造有源矩阵式显示器衬底期间晶粒的位置,这些特性也对TFTs的均匀性具有重要的影响。
根据晶粒的大小、倾斜角θ、有源沟道的尺寸(长度L和宽度W)以及每个TFT在衬底上的位置,包含在显示器件的整个衬底上的TFTs的有源沟道区中的重要晶粒边界(以下称作“主晶粒边界”)的数量可以相等或不等(图1A和图1B)。
如图1A和1B所示,如果晶粒边界的最大数量为N最大,即对于晶粒大小为Gs、有源沟道的尺寸为L×W、以及倾斜角为θ,包含在有源沟道区中的“主”晶粒边界的数量;根据TFT在衬底或显示器件上的位置,包含在有源沟道区中的“主”晶粒边界的数量将为N最大(在图1B的情形中为3)或N最大-1(图1A情形中的2),并且当对于所有的TFTs包含在有源沟道区中的“主”晶粒边界数量为N最大时,可以确保最佳TFT特性的均匀性。即,每个TFT的晶粒边界数量越相等,器件的均匀性越好。
另一方面,如果具有N最大个“主”晶粒边界的TFTs的数量等于具有N最大-1个“主”晶粒边界的TFTs的数量,则可以很容易地知道,在TFT衬底或显示器件上的TFTs的特性均匀性最差。
如图2A和图2B所示,利用连续横向凝固(sequential lateral solidification,SLS)结晶法,多晶或单晶颗粒能够在衬底上形成大的硅晶粒,并且据报道,当利用大的硅晶粒制造TFT时,获得类似于由单晶硅制得的TFTs的特性。
但是,必须制作用于驱动器和像素阵列的大量TFTs以制造有源矩阵显示器。例如,在制作具有SVGA分辨率的有源矩阵显示器时,大约要制作一百万个像素。在液晶显示器(LCD)的情形中每个像素需要一个TFT,并且在利用有机发光物质的显示器(如有机电致发光器件)中要求每个像素至少有两个或更多的TFTs。
因此,对于一百万至两百万或更多TFTs中的每一个的有源沟道区,通过只在一特定方向上生长一定数量的晶粒来制作TFTs是不可能的。
作为实现这一目标的方法,美国专利US 6,322,625中公开了一项技术,在利用PECVD、LPCVD或溅射法沉积非晶硅之后,通过SLS结晶法把整个衬底上的非晶硅转变成多晶硅,或仅使衬底上的选定区域结晶,参见图2A和2B。
与具有几微米×几微米尺寸的有源沟道区相比,选定区域也是一个相当大的区域。另外,用在SLS结晶法中的激光束的尺寸近似为几毫米×几十毫米,并且实质上要求激光束或台的步进和位移,以晶化衬底上整个区域或选定区域的非晶硅,其中存在被激光束辐射的区域之间的失准。因此,包含在TFTs的大量有源沟道区中的“主”晶粒边界的数量不等,并且整个衬底上或驱动区和像素单元区中的TFTs具有不可预测的非均匀性。这种非均匀性对于有源矩阵显示器件的实施例产生严重的不利影响。
另外,在美国专利US 6,177,391中公开了一项技术,即在制造用于LCD器件的TFT时,其中包括驱动器和像素阵列的TFT,通过利用SLS结晶法形成大的硅晶粒,如图3A所示,在有源沟道的方向平行于通过SLS结晶法生长的晶粒的方向的情形下,晶粒边界的阻挡效应在电荷载流子方向上最小。因此,可以获得次于单晶硅的TFT特性。另一方面,在有源沟道方向垂直于晶粒生长方向的情形中,如图3B所示,存在下述的晶粒边界,其中的TFT特性用于捕获电荷载流子,并且TFT特性大大地恶化。
实际上,存在这样的情形,当制造有源矩阵显示器件时位于驱动电路中的TFTs以90°的角度普遍向位于像素单元区中的TFTs倾斜,其中通过下述方式制作TFTs可改善显示器件的均匀性,即有源沟道区的方向以30~60°的角度向晶粒生长方向倾斜以提高TFTs之间的特性均匀性,当每个TFT的特性没有显著变差时,如图3C所示。
但是,也存在一种可能性,即因为该方法还利用通过SLS结晶法形成的具有有限尺寸的晶粒,所以在有源沟道区中包含主晶粒边界。因此,该方法产生的问题是:存在不可预知的不均匀性,造成TFTs之间的特性差异。
另外,随着TFT特性的改进,应该考虑的方面是用于驱动显示面板内的像素的TFTs的均匀性。
当特性根据TFT在衬底中的位置而改变时,甚至当TFT显示良好的特性时,尤其是当TFT的阈值电压即导通电压依据衬底的位置而变化时,很难实现显示器的均匀图像品质。
因此,随着一种能够增大晶粒的大小并控制晶粒的生长方向的结晶法如SLS法的开发,必须设计并制作一种适于所开发方法的TFT衬底。
发明内容
本发明旨在解决前述和/或其它问题,并且本发明的一个方面在于提供一种具有优良的驱动特性和亮度特性的显示装置。
为了实现前述和/或其它方面,本发明提供了一种具有多晶硅衬底的显示器件,其包括显示区、位于显示区中的多个第一薄膜晶体管、和位于显示区的多晶硅衬底中的主晶粒边界,其中主晶粒边界向自多个第一薄膜晶体管的每一个的源极流到漏极的第一电流方向以-30°~30°的角度倾斜。
根据本发明实施例制作的TFT通过设计TFT,在利用SLS法制作显示器阵列的驱动TFTs时使得有源沟道的方向垂直于次晶粒边界,能够使Vth和迁移率特性更均匀,并且防止了由整个显示屏上Vth的不均匀性产生的显示器件的亮度不均匀。
本发明的其它方面和/或优点在下文中部分地提出以及部分地从说明书中显而易见,或者可以从本发明的实践中得知。
附图说明
通过下面结合附图对优选实施例的详细描述,本发明的这些和/或其它方面及优点将变得更加清晰,其中:
图1A是一TFT的平面示意图,其中对于相等的晶粒大小Gs、有源沟道的尺寸为L×W时,主晶粒边界数为2;
图1B是一TFT的平面示意图,其中主晶粒边界数为3;
图2A和图2B是TFTs的有源沟道的平面示意图,其中包括通过SLS结晶法形成的、具有大晶粒尺寸的硅晶粒;
图3A~3C是根据其它现有技术制造的TFTs的有源沟道的平面示意图;
图4A是有源沟道区中的“主”晶粒边界垂直于从源极流向漏极的电流方向而分布的示意图,并且图4B是一曲线图,显示按照TFT在根据图4A中的排布制作的衬底中的位置测得的Vth曲线;和
图5A是有源沟道区中的“主”晶粒边界平行于从源极流向漏极的电流方向分布的示意图,并且图5B是一曲线图,显示按照TFT在根据图5A中的排布制作的衬底中的位置测得的Vth曲线。
具体实施方式
下面将结合附图对本发明的优选实施例进行详细解释,在附图中显示了本发明的优选实施例,其中对相同的元件一直采用相同的标记。
由于有限的晶粒大小,在相邻晶粒之间形成晶粒边界,如果多晶硅的晶粒对TFT特性有直接或间接的重要影响,则在制作用于有源矩阵显示器件的TFTs期间,晶粒尺寸大且规则化,以提高TFT的特性。
在本发明中,“晶粒大小”是指晶粒边界之间的可确定距离,并且一般地定义为属于普通误差范围的晶粒边界之间的距离。
晶粒边界通常被分为垂直于晶体生长方向而形成的“主”晶粒边界和沿晶体生长方向而形成的“次”晶粒边界。
图4A表示有源沟道区中的“主”晶粒边界垂直于从源极流向漏极的电流方向分布,图4B是表示按照TFT在根据图4A所示的排列制作的衬底中的位置测得的Vth曲线。
图5A表示有源沟道区中的“主”晶粒边界平行于从源极流向漏极的电流方向分布,图5B是表示按照TFT在根据图5A所示的排列制作的衬底中的位置测得的Vth曲线。
要确保TFTs的均匀性很困难,因为“主”晶粒边界起着电荷载流子移动的陷阱的作用,有源沟道区中的“主”晶粒边界的数量比平行于或与晶粒生长方向倾斜的“次”晶粒边界的数量少,并且在“主”晶粒边界垂直于从TFT的源极流向漏极的电流方向的情形中,依赖于有源沟道的位置,“次”晶粒边界的数量是不规律的,如图4A所示。可以看出,Vth不恒定,如图4B所示。
但是,与图5A所示的“主”晶粒边界平行于从源极流到漏极的电流方向的情形相比,电流迁移率特性优良,因为只有“主”晶粒边界起陷阱的作用,而“次”晶粒边界不起捕获流动电流的作用。
另一方面,如上所述,可以确保TFTs的均匀性,因为衬底内的有源沟道的位移(displacement)的变化性(variability)很小(即,存在着当晶粒边界数从一个变为两个时出现的变化性与当晶粒边界数从100个变为102个时出现的变化性之间的差异)。虽然电流特性较差,因为用于捕获电荷载流子的晶粒边界数增加,并且电荷载流子不得不横向穿越大量的晶粒边界(“次”晶粒边界),如图5A所示(即,在“主”晶粒边界平行于电流方向的情况下),但是TFTs的均匀性得到提高。从图5B所示的Vth曲线中可以看出,Vth保持恒定。
即,“主”晶粒边界根据晶粒边界数量的变化具有很大的电流移动变化性,而“次”晶粒边界根据晶粒边界数的变化具有较小的电流移动变化性。
因此,因为在一显示区中,即在显示器件中尤其要求TFT的均匀性的区域中,例如其中排列有像素的区域中,需要TFTs的均匀性而不是电流特性,所以根据本发明实施例的显示器件以下述方式制作,即“主”晶粒边界平行于电流的流动方向,如图5A所示。
当然,当“主”晶粒边界与电流的流动方向形成一定角度时,均匀性不会受到很大地影响,并且“主”晶粒边界向电流流动方向倾斜的角度优选从-30°到30°。
另一方面,存在能够成为势垒的晶粒边界越少,电流的迁移率越好。因此,优选以这样的方式制作一驱动区,即虽然电流的移动受到“主”晶粒边界的显著影响,但电流的流动很少受到多个“次”晶粒边界的影响,并且在驱动区中“主”晶粒边界优选以30°~150°的角度向电流的流动方向倾斜。
在一些实施例中,优选以这种方式制作驱动区,即“主”晶粒边界垂直于电流的流动方向,如图4A所示。
另一方面,用在本发明中的多晶硅衬底能够通过SLS方法在特定的方向上生长晶粒。
根据本发明实施例的前述器件可以用作半导体器件或显示器件,并且优选用作液晶显示器件或有机电致发光(EL)器件的显示器件。
根据本发明实施例制作的TFT通过设计TFT,在利用SLS法制作显示器阵列的驱动TFTs时使得有源沟道的方向垂直于次晶粒边界,能够使Vth和迁移率特性更均匀,并且防止了由整个显示屏上Vth的不均匀性产生的显示器件的亮度不均匀。
虽然以上展示并描述了本发明的几个实施例,但本领域的技术人员将会理解,在不脱离本发明实质和范围的前提下,可以改变这些实施例,本发明的保护范围由所附权利要求及其等同物限定。

Claims (11)

1.一种具有多晶硅衬底的显示器件,包括:
一显示区;
位于该显示区中的多个第一薄膜晶体管;和
位于该显示区的该多晶硅衬底中的主晶粒边界;
其中该主晶粒边界以-30°~30°的角度向自该多个第一薄膜晶体管的每一个的源极流到漏极的第一电流方向倾斜。
2.如权利要求1所述的显示器件,其中该主晶粒边界平行于该第一电流方向。
3.如权利要求2所述的显示器件,其中在该多个第一薄膜晶体管的每个的有源沟道区中存在该主晶粒边界的第一数量。
4.如权利要求1所述的显示器件,其中该显示器是一有机电致发光显示器。
5.如权利要求1所述的显示器件,其中该多晶硅衬底通过连续横向凝固(SLS)法制作。
6.如权利要求1所述的显示器件,还包括:
该显示器件的驱动区;和
位于该驱动区中的多个第二薄膜晶体管;
其中该主晶粒边界以30°~150°的角度向自该多个第二薄膜晶体管的每一个的源极流到漏极的第二电流方向倾斜。
7.如权利要求6所述的显示器件,其中该主晶粒边界垂直于该第二电流方向。
8.如权利要求7所述的显示器件,其中该多个第二薄膜晶体管的每一个的有源沟道区中存在该主晶粒边界的第二数量。
9.如权利要求6所述的显示器件,其中该显示器件是一有机电致发光显示器件。
10.如权利要求6所述的显示器件,其中该多晶硅衬底通过连续横向凝固(SLS)法制作。
11.一种具有多晶硅衬底的显示器件,包括:
驱动区;
位于该驱动区中的多个薄膜晶体管;和
位于该驱动区的该多晶硅衬底中的主晶粒边界;
其中该主晶粒边界以30°~150°的角度向自该多个薄膜晶体管的每一个的源极流到漏极的电流方向倾斜。
CNB2003101029780A 2002-11-05 2003-10-31 具有优良特性的显示器件 Expired - Lifetime CN1249650C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2002-0068232A KR100534577B1 (ko) 2002-11-05 2002-11-05 특성이 우수한 디스플레이 디바이스
KR68232/02 2002-11-05
KR68232/2002 2002-11-05

Publications (2)

Publication Number Publication Date
CN1499457A true CN1499457A (zh) 2004-05-26
CN1249650C CN1249650C (zh) 2006-04-05

Family

ID=32171613

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2003101029780A Expired - Lifetime CN1249650C (zh) 2002-11-05 2003-10-31 具有优良特性的显示器件

Country Status (4)

Country Link
US (1) US7750348B2 (zh)
JP (1) JP2004158853A (zh)
KR (1) KR100534577B1 (zh)
CN (1) CN1249650C (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI389316B (zh) * 2005-09-08 2013-03-11 Sharp Kk 薄膜電晶體、半導體裝置、顯示器、結晶化方法及製造薄膜電晶體方法
CN114270530A (zh) * 2019-08-09 2022-04-01 美光科技公司 晶体管及形成晶体管的方法
US11024736B2 (en) 2019-08-09 2021-06-01 Micron Technology, Inc. Transistor and methods of forming integrated circuitry
US11637175B2 (en) 2020-12-09 2023-04-25 Micron Technology, Inc. Vertical transistors

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3157985B2 (ja) * 1993-06-10 2001-04-23 三菱電機株式会社 薄膜トランジスタおよびその製造方法
JP3450376B2 (ja) * 1993-06-12 2003-09-22 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5640067A (en) 1995-03-24 1997-06-17 Tdk Corporation Thin film transistor, organic electroluminescence display device and manufacturing method of the same
JP3216861B2 (ja) * 1995-04-10 2001-10-09 シャープ株式会社 多結晶シリコン膜の形成方法および薄膜トランジスタの製造方法
CA2256699C (en) * 1996-05-28 2003-02-25 The Trustees Of Columbia University In The City Of New York Crystallization processing of semiconductor film regions on a substrate, and devices made therewith
JPH09321310A (ja) * 1996-05-31 1997-12-12 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3641342B2 (ja) * 1997-03-07 2005-04-20 Tdk株式会社 半導体装置及び有機elディスプレイ装置
JP3642546B2 (ja) * 1997-08-12 2005-04-27 株式会社東芝 多結晶半導体薄膜の製造方法
KR100292048B1 (ko) * 1998-06-09 2001-07-12 구본준, 론 위라하디락사 박막트랜지스터액정표시장치의제조방법
JP2000243968A (ja) * 1999-02-24 2000-09-08 Matsushita Electric Ind Co Ltd 薄膜トランジスタとその製造方法及びそれを用いた液晶表示装置とその製造方法
US6177391B1 (en) * 1999-05-27 2001-01-23 Alam Zafar One time use disposable soap and method of making
US6828587B2 (en) * 2000-06-19 2004-12-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
CN1249650C (zh) 2006-04-05
US20040085268A1 (en) 2004-05-06
KR20040039971A (ko) 2004-05-12
JP2004158853A (ja) 2004-06-03
US7750348B2 (en) 2010-07-06
KR100534577B1 (ko) 2005-12-07

Similar Documents

Publication Publication Date Title
US20030147018A1 (en) Display apparatus having polycrystalline semiconductor layer
CN1758310A (zh) 有机发光二极管显示器件
CN1249650C (zh) 具有优良特性的显示器件
US20080290344A1 (en) Image Display Device And Method For Manufacturing The Same
CN1527260A (zh) 具有薄膜晶体管的平板显示器
CN1949513A (zh) 一种单栅双沟道像素结构
CN1527405A (zh) 多晶硅薄膜、其制法以及用该膜制造的薄膜晶体管
US6825494B2 (en) Polycrystalline silicon thin film used in a thin film transistor and a device using the same
CN1636162A (zh) 薄膜晶体管和液晶显示器
CN1542707A (zh) 具有薄膜晶体管的平板显示器
JP4361769B2 (ja) Ldd/オフセット構造を具備している薄膜トランジスター
KR100552958B1 (ko) 다결정 실리콘 박막 트랜지스터를 포함하는 평판 표시소자 및 그의 제조 방법
CN100361283C (zh) 制造使用双重或多重栅极的薄膜晶体管的方法
CN1276400C (zh) 平板显示器
CN1503376A (zh) 薄膜晶体管和使用该薄膜晶体管的有机电致发光设备
CN1622178A (zh) 有源矩阵型显示器及其制造方法
KR100542991B1 (ko) 다결정 실리콘 박막 트랜지스터를 포함하는 평판 표시 소자
CN100501547C (zh) 具有多晶硅薄膜晶体管的平板显示装置
KR100534576B1 (ko) 다중 게이트를 갖는 박막 트랜지스터
KR101246572B1 (ko) 박막트랜지스터의 제조방법
KR100507345B1 (ko) 엘디디 구조를 구비하고 있는 박막 트랜지스터 및 이를사용하는 평판 표시 소자
KR100542992B1 (ko) 다결정 실리콘 박막 트랜지스터를 포함하는 평판 표시 소자
KR100637430B1 (ko) 다결정 실리콘 박막 트랜지스터를 이용한 평판 표시 장치및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090109

Address after: Gyeonggi Do, South Korea

Patentee after: Samsung Mobile Display Co.,Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: Samsung SDI Co.,Ltd.

ASS Succession or assignment of patent right

Owner name: SAMSUNG MOBILE DISPLAY CO., LTD.

Free format text: FORMER OWNER: SAMSUNG SDI CO., LTD.

Effective date: 20090109

ASS Succession or assignment of patent right

Owner name: SAMSUNG MONITOR CO., LTD.

Free format text: FORMER OWNER: SAMSUNG MOBILE DISPLAY CO., LTD.

Effective date: 20121026

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20121026

Address after: Gyeonggi Do, South Korea

Patentee after: SAMSUNG DISPLAY Co.,Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: Samsung Mobile Display Co.,Ltd.

CX01 Expiry of patent term

Granted publication date: 20060405

CX01 Expiry of patent term