CN1486504A - 用于低k工艺的铜通孔的铬粘结层 - Google Patents
用于低k工艺的铜通孔的铬粘结层 Download PDFInfo
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Abstract
在具有铜互连(30，50)和低k层间介质(40)的集成电路中，发现热处理后的断路问题，通过Cr第一衬层(42)、随后CVD TiN保形衬层(46)、依次随后的Ta或TaN最终衬层(48)解决该问题，从而提高通孔(50)和下层的铜层(30)之间的粘附力，同时保持低电阻。
Description
技术领域
本发明的领域是形成具有铜金属化和低k电介质的集成电路的领域。
背景技术
在具有氧化物的铜领域中，现有技术已经开发了一组相容材料，以形成包含铜的沟槽和穿孔的衬里。衬里(lining)必须粘结到粘附在电介质上并阻止扩散以及电迁移。
通常，在氧化物介质电路中，双镶嵌结构(dual damascenestructure)结合连接到下层平面的通孔与水平互连部件，并包括Ta或TaN的粘结层、防止铜扩散的TaN阻挡层以及在铜籽晶淀积之前的Ta或TaN顶层。
当半导体器件的尺寸继续缩小时，金属互连的RC延迟成为器件速度的主要限制因素。为了解决该问题，在低k介质材料(减小金属线路之间的电容C)中进行铜互连(减小电阻R)成为半导体工业将器件缩小为深亚微米尺寸的关键问题。
进行铜低k金属化工艺最经济的方法是使用具有金属通孔和金属线路的双镶嵌结构，在一个工序中腐蚀和用铜金属填充通孔和金属线路。通过CMP(化学机械抛光)除去过量的铜。在双镶嵌结构中，金属通孔和金属线路都需要铜金属和介质材料之间的阻挡层(或多层)。该阻挡层称为衬层(liner)。该衬层有两个作用：作为铜扩散阻挡层，防止铜扩散到介质材料中，作为铜金属通孔和底金属线(由Cu或W组成)之间的接触层。
在SiO2介质(不认为是低k介质材料)中的铜双镶嵌金属化结构领域中，现有技术已经开发了一组用于衬层的可相容材料，例如Ta、TaN以及CVD TiN。已发现Ta具有与Cu金属的良好粘附性，CVDTiN更好地覆盖在线路和通孔的侧壁上，尤其适于高长宽比结构。
但是，在低k介质材料中形成铜金属互连的领域中，产生新的问题：在SiO2介质中的铜金属互连没有对应物(counterpart)。例如，低k介质之一，如SiLK，具有几种不存在于SiO2中的材料性质。SiLK是聚合物材料，且主要由C制成。SiLK还是具有高热膨胀系数的软材料。因为SiLK材料的这些独特特性，对那种材料中的铜金属互连的要求，如通孔侧壁的覆盖以及衬层和底金属(Cu或W金属)之间的粘结，不同于SiO2介质材料中的铜金属中的相应要求。
此外，通孔和金属线的尺寸减小的事实，伴随通孔的长宽比相应增加，在用于双镶嵌结构的衬层方面增加了额外的要求。
发明内容
本发明涉及使用低k电介质的铜互连电路的结构和材料的结合，提供通孔的底部和下层的铜互连部件之间的所需粘结，以及足够低的电阻。
本发明的特点是通孔底部处的Cr衬层和下层的互联之间的粘附力足以承受由热循环所引起的应力。
本发明另一特点是通过Cr层的吸气作用减小通孔底部处的碳污染。
附图说明
图1示出根据本发明的部分互连。
图2示出根据现有技术的部分互连。
具体实施方式
在测试结合铜金属化和低k电介质(例如来自Dow的SiLK)的集成电路中，发现一个意外的问题。
与具有氧化物层间介质的铜互连的现有技术工作比起来，在热循环发生后具有断开通孔的不能接受的高失效率。
发现该问题的原因是通孔底部和下层的铜部件之间机械分开。
该问题只能在通孔的横向尺寸缩小(和它们的长宽比增加)时产生。
现在参考图2，示出了根据现有技术的典型通孔。下层的介质层20放置在硅衬底10上。第一铜层30从左向右延伸。常规阻挡层32，称为覆盖层，如SiN，淀积在铜层30上。
在图的中心，通孔从铜层50向下延伸与层30接触。用CVD TiN衬层62和Ta(和/或TaN)衬层64的常规组合形成铜的衬里。在说明性的实施例中，对于具有200nm标称基准(ground rule)的工艺，层40的厚度标称为300nm，通孔尺寸标称为200nm乘200nm，长宽比标称为3.5。当尺寸缩小时，长宽比(因此通孔底端的键合应变)将增加。
已经发现这些组合，尽管在任何热应力之前令人满意，但是在-65℃和200℃之间重复热循环后，产生不能接受的高失效率。该失效率的原因已确定为通孔底部机械分开。SiLK的热膨胀系数比铜大五倍，以致当电路温度上升时，层间电介质在通孔底端的结点上施加大的应力。
该分开的一个可疑原因是腐蚀和清洁通孔的先前步骤过程中从低k电介质放出碳(放气)。这些碳通过常规清洁工艺如溅射清洁不能完全除去，并妨碍铜的顶面和衬层底面之间形成良好键合。此外，当晶片暴露于空气时，氧可以被吸附在通孔露出的底部上。这些效应的结合削弱了Ta和/或TaN与铜之间的键合，且在热应力条件下产生断路的现象。在铜互连和低k电介质的有益特点的结合中这产生了难题。
现在参考图1，展示了本发明的实施例，其中用溅射的Cr第一衬层42代替衬层62和64，在通孔底部处标称为10-20nm厚。当溅射的Cr没有很好地覆盖垂直表面时，侧面上的Cr覆盖小于底端。已经发现Cr对有机材料例如SiLK的粘结性好。在过去的集成电路封装领域中，Cr用作铜上的粘结层，其中没有使用有机材料，且尺寸和应力完全不同于集成电路技术。
然后，在标准条件淀积标称为5nm-10nm厚的CVD TiN(通过化学气相淀积进行淀积)衬层46。该层是保形的且补偿第一层覆盖的欠缺。TiN也很好地粘结到SiLK，从而如果在通孔壁上有任何露出的SiLK表面，那里仍很好地粘结在壁上。
衬层的最终层是Ta层48，标称25nm厚，用来增强TiN衬层和铜互连部件之间的键合。也可以使用TaN。
试验结果表明根据本发明的通孔结构显著地减小失效率。在操作中，按常规淀积和构图第一铜互连层(优选用镶嵌结构)。也按常规淀积介质的第一层。然后，优选在双镶嵌工艺中，腐蚀一组穿过层间绝缘材料的通孔。放置一组三个衬层，如果愿意，通过常规的CMP除去沟道外部的第二铜层。
放置和构图第二铜层。需要时重复该工艺直到所有铜层都放置。
可选实施例：
先前的讨论提及三层衬垫。也可以使用本发明的其他实施例。例如：可以使用单个Cr层42，没有TiN或Ta。该实施例放弃TiN的保形覆盖和它作为扩散阻挡层的性能。该实施例具有成本更低的优点，但是比CVD TiN更少保形。
另一个实施例是由另外溅射的Cr层代替Ta顶衬层48。这提供对上层的互连铜层的良好粘结且使用更少的材料。
但是另一个层省去TiN层46并保留Ta(或TaN)层48。这比第一实施例将更少保形，但是省去CVD步骤。
在每一个实施例中，通常是常规溅射的铜籽晶层以促进粘结。
尽管已经通过单个优选实施例描述了本发明，但是在权利要求的精神和范围内，本领域的技术人员将认识到本发明可以以各种方式实施。
工业实用性
本发明用于集成电路制造领域。具体在具有铜金属化和低k电介质的集成电路中。
Claims (9)
1.一种在集成电路中形成铜互连的方法，包括以下步骤：
(a)淀积和构图第一铜互连层(30)；
(b)淀积第一低介电常数层间介质层(40)；
(c)形成一组通孔，所述通孔穿过所述的第一低介电常数层间介质层，在所述第一铜互连层上中止。
(d)在所述通孔组内淀积Cr第一衬层(42)；以及
(e)淀积和构图第二铜互连层(50)；
2.根据权利要求1在集成电路中形成铜互连的方法，包括以下附加的步骤：
(d-1)在所述通孔组内淀积CVD TiN第二衬层(46)。
3.根据权利要求2在集成电路中形成铜互连的方法，包括以下附加的步骤：
(d-2)淀积选自Ta和TaN的材料组成的第三衬层(48)。
4.根据权利要求2在集成电路中形成铜互连的方法，包括以下附加的步骤：
(d-2)淀积Cr第三衬层(48)。
5.根据权利要求1在集成电路中形成铜互连的方法，包括以下附加的步骤：
(d-1)淀积选自Ta和TaN的材料组成的第二衬层(46)。
6.根据权利要求1在集成电路中形成铜互连的方法，包括以下附加的步骤：
(d-1)在所述通孔组内淀积CVD TiN第二衬层(46)；以及
(d-2)淀积选自Ta和TaN的材料组成的第三衬层(48)。
7.根据权利要求6的方法，还包括重复所述的步骤(b)至(g)至少一次。
8.根据权利要求6的方法，其中所述的低介电常数层间介质包括SiLK。
9.根据权利要求7的方法，其中所述的低介电常数层间介质包括SiLK。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/759,017 | 2001-01-11 | ||
| US09/759,017 US6539625B2 (en) | 2001-01-11 | 2001-01-11 | Chromium adhesion layer for copper vias in low-k technology |
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| Publication Number | Publication Date |
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| CN1486504A true CN1486504A (zh) | 2004-03-31 |
| CN1263109C CN1263109C (zh) | 2006-07-05 |
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| EP (1) | EP1356498A4 (zh) |
| JP (1) | JP4558272B2 (zh) |
| KR (1) | KR100538748B1 (zh) |
| CN (1) | CN1263109C (zh) |
| TW (1) | TW516203B (zh) |
| WO (1) | WO2002056337A1 (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103260814A (zh) * | 2010-12-30 | 2013-08-21 | 3M创新有限公司 | 使用具有金面层的支撑构件进行激光切割的设备和方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7279411B2 (en) * | 2005-11-15 | 2007-10-09 | International Business Machines Corporation | Process for forming a redundant structure |
| US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
| US7919409B2 (en) * | 2008-08-15 | 2011-04-05 | Air Products And Chemicals, Inc. | Materials for adhesion enhancement of copper film on diffusion barriers |
| US8242600B2 (en) | 2009-05-19 | 2012-08-14 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
| TWI414047B (zh) * | 2010-03-17 | 2013-11-01 | Ind Tech Res Inst | 電子元件封裝結構及其製造方法 |
| US8575000B2 (en) * | 2011-07-19 | 2013-11-05 | SanDisk Technologies, Inc. | Copper interconnects separated by air gaps and method of making thereof |
| US8835306B2 (en) * | 2013-02-01 | 2014-09-16 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits having embedded electrical interconnects |
| JP2021040092A (ja) | 2019-09-05 | 2021-03-11 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| CN110767604B (zh) * | 2019-10-31 | 2022-03-18 | 厦门市三安集成电路有限公司 | 化合物半导体器件和化合物半导体器件的背面铜制程方法 |
| DE102021100529A1 (de) * | 2020-08-13 | 2022-02-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tsv-struktur und verfahren zum bilden davon |
| US11527439B2 (en) | 2020-09-22 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | TSV structure and method forming same |
Family Cites Families (12)
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| US4396900A (en) | 1982-03-08 | 1983-08-02 | The United States Of America As Represented By The Secretary Of The Navy | Thin film microstrip circuits |
| US5917707A (en) * | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
| JPS6341049A (ja) * | 1986-08-05 | 1988-02-22 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | ヴアイア接続を有する多層回路 |
| US5153986A (en) | 1991-07-17 | 1992-10-13 | International Business Machines | Method for fabricating metal core layers for a multi-layer circuit board |
| US5231751A (en) * | 1991-10-29 | 1993-08-03 | International Business Machines Corporation | Process for thin film interconnect |
| US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
| US5503286A (en) | 1994-06-28 | 1996-04-02 | International Business Machines Corporation | Electroplated solder terminal |
| TW369672B (en) * | 1997-07-28 | 1999-09-11 | Hitachi Ltd | Wiring board and its manufacturing process, and electrolysis-free electroplating method |
| US6265779B1 (en) * | 1998-08-11 | 2001-07-24 | International Business Machines Corporation | Method and material for integration of fuorine-containing low-k dielectrics |
| JP3481877B2 (ja) * | 1999-02-25 | 2003-12-22 | 日本電信電話株式会社 | 配線構造およびその製造方法 |
| US6245655B1 (en) * | 1999-04-01 | 2001-06-12 | Cvc Products, Inc. | Method for planarized deposition of a material |
| US6263566B1 (en) * | 1999-05-03 | 2001-07-24 | Micron Technology, Inc. | Flexible semiconductor interconnect fabricated by backslide thinning |
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- 2001-12-13 CN CNB018219020A patent/CN1263109C/zh not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103260814A (zh) * | 2010-12-30 | 2013-08-21 | 3M创新有限公司 | 使用具有金面层的支撑构件进行激光切割的设备和方法 |
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| Publication number | Publication date |
|---|---|
| KR20040012705A (ko) | 2004-02-11 |
| TW516203B (en) | 2003-01-01 |
| CN1263109C (zh) | 2006-07-05 |
| US20020088117A1 (en) | 2002-07-11 |
| WO2002056337A1 (en) | 2002-07-18 |
| EP1356498A1 (en) | 2003-10-29 |
| US6539625B2 (en) | 2003-04-01 |
| KR100538748B1 (ko) | 2005-12-26 |
| EP1356498A4 (en) | 2009-05-13 |
| JP2004523891A (ja) | 2004-08-05 |
| JP4558272B2 (ja) | 2010-10-06 |
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