TW516203B - Chromium adhesion layer for copper vias in low-k technology - Google Patents

Chromium adhesion layer for copper vias in low-k technology Download PDF

Info

Publication number
TW516203B
TW516203B TW091100147A TW91100147A TW516203B TW 516203 B TW516203 B TW 516203B TW 091100147 A TW091100147 A TW 091100147A TW 91100147 A TW91100147 A TW 91100147A TW 516203 B TW516203 B TW 516203B
Authority
TW
Taiwan
Prior art keywords
layer
depositing
copper wire
patent application
forming
Prior art date
Application number
TW091100147A
Other languages
English (en)
Inventor
Brett H Engel
Mark Hoinkis
John A Miller
Soon-Cheon Seo
Yun-Yu Wang
Original Assignee
Ibm
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Infineon Technologies Corp filed Critical Ibm
Application granted granted Critical
Publication of TW516203B publication Critical patent/TW516203B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

516203
發明領域 本發明之領域為形成具有銅金屬化和低k介電質的積體 電路。 發明背景 在銅與氧化物的領域中，該技藝己開發出_組相容材 料，以鑲襯含銅的溝渠和通孔。鑲襯物必須黏附於介電質 •上’並阻止擴散和電致遷移。 傳統上，在氧化物介電質電路中，將連接至下層的通孔 與一水平導線構件組合在一起的雙鑲嵌結構包含由丁&或
TaN構成的黏附層、·由TaN構成，以防止銅擴散的障礙 裝 層，以及在Cu種子沈積之前，由Ta4lraN構成的頂層。 、當半導體裝置的尺寸持續縮小時，其金屬導線的^延 遲變成裝置速率的主要限制因素。為解決此問題，在一低 訂 k介電材料（降低金屬導線之間的電容值c)内實作銅導線 (降低電阻值H) ’成為半導體工業將裝置縮小至深次微米 尺寸時的關鍵性問題。 實現銅低k金屬化製程最經濟的方式為使用一雙鑲嵌結 構，並於某-製程步驟中姓刻金屬通孔和金屬導線，並填 以Cu金屬。多餘的Cu#CMp(化學機械研磨）法除去。 =嵌結構中，對於金屬通孔和金屬導線而言，U金^ 2材枓之間需要一層（或多層）障礙層。此障礙層亦稱為 ’㈣物。報襯物有兩個功能：t*Cu擴散的障礙物，可防 ‘政5丨1私材料内，也是C u金屬通孔與下層金屬導 、”（可由Cu或W製成）之間的接觸層。 才 芘張尺度適用格(21〇χ297公着) 516203 A7 B7 五、發明説明（ 在「31〇2介負内的C u雙鑲嵌金屬化結構」的領域中（吾 人並不將此介電質視為低k介電材料），以往技藝已開發出 一組用於鑲襯物的相容材料，例如T a、τ aN和CVD T i N。 吾人也已發現T a對C u金屬的黏附性很好，而CVD 丁 i N在 導線和通孔側壁上的覆蓋性較佳，特別是對高寬比很大的 結構。 .然而’ 「在低k介電材料内形成c u金屬導線」領域中已 產生了新的問題，這些問題在「&〇2介質内的c u金屬導 線」中並無對應的問題。例如某一種低k介電質（例如SiLK) 有一些在Si02中並不存在的材料性質。siLK為一聚合物材 料主要疋由C構成。SiLK也是一種軟材料，其熱膨脹係 數非常南。由於SiLK材料的這些獨特性質，該材料中之c u 金屬導線的要求，例如通孔側壁的覆蓋性，以及鑲襯層與 下層金屬(―Cu或W金屬）之”間的黏附性，與Si〇2介電材料内 C u金屬化的對應要求不同。 此外，通孔及金屬導線的尺寸正在縮小，且通孔的高寬 比相對增加的事實，也對雙鑲嵌結構的鑲襯物增加了額外 的要求。 本I明係關於一種材料與結構的組合，此組合係針對使 用低k介電質的銅導線電路’它提供通孔底部與下方銅導 線構件之間所需的黏附性，並提供足夠低的電阻值。 本發明的特色之一為通孔底部的C r鑲襯層與下方銅導線 構件之間的黏附性足以抵抗熱循環造成的應力。 516203 A7 B7
五、發明説明（ 本發明的另一特色為吾人藉由一 Cr層的吸氣作用而減少 通孔底部上的碳污染。 圖式簡述 圖1顯示根據本發明之導線的一部分。 圖2顯示根據以往技藝之導線的一部分。 k j圭具體复例的詳細描述 .在測武將銅金屬化與低k介電質（例如D 〇 w出品的SiLK) 組合的積體電路時，吾人發現一意料之外的問題。 相較於在「銅導線與氧化物層間介電質」方面的以往技 r 藝工作，通孔在熱循環後發生了開路現象，其失敗率高得 令人不能接受。 吾人已發現問題的原因為通孔底部與下層鋼構件之間的 機械分離。 當通孔橫向尺寸縮小（以及其高寬比增加）時，此問題 只會更嚴重。 現在參閱圖2，其中顯示一根據以往技藝的典型通孔。 下方介電層20置於矽基板10上。第一銅層3〇從左邊延伸 到右邊。一傳統的障礙層3 2，亦稱為覆蓋層（例如s iN)， 已沉積於銅層30上。 在圖的中央，一通孔從銅層50向下延伸，並與層3〇接 觸。吾人以一傳統的CVD TiN鑲襯物62和丁a(及/STaN)鑲 襯物6 4的組合將銅鑲襯。在一示範性具體實施例中，對一 名義上的接線規則為2〇〇奈米的製程而言，層4〇的厚度名 義上為300奈米，通孔的尺寸名義上為2〇〇奈米χ2〇〇奈米，高 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) I比名義上為3.5。當尺寸縮小時，高寬比（以及通孔底部 之鍵結上的張力）會增加。 ^人已喬現此一組合在產生任何熱應力之前很理想，然 而當其在介於_65。(：與2〇〇它之間的重覆熱循環之後，會造 成鬲得不能接受的失敗率。吾人已發現失敗率的原因為通 =展部的機械分離。SiLK的熱膨脹係數比銅大五倍，因此 ‘田電路的溫度上升時，層間·介電質會對通孔底部的人 施加很大的應力。 造成分離的可疑原因之-是因為在先前#刻與清潔通孔 的製程中，碳從低1^介電質放出（逸出）。傳統的清潔過程 (例如噴滅清潔法）並未將這些碳完全除去’它們會干擾_ 的上表面及鑲襯物下方表面之間良好鍵結的形成。此外， 當晶圓暴露於空氣中時，氧會吸附在暴露出來的通孔底部 上ϋ匕效應的組合，+Ta及/或丁aN與銅之間的鍵結變 弱’並產生在熱應力下造成電路開路的現象。《已造成組 合銅導線與低k介電質之優良特性時的難題。 / 現在參閱圖1 ’顯示本發明的一具體實施例，其中在诵 ::的底部’鑲襯物62和64已被取代為由賤鍍的C:構成的 ^ .襄襯物4 2厚度名義上為j 〇〜2 〇奈米。c r在側邊的覆 蓋率將較底部為低，因為濺鍵的對垂直表面的ρ性^ 佳。以往在電路封裝領域中，〇已被使用為銅上:黏附 層’其中並未使用有機材料’且其尺寸及應力與積體電路 技蟄完全不同。 其次， 吾人在標準狀態下沉積一 名義上為5奈米到1 〇奈 516203
米厚的CVD ΤιΝ(以化學氣相沉積法沉積）$。此層具有保形 7並可彌補第一層缺少的覆蓋性。TiN對SiLK的黏附性也 很予口此即使通孔壁上有任何敞開的SiLK表面，壁上的 黏附性仍然很好。 €襯物的最後一層為_丁 &層，名義上為奈米厚， ，、功用為增進丁 lN鑲襯物與C u導線構件之間的鍵結。亦 可使用TaN。 貝驗〜果_ 7F ·根據本發明建造的通孔，其失敗率已劇 降。 在铋作時，第一層銅導線照常沉積與製作圖案（最好在 :鑲嵌結構内）。第一層介電質亦照常沉積。纟次，吾人 最好在雙鑲肷製程内蝕刻層間介電質，將其貫穿而產生 一組通孔。一組三層鑲襯層已放下，且若吾人希望的話， 並以傳統的CMP方法除去通道外的鑲襯層，俾供第二銅層 之用。 3 吾人放下第二層銅，並製作圖案。製程將視需要而重 複，直到所有的銅層都被放下。 !一種具體f 瓦面的討論係針對三層的鑲襯物。吾人亦可使用本發明 的其他具體實施例。例如，吾人可使用單一的C r層4 2，而 不使用TiN或丁a。此具體實施例放棄了 TiN的保形性覆蓋 及其身為擴散障礙層的品質。此具體實施例具有成本較低 的優點’但其保形性不如CVD TiN。 另一具體實施例係以另一濺鍍C r層取代T a頂端鑲襯層 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
)1()203
48。這樣可以提供對導線上層銅層的良好黏附性，且使用 的材料較少。 另一種層不使用TiN層46 ,並保留Ta(或TaN)層48。 其保形性不如第一具體實施例，但可略去cv〇步驟。 在每-具體實施例中’通常會有一傳統的濺鍍銅種子 層，以改進黏附性。 .雖然本|明係針對單-較佳具體實施例而描㉛，熟悉本 技藝的人士將理解吾人可在下列申纟杳森 仏P〜肀叫寻利軏圍的精神與範 寿 < 内，以任何版本來實行本發明。

Claims (1)

  1. 516203 A8 B8 C8 D8 六、 申請專利範圍 1· 一種在積體電路中形成鋼導線的方法，包含下列步驟： (a) 沉積並圖案化一第—鋼導線層； (b) 沉積一第一層低介電常數的層間介電質； (c) 經由該第一層低介電常數的層間介電質形成/麵 通孔，並止於該銅導線的第一層上； (d) 在该組通孔内沉積一第一 Cr鑲襯層，·以及 (e) 沉積並圖案化一第二銅導線層。 2。如申請專利範圍第1項在積體電路中形成銅導線的方 法，包含額外步驟： (d- 1)在該組通孔中沉積由cv〇 丁沉構成的第二鑲襯 層。 3·如申請專利範圍第2項在積體電路中形成銅導線的方 法，包含額外步驟： (d-2)_沉積一從Ta*TaN構成的群組中選出之第三鑲 襯層。 *·如申請專利範圍第2項在積體電路中形成銅導線的方 法，包含額外步驟： (d-2)沉積一由以構成的第三鑲襯層。 方 5.如申請專利範圍第η在積體電路中形成銅導線的 法，包含額外步驟： 鑲 (d-Ι)沉積一&Ta和丁 aN構成的群組中選出之第二 襯層。 ~ 5· -種在積體電路中形成銅導線的方法，包含下列步驟 (a)沉積並圖案化一第一銅導線層； ίΑ -11 - 本紙張尺歧財® β家標準(c^ii^_X297公爱) 516203
    (b ) /儿積一弟一層低介電常數的層間介電質· (c) 經由該第一層低介電常數的層間介電質形成一組 通孔，並止於該銅導線的第一層上； (d) 在該組通孔内沉積一第一 c r鑲襯層； (e) 在該組通孔内沉積一第二cvd TiN鑲襯層； (f) 沉積一從T a和T aN構成的群組中選出之第三镶觀 層；以及 (g) 沉積一第二銅導線層，並製作圖案。 7.如申請專利範圍第6項的方法，尚包含重複該步驟（b)到 (g)至少一次。 8·如申請專利範圍第6項的方法，其中該低介電常數的層 間介電質含有SiLK。 9·如申請專利範圍第7項的方法，其中該低介電常數的層 間介電質含有SiLK。 -12 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
TW091100147A 2001-01-11 2002-01-08 Chromium adhesion layer for copper vias in low-k technology TW516203B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/759,017 US6539625B2 (en) 2001-01-11 2001-01-11 Chromium adhesion layer for copper vias in low-k technology

Publications (1)

Publication Number Publication Date
TW516203B true TW516203B (en) 2003-01-01

Family

ID=25054065

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091100147A TW516203B (en) 2001-01-11 2002-01-08 Chromium adhesion layer for copper vias in low-k technology

Country Status (7)

Country Link
US (1) US6539625B2 (zh)
EP (1) EP1356498A4 (zh)
JP (1) JP4558272B2 (zh)
KR (1) KR100538748B1 (zh)
CN (1) CN1263109C (zh)
TW (1) TW516203B (zh)
WO (1) WO2002056337A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI720936B (zh) * 2019-10-31 2021-03-01 大陸商廈門市三安集成電路有限公司 化合物半導體元件及其背面銅製程方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279411B2 (en) * 2005-11-15 2007-10-09 International Business Machines Corporation Process for forming a redundant structure
US7892972B2 (en) * 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US7919409B2 (en) * 2008-08-15 2011-04-05 Air Products And Chemicals, Inc. Materials for adhesion enhancement of copper film on diffusion barriers
US8242600B2 (en) 2009-05-19 2012-08-14 International Business Machines Corporation Redundant metal barrier structure for interconnect applications
TWI414047B (zh) * 2010-03-17 2013-11-01 Ind Tech Res Inst 電子元件封裝結構及其製造方法
SG191244A1 (en) 2010-12-30 2013-07-31 3M Innovative Properties Co Apparatus and method for laser cutting using a support member having a gold facing layer
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
US8835306B2 (en) * 2013-02-01 2014-09-16 GlobalFoundries, Inc. Methods for fabricating integrated circuits having embedded electrical interconnects
JP2021040092A (ja) 2019-09-05 2021-03-11 キオクシア株式会社 半導体装置およびその製造方法
DE102021100529A1 (de) * 2020-08-13 2022-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Tsv-struktur und verfahren zum bilden davon
US11527439B2 (en) 2020-09-22 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. TSV structure and method forming same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4396900A (en) 1982-03-08 1983-08-02 The United States Of America As Represented By The Secretary Of The Navy Thin film microstrip circuits
US5917707A (en) * 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
JPS6341049A (ja) * 1986-08-05 1988-02-22 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン ヴアイア接続を有する多層回路
US5153986A (en) 1991-07-17 1992-10-13 International Business Machines Method for fabricating metal core layers for a multi-layer circuit board
US5231751A (en) * 1991-10-29 1993-08-03 International Business Machines Corporation Process for thin film interconnect
US6336269B1 (en) * 1993-11-16 2002-01-08 Benjamin N. Eldridge Method of fabricating an interconnection element
US5503286A (en) 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
TW369672B (en) * 1997-07-28 1999-09-11 Hitachi Ltd Wiring board and its manufacturing process, and electrolysis-free electroplating method
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
JP3481877B2 (ja) * 1999-02-25 2003-12-22 日本電信電話株式会社 配線構造およびその製造方法
US6245655B1 (en) * 1999-04-01 2001-06-12 Cvc Products, Inc. Method for planarized deposition of a material
US6263566B1 (en) * 1999-05-03 2001-07-24 Micron Technology, Inc. Flexible semiconductor interconnect fabricated by backslide thinning

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI720936B (zh) * 2019-10-31 2021-03-01 大陸商廈門市三安集成電路有限公司 化合物半導體元件及其背面銅製程方法

Also Published As

Publication number Publication date
KR20040012705A (ko) 2004-02-11
CN1263109C (zh) 2006-07-05
US20020088117A1 (en) 2002-07-11
WO2002056337A1 (en) 2002-07-18
CN1486504A (zh) 2004-03-31
EP1356498A1 (en) 2003-10-29
US6539625B2 (en) 2003-04-01
KR100538748B1 (ko) 2005-12-26
EP1356498A4 (en) 2009-05-13
JP2004523891A (ja) 2004-08-05
JP4558272B2 (ja) 2010-10-06

Similar Documents

Publication Publication Date Title
TWI234231B (en) Reliable low-k interconnect structure with hybrid dielectric
TWI222170B (en) Interconnect structures containing stress adjustment cap layer
US8178437B2 (en) Barrier material and process for Cu interconnect
TW516203B (en) Chromium adhesion layer for copper vias in low-k technology
US20070059919A1 (en) Method of manufacturing semiconductor device
WO2006046487A1 (ja) 半導体装置および半導体装置の製造方法
JP2009105289A (ja) Ｃｕ配線の形成方法
TWI241631B (en) Method for dual-damascene patterning of low-k interconnects using spin-on distributed hardmask
KR20000012027A (ko) 반도체장치의제조방법
TW293162B (zh)
TWI245365B (en) Copper vias in low-k technology
US8338952B2 (en) Interconnect structures with ternary patterned features generated from two lithographic processes
TW200531208A (en) Damascene process for fabricating interconnect layers in an integrated circuit
TW202320131A (zh) 具有減法金屬蝕刻之二維自對準方案
JP2001053151A (ja) 半導体集積回路装置およびその製造方法
TWI227040B (en) Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same
TWI239055B (en) Ti liner for copper interconnect with low-k dielectric
JPH04242960A (ja) 集積回路用配線
US20240332070A1 (en) Etch stop layer for interconnect structures
TW452921B (en) Method for forming etching stop layer in dual damascene processing
TW447075B (en) Method for forming dielectric layer with low dielectric constant
JPH10335330A (ja) 多層溝配線
TW504791B (en) Method of reducing fringe capacitance of metal interconnects
TW434823B (en) Method to form the structure of metal interconnections without cutting angle
Usami et al. Stopper-less Hybrid Low-k/Cu DD structure fabrication combined with Low-k CMP

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees