TW452921B - Method for forming etching stop layer in dual damascene processing - Google Patents

Abstract

The present invention discloses a method for forming a multi-level structure of the etching stop layer/dielectric layer with low dielectric constant/etching stop layer/dielectric layer with low dielectric constant, which includes the following processing steps: first, providing a semiconductor substrate with finished pre-stage integrated circuit processing; next, using trimethylsilane, nitrogen, ammonia as the reaction gas to form a first etching stop layer; then, forming a first dielectric layer with low dielectric constant; and, using trimethylsilane, nitrogen, ammonia as the reaction gas to form the second etching stop layer, and then forming the second dielectric layer with low dielectric constant; in which, the first etching stop layer, the first dielectric layer with low dielectric constant, the second etching barrier and the second dielectric layer with low dielectric constant are all formed by using plasma-enhanced chemical vapor deposition in the same reaction chamber with continuous deposition processing.

Description

452921 V. Description of the invention (1) Technical field: The present invention relates to a method for forming a etching stop layer of a dual damascene process, in particular to a method for forming a layer based on trimethyl Trimethylsilane-based nitride (trimethylsilane) is used as a method of etching a barrier layer in a dual damascene process. Background of the Invention: In order to pursue faster operating speed and greater accumulation density, research units and manufacturers of integrated circuits have devoted all their efforts to designing and manufacturing smaller critical dimension (CD) components. According to experiments, when the integrated circuit manufacturing process enters the technical field of 0.1 8 microns or even 1.3 microns, the key factors affecting the operating speed of components have been shifted from the width of the gate to the metal interconnection. RC del ay effect. Because the resistance of a wire is inversely proportional to its cross-sectional area, as the integrated density of the integrated circuit increases, the line width and thickness of the metal interconnects also decrease, so the resistance value increases accordingly; especially, With the increase of the integrated density of the integrated circuit, the line spacing of the metal interconnects is also reduced, thereby causing the coupling capacitance between the wires to increase. Therefore, after the manufacturing process of the integrated circuit enters the deep sub-micron field, the resistance-capacitance hysteresis of the metal interconnect is greatly improved, which also affects the operation rate and access rate of the integrated circuit. In order to improve the integration density of the integrated circuit, under the condition that the line width and line spacing should not be increased, it is the best choice to replace the material of the metal interconnects and interlayer dielectric layers.

452921 V. Description of the invention (2) In terms of metal interconnects, the metal material is replaced by the original aluminum-silicon-copper alloy or aluminum-copper alloy with copper metal. In addition to its low resistance, it also has good resistance to electron migration and Good stress resistance, in addition to increasing the operating speed of the device, can also improve the reliability of the device; on the other hand, the interlayer dielectric layer must choose a low dielectric constant (D 丨 e 丨 ectric Cons tan t) Material to replace the original silicon dioxide to reduce the capacitance between the metal and the connection. The dielectric constant of silicon dioxide is about 3.9, so a dielectric with a dielectric constant less than 3.9 must be selected as the interlayer dielectric layer in order to achieve the effect of reducing the resistance > capacitance hysteresis, such as: fluorine doped Miscellaneous silica (SiOF), organic spin-on glass (HSQ), etc. Another effective low; 丨 the material of the electrical constant is black diamond, which is formed by the methic si lane, its composition is 20% silicon, 30% oxygen, 9% carbon , Hydrogen 3 6%, and other elements. Because black diamond has about 3 6% of its volume as holes ’, its dielectric constant is only about 2.9, which is a promising low dielectric constant material. In the technology of copper process, because copper metal cannot be etched with gas like aluminum alloy, the industry has developed a dual damascene process method. "Dual damascene process technology can refer to 〇〇〇〇 1 a company Boeck; Bruce Alleη et al. disclosed in the US Patent No. 5 8 0 0 18 1'Method for manufacturing a low dielectric constant inter-level integrated circuit structure ". Please refer to FIG. 1, a first silicon nitride layer 1, a first low-k dielectric layer 12, a second silicon nitride layer 13, and a second low-dielectric layer are continuously formed on a semiconductor substrate 10 that has completed a previous process. Constant dielectric layer 14 '

452921 V. Description of the invention (3) The two lithography and surname engraving techniques are used to form the opening 1 in Figure 1A. The silicon nitride layer 11, 13 is used as an etching barrier layer, and the manufacturing method is based on s 丨 H 4 and N Η as reactive gases, and the plasma enhanced chemical vapor deposition (PECVD) method is used in N. The RF power required to form a thin film of about 500 Angstroms (AngStrom) deposited under the environment is about 400 Watts. The silicon nitride layer formed under the general process conditions has a compressive stress of about 1 E 9 dyne / cm 2, which can be used to offset the large tensile stress of the low dielectric constant dielectric layer. stress). The deposition steps of the first low dielectric constant > dielectric layer 12 and the second low dielectric constant dielectric layer 14 are based on N o and methyl si lane as reaction gases, which are enhanced by electricity. 1 Chemical vapor deposition (PECVD) deposition, where the required rate is about 70 watts, the flow rate of N20 is about 370 seem, the flow rate of methyl sintering is about 6 8 sccm, and the reaction time is about 60. Seconds to form a thin film of diamond of about 5000 angstroms. Next, please refer to FIG. 1B, and a layer of copper film 16 is formed by PVD, CVD, or electromagnetism, + ⑸% fiber method. Finally, as shown in FIG. 1C, the metal thin film i 6 was polished by chemical mechanical polishing (Chemical Mechanical Polishing; CMP) to form copper wires 17. However, the traditional copper wire / low-k dielectric layer is a one-man spear. In the dielectric constant of the first silicon nitride layer and the second gas #aa Α or siliconized layer as the etching barrier layer, the dielectric constant is relatively large, which is between 7.0 and 8. Y & ~ step to reduce the coupling capacitance between metal interconnects. Therefore, the development of an etch barrier layer with a small electric constant has become a very important issue in the semiconductor industry. To this end, companies such as Applied Material have developed β β ‘Α Division—

Page 6 4529 2 1 V. Description of the invention (4) A new process to reduce the dielectric constant of the etch barrier layer. This new process uses trimethy lsi lane plus helium or trimethylsilane plus 1 defect as the reaction emulsion to form a wide range of barriers. Its dielectric constant can be reduced to about 5.1. And it has a δE 8 dyne / cm 2 compressive stress, which indeed has the effect of reducing the dielectric constant. However, if the etching barrier layer formed by the above method is left in the air for 3 days, it will become a thin film with a tensile stress of 1E 9 dyne / cm 2 due to oxidation, which cannot only offset the low dielectric The large tensile stress of the dielectric constant dielectric layer is more likely to cause the cracking and peeling of the etch barrier layer and the low dielectric constant dielectric layer, which seriously affects the yield of the process. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for forming an etch barrier layer in a dual damascene process. A secondary object of the present invention is to provide a method for forming a multilayer structure of an etch barrier layer / low-dielectric-constant dielectric layer / a lithographic barrier layer / low-dielectric-constant dielectric layer. Another object of the present invention is to provide a method for forming a layer of trimethylsilane-based nitride as a etch barrier layer in a dual damascene process. The invention discloses a method for forming a multilayer structure of an etch barrier layer // low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer. The manufacturing process includes the following steps: The semiconductor substrate in the previous stage of the circuit, followed by trimethylsilane, nitrogen and ammonia as reaction gases.

4 5 29 2 1 V. Description of the invention (5) Forming a first etch barrier layer. A first low-k dielectric layer is subsequently formed. Next, using a trifluorenylsilane, nitrogen and ammonia as reaction gases, a second etching barrier layer is formed, and then a second low-k dielectric layer is formed. The first etch barrier layer, the first low-k dielectric layer, the second low-k dielectric layer, and the second low-k dielectric layer are all formed on the same layer using a plasma enhanced chemical vapor deposition method. Deposited continuously in the reaction chamber. The multilayer structure of the silicon nitride layer / low dielectric constant dielectric layer / silicon nitride layer / low dielectric constant dielectric layer formed by the method of the present invention has the following advantages: 1. The etching resistance formed by the present invention The barrier layer is a silicon nitride layer based on trimethylsilane, which has a lower dielectric constant and can effectively reduce the coupling capacitance between metal interconnects; and its compressive stress does not change with time, and can be used to Cancel the tensile stress of the low dielectric constant dielectric layer and avoid the occurrence of peeling. 2. In the present invention, the four deposition processes are continuously performed in the same reaction chamber, which can greatly save the process time, increase the yield and reduce the manufacturing cost. 3. In the present invention, the four deposition processes are continuously performed in the same reaction chamber, and only the reaction gas is changed without turning off the RF RF in the middle, so that the bonding strength between each layer and its upper or lower adjacent layers can be greatly improved. Make the adhesion between the layers even stronger. Drawing number description

Page 8 11-First silicon nitride layer 13-Second silicon nitride layer 1 5-Opening 1 7-Copper wire 3 1-First etched barrier layer 3 3-Second etched barrier layer 3 5- Open 37-copper wire method

452921 Jade and invention description (6) 10-semiconductor substrate 12-first low dielectric constant dielectric layer 14-second low dielectric constant dielectric layer 1 6 -copper film 3 0 -semiconductor substrate 32-first The present invention relates to a method for forming a barrier layer formed by a double-ballasting process, especially a method for forming a low dielectric constant. The constant etch barrier layer is suitable for the dual damascene process of the copper process. The invention can be applied to the copper wire / low-dielectric constant eight integration process of logic elements and memory elements of various states. Please refer to FIG. 2 for the process flow chart of the present invention. First, a semiconductor substrate 21 that has completed the previous process of the bulk circuit is provided. A chemical vapor phase layer is used to form a trimethylsilane-based nitride. ) As the first remaining etching resist layer 22. Next, in the same reaction chamber and without closing the radio frequency RF, N 2 0 and methyl stone Xiyuan form the first ferrite film 23 for the reaction gas vessel. Then In the case of the same reaction chamber and without turning off the RF RF, 'a vapor deposition method was used to form a trimethyl sintered silicon oxide layer based on trimethyl sintering to form the first etched barrier layer 24. Finally in the same React to face without closing RF rf face ::

Page 9 452921 V. Description of the invention (7) ~~, -------- In the case of 'N2〇ί 口 甲' from α m ^ ^ U v. Methylsilane as the reaction gas to form the second black Diamond 溥 film Z 5 to complete the resistance to the M dark ® / 彳 ft eight Φ g barrier layer / low dielectric constant dielectric layer / engraved barrier slip / low dielectric constant age dielectric breakdown Deposition of the telegraph layer.真 和 廄 翁 许 ^ Figure 3A, in which step 22 is based on trimethylsilane and NHa; D, using the chemically enhanced enhanced chemical vapor deposition method (face) "V formed on the semiconductor substrate 30- The layer is based on a trimethylsiloxane scrambled silicon layer as the first etch barrier layer 31 and has a thickness between 300 angstroms and 100 angstroms. The flow rate of the trimethylsilane is Between 30 and 150 SCCm, the best flow is 70 sccm; n 妁 flow is between 1000 and 3500 sccm, and the best flow is 2500 scC [n; NH fishing flow is between 10 and Between lOOsccm, the best flow rate is 30sccm; the power of the radio frequency is between 200 and 80 0 watts. The dielectric constant of the formed film is about 5_2, with about 1. 4 9 E 9 dyne / cm 2 The compressive stress of the silicon nitride layer based on trimethylsilane formed by the present invention does not change with time, which is different from the processes of companies such as Applied Materials. The compressive stress of 1. 4 8 2 E 9 dyne / cm 2 is still maintained. In this way, the etching barrier layer as in the conventional process will not occur after 1 to 3 days. It becomes tensile stress', which causes the cracking and peeling of the etch barrier layer and the low dielectric constant dielectric layer. In addition to the black diamond film, other types of low dielectric constant dielectric layers (for example: fluorine doped two) Silicon oxide (SiOF, organic spin-on glass, etc.) also has great tensile stress. In another embodiment of the present invention, the above can be formed into an etching barrier with compressive stress and low dielectric constant. Layer process applied to any other low-k dielectric layer

Page 10 '1 _ 452921 V. Description of the invention (8) above' to balance the tensile stress of the low dielectric constant dielectric layer and reduce the coupling capacitance between the metal interconnects. Next, as shown in step 23, in the case of the same reaction chamber without turning off the radio frequency, the N 2 substance difluorenyl silane is used as the reaction gas. The diamond film is deposited to form a first black diamond film 32 of about 500 angstroms. Wherein, the flow rate of n20 is between 350 and 40 SCCm, and the optimal flow rate is 37 ° sccm; the flow rate of trimethylsilane is between 50 and 100sCcm, and the optimal flow rate is 68sccin; The optimal response time between 30 seconds and 100 seconds is about 60 seconds. It is particularly important that this step and the above-mentioned step of forming the first etch barrier layer 3 are continuously completed in the same reaction chamber, which can not only save process time, but more importantly, can improve the first etch barrier layer 3 The bond strength between 丨 and the first black diamond film 32 is to increase the adhesion between the two layers and strengthen them. Next, in step 24, in the same reaction chamber without turning off the radio frequency 0, a chemical vapor deposition method is used to form a silicon nitride layer based on trifluorene based silane as the second etching barrier layer. 3 3. In this step, monomethylsilane and NH are used as the reaction gases. The plasma enhanced chemical vapor deposition method (PECVD) is used to form a layer based on trimethyllithium on the first black diamond film 32 under a N-hook environment. The layer of burnt nitride nitride is used as the second-side barrier layer 3 2 ′ whose thickness is between 300 angstroms and 100 angstroms, wherein the flow of J w # ~ dimethylsilane Between 30 to 150 sccm, the optimal flow is 7 η, 1u s ccm-N2 flows from 1 0 0 0 to 3 5 0 0 sccfn, the optimal flow is 2 5 0 0 sccm ; N Η flows between 10 and 1 0 0 sccm, up to $ f

Page 11 452921 V. Description of the invention (9) is 30sccm; the power of radio frequency RF is between 200 and 800 watts. The dielectric constant of the formed film is about 5.2, and it has a compressive stress of about 1.49E 9 dyne / cm 2, and it also does not change over time. It is particularly important that this step and the above-mentioned step of forming the first black diamond film 32 are continuously completed in the same reaction chamber, which can not only save the process time, but more importantly can improve the first black diamond film 32 and The bonding strength between the second etch barrier layers 33 is to make the adhesion between the two layers stronger. Next, as shown in step 25, in the same reaction chamber without closing the RF RF, using N 20 and trimethyl silane as the reaction gas, using plasma enhanced chemical vapor deposition to perform black diamond with RF RF The film is deposited to form a second black diamond film 34 of about 5000 angstroms. Wherein, the flow rate of the N20 is between 350 and 400 sccm, and the optimal flow rate is 370 sccm; the flow rate of the trimethyl stone burner is between 50 and 100 sccm, and the optimal flow rate is 6 8 sccm; Between 30 seconds and 100 seconds, the optimal response time is about 60 seconds. It is particularly important that this step and the above-mentioned step of forming the second etch barrier layer 3 3 are continuously completed in the same reaction chamber, which can not only save the process time, but more importantly, can improve the second etch barrier layer 3 The bonding strength between 3 and the second black diamond film 3 4 makes the adhesion between the two layers stronger. Referring next to FIG. 3B, the opening 35 is formed by two successive lithography and etching techniques. Next, referring to FIG. 3C, a copper thin film 36 is formed by PVD, CVD, or electroplating. Finally, as shown in FIG. 3D, the copper thin film 36 is polished by a chemical mechanical polishing method to form a copper wire 37. Etch barrier layer / low dielectric constant dielectric formed by using the method of the present invention

Page 12 452921 V. Description of the invention (ίο) The multilayer structure of the electrical layer / etch barrier layer / low dielectric constant dielectric layer has the following advantages: 1. The etch barrier layer formed by the present invention is a layer based on three The silicon nitride layer of methyl silane has a lower dielectric constant, which can effectively reduce the coupling capacitance between metal interconnects; and its compressive stress does not change with time, which can offset the low dielectric constant The tensile stress of the electrical layer prevents the occurrence of peeling. 2. In the present invention, the four deposition processes are continuously performed in the same reaction chamber, which can greatly save the process time, increase the yield and reduce the manufacturing cost. 3. In the present invention, the four deposition processes are continuously performed in the same reaction chamber, and only the reaction gas is changed without turning off the RF RF in the middle, so that the bonding strength between each layer and its upper or lower adjacent layers can be greatly improved. Make the adhesion between the layers even stronger. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will also understand that making small changes and adjustments appropriately will still lose the essence of the present invention. Without departing from the spirit and scope of the invention.

Page 13 452921 Brief description of the diagram Brief description of the diagram: Figure 1A is a conventional dual damascene process in which a first silicon nitride layer and a first low dielectric constant dielectric layer are continuously formed on a semiconductor substrate that has completed the previous process. A schematic cross-sectional view of a process of forming an electrical layer, a second silicon nitride layer, and a second low-k dielectric layer, and then using two successive lithography and etching techniques to form an opening. FIG. 1B is a schematic cross-sectional view of a process for forming a copper film in a conventional dual damascene process. FIG. 1C is a schematic cross-sectional view showing a process of grinding the copper thin film by a chemical mechanical polishing method to form a copper wire in a conventional dual damascene process. FIG. 2 is a flow chart of a process for forming a multi-layer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer low dielectric constant dielectric layer according to the present invention. FIG. 3A is the first etch barrier layer, the first low-k dielectric layer, the second etch-barrier layer, and the second low-dielectric layer are continuously formed on a semiconductor substrate that has completed the previous process in the process of the present invention. A schematic cross-sectional view of a process for manufacturing a constant dielectric layer. Figure 3: B is a schematic cross-sectional view of a process of forming an opening by two successive lithography and etching techniques in the process of the present invention. Figure 3C is a schematic cross-sectional view of a process for forming a copper film in the process of the present invention. FIG. 3D is a schematic cross-sectional view of a process of polishing the copper thin film by a chemical mechanical polishing method in the process of the present invention to form a copper wire.

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Claims (1)

452921 6. Scope of patent application 1. A method for forming an etch barrier layer in a dual damascene process. The process method is to use trimethylsilane, nitrogen and ammonia as reaction gases, and use chemical vapor deposition to form a layer based on trimethyl methacrylate. Trimethylsilane-based nitride 0 2. The method for forming an etch barrier layer in a dual damascene process as described in item 1 of the patent application scope, wherein the chemical vapor deposition method is plasma enhanced Chemical vapor deposition (PECVD). 3. The method for forming an etch barrier layer in a dual damascene process as described in item 1 of the scope of the patent application, wherein the flow rate of the trimethylsilane is between 30 and 150 sccm; the flow rate of nitrogen is between 100 and 100 3500 sccm; and the flow rate of ammonia gas is between 10 and 100 sccm. 4. A method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer, suitable for a dual damascene process, the process steps include: a. Provide a semiconductor substrate that has completed the previous stage of the integrated circuit; b. Use trimethylsilyl, nitrogen and ammonia as the reaction gases to form the first #etched barrier layer by chemical vapor deposition method; c. Form the first A low dielectric constant dielectric layer; d. Forming a second etch barrier layer by chemical vapor deposition using trimethylsilane, nitrogen and ammonia as reaction gases; and e. Forming a second low dielectric constant dielectric layer Floor. Page 15 4529 2 1 6. Application for patent scope 5. The formation of etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application The method of multi-layer structure, wherein the first etch barrier layer in step (b) is a layer of trimethylsilane-based nitride. 6. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application, wherein step (b) The flow rate of trimethylsilane is between 30 and 150 sccm; the flow rate of nitrogen is between 150 and 3 50 sccm; and the flow rate of ammonia is between 10 and 50 sccm. between. 7. The method for forming a multilayer structure of an etching barrier layer / low dielectric constant dielectric layer / etching barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application, wherein the first The low-k dielectric layer is a black diamond film. 8. The method of forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 7 of the scope of the patent application, wherein the black diamond The thin film is formed by using N 20 and trimethyl silane as a reaction gas by a chemical vapor deposition method. 9. The method for forming a multilayer structure of an etching barrier layer / low dielectric constant dielectric layer / etching barrier layer / low dielectric constant dielectric layer as described in item 8 of the scope of the patent application, wherein N A flow of 20 is between 3 50 and 4 0 sccm; Page 16 452921 VI. Scope of patent application The flow rate of the kiln-fired kiln fire is between 50 and 100 s c c m. 10. The method for forming a multi-layer structure of an etched barrier layer / low dielectric constant dielectric layer / etched barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application, wherein the steps (D) The second etch barrier layer is a silicon nitride layer based on trimethylsilane. 1 1. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application, wherein step (d The flow rate of trimethylsilyl in) is between 30 and 150 sccm; the flow rate of II gas is between 100 and 3500 sccm; and the flow rate of ammonia gas is between 10 and 100 scc in. 1 2. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / a lithographic barrier layer / low dielectric constant dielectric layer as described in item 4 of the scope of patent application, wherein The second low-k dielectric layer is a black diamond film. 1 3. The method for forming a multi-layer structure of an etch barrier dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 12 of the scope of patent application, wherein the black diamond The thin film is formed by using N 20 and trimethyl silane as a reaction gas by a chemical vapor deposition method. 1 4. The multilayer structure for forming an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 13 of the scope of patent application Page 17 4529 2 ^ VI. Patent application method, wherein the flow rate of N 20 is between 350 and 400 s c c m; the flow rate of trimethyl Shixuan is between 50 and 100 sccm. 1 5. —A method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer, the process steps of which include: a. Provide a completed Semiconductor substrate in the previous stage of the integrated circuit; b. Forming a first barrier layer using trimethyl sulfite, nitrogen and gas as reaction gases; c. Forming a first low-k dielectric layer; d. Trimethylsilane, nitrogen, and ammonia as reaction gases to form a second etch barrier layer; and e. Forming a second low dielectric constant dielectric layer; wherein the first etch barrier layer and the first low dielectric layer The constant dielectric layer, the second silver-etched barrier layer, and the second low dielectric constant dielectric layer are all continuously deposited in the same reaction chamber using a plasma enhanced chemical vapor deposition method. 16. The method for forming a multi-layer structure of a contact barrier layer / low dielectric constant dielectric layer / etching barrier layer / low dielectric constant dielectric layer as described in item 15 of the scope of patent application, which makes The first etch barrier layer described in step (b) is a layer of trimethylsilane-based nitride 0 1 7. The formation of a touch-etching resist as described in item 15 of the scope of patent application Barrier Tang / Low Page 18, 45292 ^ VI. Method for applying a multilayer structure of a dielectric constant dielectric layer / etching barrier layer / low dielectric constant dielectric layer in a patent application range, in which the flow rate of trimethylsilane in step (b) is between 3 Between 0 and 150 sccm; the flow rate of nitrogen is between 100 0 and 3500 sccm; and the flow rate of gas is between 10 and 100 sccm. 18. The method for forming a multilayer structure of an etching barrier layer / low dielectric constant dielectric layer / etching barrier layer / low dielectric constant dielectric layer as described in item 15 of the scope of patent application, wherein The first low-k dielectric layer is a black diamond film. 1 9. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 18 of the scope of patent application, wherein The black diamond film is formed by chemical vapor deposition method using N 2 0 and trimethylsilyl as reaction gases. 20. The method for forming a #etched barrier layer / low-dielectric constant dielectric layer / etched barrier layer / low-dielectric constant dielectric layer multi-layer structure as described in item 19 of the scope of patent application, wherein The flow rate of the N 2O is between 350 and 400 sccm; the flow rate of the sulphur-based sintered stone is between 50 and 100 sccm. 2 1. The method for forming a multi-layered structure of the etched barrier layer / low dielectric constant dielectric layer / shoe etched barrier layer / low dielectric constant dielectric layer as described in item 15 of the scope of patent application, wherein The second etch barrier layer in step (d) is a silicon nitride layer based on trimethylsilane. Page 19, 452921 6. Application for patent scope 2 2. Formation of etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 15 of patent application scope Multi-layer structure method, in which the flow rate of trimethylsilyl in step (d) is between 30 and 150 sccm; the flow rate of nitrogen is between 100 and 3500 sccm; and the flow rate of ammonia is between 10 and 100 sccm between. 2 3. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 15 of the scope of patent application, wherein The second low-k dielectric layer is a black diamond film. 2 4. The method for forming a multilayer structure of an etch barrier layer / low dielectric constant dielectric layer / etch barrier layer / low dielectric constant dielectric layer as described in item 23 of the scope of patent application, wherein The black diamond film is formed by chemical vapor deposition method using N 20 and trimethyl silane as reaction gases. 25. The method for forming a multilayer structure of etched barrier layer Δ's dielectric constant dielectric layer / etched barrier layer / low dielectric constant dielectric layer as described in item 24 of the scope of patent application, wherein The flow rate of N 20 is between 350 and 400 seem; the flow rate of trimethylsilane is between 50 and 100 seem. Page 20